1be462c97SLizhi Hou /* SPDX-License-Identifier: GPL-2.0 */ 2be462c97SLizhi Hou /* 3be462c97SLizhi Hou * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4be462c97SLizhi Hou */ 5be462c97SLizhi Hou 6be462c97SLizhi Hou #ifndef _AMDXDNA_CTX_H_ 7be462c97SLizhi Hou #define _AMDXDNA_CTX_H_ 8be462c97SLizhi Hou 9*aac24309SLizhi Hou #include <linux/bitfield.h> 10*aac24309SLizhi Hou 11*aac24309SLizhi Hou #include "amdxdna_gem.h" 12*aac24309SLizhi Hou 13*aac24309SLizhi Hou struct amdxdna_hwctx_priv; 14*aac24309SLizhi Hou 15*aac24309SLizhi Hou enum ert_cmd_opcode { 16*aac24309SLizhi Hou ERT_START_CU = 0, 17*aac24309SLizhi Hou ERT_CMD_CHAIN = 19, 18*aac24309SLizhi Hou ERT_START_NPU = 20, 19*aac24309SLizhi Hou }; 20*aac24309SLizhi Hou 21*aac24309SLizhi Hou enum ert_cmd_state { 22*aac24309SLizhi Hou ERT_CMD_STATE_INVALID, 23*aac24309SLizhi Hou ERT_CMD_STATE_NEW, 24*aac24309SLizhi Hou ERT_CMD_STATE_QUEUED, 25*aac24309SLizhi Hou ERT_CMD_STATE_RUNNING, 26*aac24309SLizhi Hou ERT_CMD_STATE_COMPLETED, 27*aac24309SLizhi Hou ERT_CMD_STATE_ERROR, 28*aac24309SLizhi Hou ERT_CMD_STATE_ABORT, 29*aac24309SLizhi Hou ERT_CMD_STATE_SUBMITTED, 30*aac24309SLizhi Hou ERT_CMD_STATE_TIMEOUT, 31*aac24309SLizhi Hou ERT_CMD_STATE_NORESPONSE, 32*aac24309SLizhi Hou }; 33*aac24309SLizhi Hou 34*aac24309SLizhi Hou /* 35*aac24309SLizhi Hou * Interpretation of the beginning of data payload for ERT_START_NPU in 36*aac24309SLizhi Hou * amdxdna_cmd. The rest of the payload in amdxdna_cmd is regular kernel args. 37*aac24309SLizhi Hou */ 38*aac24309SLizhi Hou struct amdxdna_cmd_start_npu { 39*aac24309SLizhi Hou u64 buffer; /* instruction buffer address */ 40*aac24309SLizhi Hou u32 buffer_size; /* size of buffer in bytes */ 41*aac24309SLizhi Hou u32 prop_count; /* properties count */ 42*aac24309SLizhi Hou u32 prop_args[]; /* properties and regular kernel arguments */ 43*aac24309SLizhi Hou }; 44*aac24309SLizhi Hou 45*aac24309SLizhi Hou /* 46*aac24309SLizhi Hou * Interpretation of the beginning of data payload for ERT_CMD_CHAIN in 47*aac24309SLizhi Hou * amdxdna_cmd. The rest of the payload in amdxdna_cmd is cmd BO handles. 48*aac24309SLizhi Hou */ 49*aac24309SLizhi Hou struct amdxdna_cmd_chain { 50*aac24309SLizhi Hou u32 command_count; 51*aac24309SLizhi Hou u32 submit_index; 52*aac24309SLizhi Hou u32 error_index; 53*aac24309SLizhi Hou u32 reserved[3]; 54*aac24309SLizhi Hou u64 data[] __counted_by(command_count); 55*aac24309SLizhi Hou }; 56*aac24309SLizhi Hou 57ac49797cSLizhi Hou /* Exec buffer command header format */ 58ac49797cSLizhi Hou #define AMDXDNA_CMD_STATE GENMASK(3, 0) 59ac49797cSLizhi Hou #define AMDXDNA_CMD_EXTRA_CU_MASK GENMASK(11, 10) 60ac49797cSLizhi Hou #define AMDXDNA_CMD_COUNT GENMASK(22, 12) 61ac49797cSLizhi Hou #define AMDXDNA_CMD_OPCODE GENMASK(27, 23) 62ac49797cSLizhi Hou struct amdxdna_cmd { 63ac49797cSLizhi Hou u32 header; 64ac49797cSLizhi Hou u32 data[]; 65ac49797cSLizhi Hou }; 66ac49797cSLizhi Hou 67be462c97SLizhi Hou struct amdxdna_hwctx { 68be462c97SLizhi Hou struct amdxdna_client *client; 69be462c97SLizhi Hou struct amdxdna_hwctx_priv *priv; 70be462c97SLizhi Hou char *name; 71be462c97SLizhi Hou 72be462c97SLizhi Hou u32 id; 73be462c97SLizhi Hou u32 max_opc; 74be462c97SLizhi Hou u32 num_tiles; 75be462c97SLizhi Hou u32 mem_size; 76be462c97SLizhi Hou u32 fw_ctx_id; 77be462c97SLizhi Hou u32 col_list_len; 78be462c97SLizhi Hou u32 *col_list; 79be462c97SLizhi Hou u32 start_col; 80be462c97SLizhi Hou u32 num_col; 81be462c97SLizhi Hou #define HWCTX_STAT_INIT 0 82be462c97SLizhi Hou #define HWCTX_STAT_READY 1 83be462c97SLizhi Hou #define HWCTX_STAT_STOP 2 84be462c97SLizhi Hou u32 status; 85be462c97SLizhi Hou u32 old_status; 86be462c97SLizhi Hou 87be462c97SLizhi Hou struct amdxdna_qos_info qos; 88be462c97SLizhi Hou struct amdxdna_hwctx_param_config_cu *cus; 89be462c97SLizhi Hou u32 syncobj_hdl; 90be462c97SLizhi Hou }; 91be462c97SLizhi Hou 92*aac24309SLizhi Hou #define drm_job_to_xdna_job(j) \ 93*aac24309SLizhi Hou container_of(j, struct amdxdna_sched_job, base) 94*aac24309SLizhi Hou 95*aac24309SLizhi Hou struct amdxdna_sched_job { 96*aac24309SLizhi Hou struct drm_sched_job base; 97*aac24309SLizhi Hou struct kref refcnt; 98*aac24309SLizhi Hou struct amdxdna_hwctx *hwctx; 99*aac24309SLizhi Hou struct mm_struct *mm; 100*aac24309SLizhi Hou /* The fence to notice DRM scheduler that job is done by hardware */ 101*aac24309SLizhi Hou struct dma_fence *fence; 102*aac24309SLizhi Hou /* user can wait on this fence */ 103*aac24309SLizhi Hou struct dma_fence *out_fence; 104*aac24309SLizhi Hou bool job_done; 105*aac24309SLizhi Hou u64 seq; 106*aac24309SLizhi Hou struct amdxdna_gem_obj *cmd_bo; 107*aac24309SLizhi Hou size_t bo_cnt; 108*aac24309SLizhi Hou struct drm_gem_object *bos[] __counted_by(bo_cnt); 109*aac24309SLizhi Hou }; 110*aac24309SLizhi Hou 111*aac24309SLizhi Hou static inline u32 112*aac24309SLizhi Hou amdxdna_cmd_get_op(struct amdxdna_gem_obj *abo) 113*aac24309SLizhi Hou { 114*aac24309SLizhi Hou struct amdxdna_cmd *cmd = abo->mem.kva; 115*aac24309SLizhi Hou 116*aac24309SLizhi Hou return FIELD_GET(AMDXDNA_CMD_OPCODE, cmd->header); 117*aac24309SLizhi Hou } 118*aac24309SLizhi Hou 119*aac24309SLizhi Hou static inline void 120*aac24309SLizhi Hou amdxdna_cmd_set_state(struct amdxdna_gem_obj *abo, enum ert_cmd_state s) 121*aac24309SLizhi Hou { 122*aac24309SLizhi Hou struct amdxdna_cmd *cmd = abo->mem.kva; 123*aac24309SLizhi Hou 124*aac24309SLizhi Hou cmd->header &= ~AMDXDNA_CMD_STATE; 125*aac24309SLizhi Hou cmd->header |= FIELD_PREP(AMDXDNA_CMD_STATE, s); 126*aac24309SLizhi Hou } 127*aac24309SLizhi Hou 128*aac24309SLizhi Hou static inline enum ert_cmd_state 129*aac24309SLizhi Hou amdxdna_cmd_get_state(struct amdxdna_gem_obj *abo) 130*aac24309SLizhi Hou { 131*aac24309SLizhi Hou struct amdxdna_cmd *cmd = abo->mem.kva; 132*aac24309SLizhi Hou 133*aac24309SLizhi Hou return FIELD_GET(AMDXDNA_CMD_STATE, cmd->header); 134*aac24309SLizhi Hou } 135*aac24309SLizhi Hou 136*aac24309SLizhi Hou void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size); 137*aac24309SLizhi Hou int amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo); 138*aac24309SLizhi Hou 139*aac24309SLizhi Hou static inline u32 amdxdna_hwctx_col_map(struct amdxdna_hwctx *hwctx) 140*aac24309SLizhi Hou { 141*aac24309SLizhi Hou return GENMASK(hwctx->start_col + hwctx->num_col - 1, 142*aac24309SLizhi Hou hwctx->start_col); 143*aac24309SLizhi Hou } 144*aac24309SLizhi Hou 145*aac24309SLizhi Hou void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job); 146be462c97SLizhi Hou void amdxdna_hwctx_remove_all(struct amdxdna_client *client); 147*aac24309SLizhi Hou 148*aac24309SLizhi Hou int amdxdna_cmd_submit(struct amdxdna_client *client, 149*aac24309SLizhi Hou u32 cmd_bo_hdls, u32 *arg_bo_hdls, u32 arg_bo_cnt, 150*aac24309SLizhi Hou u32 hwctx_hdl, u64 *seq); 151*aac24309SLizhi Hou 152*aac24309SLizhi Hou int amdxdna_cmd_wait(struct amdxdna_client *client, u32 hwctx_hdl, 153*aac24309SLizhi Hou u64 seq, u32 timeout); 154*aac24309SLizhi Hou 155be462c97SLizhi Hou int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 156be462c97SLizhi Hou int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 157be462c97SLizhi Hou int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 158*aac24309SLizhi Hou int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 159be462c97SLizhi Hou 160be462c97SLizhi Hou #endif /* _AMDXDNA_CTX_H_ */ 161