1*f4d7b8a6SLizhi Hou // SPDX-License-Identifier: GPL-2.0
2*f4d7b8a6SLizhi Hou /*
3*f4d7b8a6SLizhi Hou * Copyright (C) 2024, Advanced Micro Devices, Inc.
4*f4d7b8a6SLizhi Hou */
5*f4d7b8a6SLizhi Hou
6*f4d7b8a6SLizhi Hou #include <drm/amdxdna_accel.h>
7*f4d7b8a6SLizhi Hou #include <drm/drm_device.h>
8*f4d7b8a6SLizhi Hou #include <drm/drm_print.h>
9*f4d7b8a6SLizhi Hou #include <drm/gpu_scheduler.h>
10*f4d7b8a6SLizhi Hou
11*f4d7b8a6SLizhi Hou #include "aie2_pci.h"
12*f4d7b8a6SLizhi Hou #include "amdxdna_pci_drv.h"
13*f4d7b8a6SLizhi Hou
14*f4d7b8a6SLizhi Hou #define AIE2_CLK_GATING_ENABLE 1
15*f4d7b8a6SLizhi Hou #define AIE2_CLK_GATING_DISABLE 0
16*f4d7b8a6SLizhi Hou
aie2_pm_set_clk_gating(struct amdxdna_dev_hdl * ndev,u32 val)17*f4d7b8a6SLizhi Hou static int aie2_pm_set_clk_gating(struct amdxdna_dev_hdl *ndev, u32 val)
18*f4d7b8a6SLizhi Hou {
19*f4d7b8a6SLizhi Hou int ret;
20*f4d7b8a6SLizhi Hou
21*f4d7b8a6SLizhi Hou ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_CLK_GATING, &val);
22*f4d7b8a6SLizhi Hou if (ret)
23*f4d7b8a6SLizhi Hou return ret;
24*f4d7b8a6SLizhi Hou
25*f4d7b8a6SLizhi Hou ndev->clk_gating = val;
26*f4d7b8a6SLizhi Hou return 0;
27*f4d7b8a6SLizhi Hou }
28*f4d7b8a6SLizhi Hou
aie2_pm_init(struct amdxdna_dev_hdl * ndev)29*f4d7b8a6SLizhi Hou int aie2_pm_init(struct amdxdna_dev_hdl *ndev)
30*f4d7b8a6SLizhi Hou {
31*f4d7b8a6SLizhi Hou int ret;
32*f4d7b8a6SLizhi Hou
33*f4d7b8a6SLizhi Hou if (ndev->dev_status != AIE2_DEV_UNINIT) {
34*f4d7b8a6SLizhi Hou /* Resume device */
35*f4d7b8a6SLizhi Hou ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->dpm_level);
36*f4d7b8a6SLizhi Hou if (ret)
37*f4d7b8a6SLizhi Hou return ret;
38*f4d7b8a6SLizhi Hou
39*f4d7b8a6SLizhi Hou ret = aie2_pm_set_clk_gating(ndev, ndev->clk_gating);
40*f4d7b8a6SLizhi Hou if (ret)
41*f4d7b8a6SLizhi Hou return ret;
42*f4d7b8a6SLizhi Hou
43*f4d7b8a6SLizhi Hou return 0;
44*f4d7b8a6SLizhi Hou }
45*f4d7b8a6SLizhi Hou
46*f4d7b8a6SLizhi Hou while (ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk)
47*f4d7b8a6SLizhi Hou ndev->max_dpm_level++;
48*f4d7b8a6SLizhi Hou ndev->max_dpm_level--;
49*f4d7b8a6SLizhi Hou
50*f4d7b8a6SLizhi Hou ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->max_dpm_level);
51*f4d7b8a6SLizhi Hou if (ret)
52*f4d7b8a6SLizhi Hou return ret;
53*f4d7b8a6SLizhi Hou
54*f4d7b8a6SLizhi Hou ret = aie2_pm_set_clk_gating(ndev, AIE2_CLK_GATING_ENABLE);
55*f4d7b8a6SLizhi Hou if (ret)
56*f4d7b8a6SLizhi Hou return ret;
57*f4d7b8a6SLizhi Hou
58*f4d7b8a6SLizhi Hou ndev->pw_mode = POWER_MODE_DEFAULT;
59*f4d7b8a6SLizhi Hou ndev->dft_dpm_level = ndev->max_dpm_level;
60*f4d7b8a6SLizhi Hou
61*f4d7b8a6SLizhi Hou return 0;
62*f4d7b8a6SLizhi Hou }
63*f4d7b8a6SLizhi Hou
aie2_pm_set_mode(struct amdxdna_dev_hdl * ndev,enum amdxdna_power_mode_type target)64*f4d7b8a6SLizhi Hou int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target)
65*f4d7b8a6SLizhi Hou {
66*f4d7b8a6SLizhi Hou struct amdxdna_dev *xdna = ndev->xdna;
67*f4d7b8a6SLizhi Hou u32 clk_gating, dpm_level;
68*f4d7b8a6SLizhi Hou int ret;
69*f4d7b8a6SLizhi Hou
70*f4d7b8a6SLizhi Hou drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
71*f4d7b8a6SLizhi Hou
72*f4d7b8a6SLizhi Hou if (ndev->pw_mode == target)
73*f4d7b8a6SLizhi Hou return 0;
74*f4d7b8a6SLizhi Hou
75*f4d7b8a6SLizhi Hou switch (target) {
76*f4d7b8a6SLizhi Hou case POWER_MODE_TURBO:
77*f4d7b8a6SLizhi Hou if (ndev->hwctx_num) {
78*f4d7b8a6SLizhi Hou XDNA_ERR(xdna, "Can not set turbo when there is active hwctx");
79*f4d7b8a6SLizhi Hou return -EINVAL;
80*f4d7b8a6SLizhi Hou }
81*f4d7b8a6SLizhi Hou
82*f4d7b8a6SLizhi Hou clk_gating = AIE2_CLK_GATING_DISABLE;
83*f4d7b8a6SLizhi Hou dpm_level = ndev->max_dpm_level;
84*f4d7b8a6SLizhi Hou break;
85*f4d7b8a6SLizhi Hou case POWER_MODE_HIGH:
86*f4d7b8a6SLizhi Hou clk_gating = AIE2_CLK_GATING_ENABLE;
87*f4d7b8a6SLizhi Hou dpm_level = ndev->max_dpm_level;
88*f4d7b8a6SLizhi Hou break;
89*f4d7b8a6SLizhi Hou case POWER_MODE_DEFAULT:
90*f4d7b8a6SLizhi Hou clk_gating = AIE2_CLK_GATING_ENABLE;
91*f4d7b8a6SLizhi Hou dpm_level = ndev->dft_dpm_level;
92*f4d7b8a6SLizhi Hou break;
93*f4d7b8a6SLizhi Hou default:
94*f4d7b8a6SLizhi Hou return -EOPNOTSUPP;
95*f4d7b8a6SLizhi Hou }
96*f4d7b8a6SLizhi Hou
97*f4d7b8a6SLizhi Hou ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level);
98*f4d7b8a6SLizhi Hou if (ret)
99*f4d7b8a6SLizhi Hou return ret;
100*f4d7b8a6SLizhi Hou
101*f4d7b8a6SLizhi Hou ret = aie2_pm_set_clk_gating(ndev, clk_gating);
102*f4d7b8a6SLizhi Hou if (ret)
103*f4d7b8a6SLizhi Hou return ret;
104*f4d7b8a6SLizhi Hou
105*f4d7b8a6SLizhi Hou ndev->pw_mode = target;
106*f4d7b8a6SLizhi Hou
107*f4d7b8a6SLizhi Hou return 0;
108*f4d7b8a6SLizhi Hou }
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