1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _AIE2_MSG_PRIV_H_ 7 #define _AIE2_MSG_PRIV_H_ 8 9 enum aie2_msg_opcode { 10 MSG_OP_CREATE_CONTEXT = 0x2, 11 MSG_OP_DESTROY_CONTEXT = 0x3, 12 MSG_OP_SYNC_BO = 0x7, 13 MSG_OP_EXECUTE_BUFFER_CF = 0xC, 14 MSG_OP_QUERY_COL_STATUS = 0xD, 15 MSG_OP_QUERY_AIE_TILE_INFO = 0xE, 16 MSG_OP_QUERY_AIE_VERSION = 0xF, 17 MSG_OP_EXEC_DPU = 0x10, 18 MSG_OP_CONFIG_CU = 0x11, 19 MSG_OP_CHAIN_EXEC_BUFFER_CF = 0x12, 20 MSG_OP_CHAIN_EXEC_DPU = 0x13, 21 MSG_OP_CONFIG_DEBUG_BO = 0x14, 22 MSG_OP_MAX_XRT_OPCODE, 23 MSG_OP_SUSPEND = 0x101, 24 MSG_OP_RESUME = 0x102, 25 MSG_OP_ASSIGN_MGMT_PASID = 0x103, 26 MSG_OP_INVOKE_SELF_TEST = 0x104, 27 MSG_OP_MAP_HOST_BUFFER = 0x106, 28 MSG_OP_GET_FIRMWARE_VERSION = 0x108, 29 MSG_OP_SET_RUNTIME_CONFIG = 0x10A, 30 MSG_OP_GET_RUNTIME_CONFIG = 0x10B, 31 MSG_OP_REGISTER_ASYNC_EVENT_MSG = 0x10C, 32 MSG_OP_MAX_DRV_OPCODE, 33 MSG_OP_GET_PROTOCOL_VERSION = 0x301, 34 MSG_OP_MAX_OPCODE 35 }; 36 37 enum aie2_msg_status { 38 AIE2_STATUS_SUCCESS = 0x0, 39 /* AIE Error codes */ 40 AIE2_STATUS_AIE_SATURATION_ERROR = 0x1000001, 41 AIE2_STATUS_AIE_FP_ERROR = 0x1000002, 42 AIE2_STATUS_AIE_STREAM_ERROR = 0x1000003, 43 AIE2_STATUS_AIE_ACCESS_ERROR = 0x1000004, 44 AIE2_STATUS_AIE_BUS_ERROR = 0x1000005, 45 AIE2_STATUS_AIE_INSTRUCTION_ERROR = 0x1000006, 46 AIE2_STATUS_AIE_ECC_ERROR = 0x1000007, 47 AIE2_STATUS_AIE_LOCK_ERROR = 0x1000008, 48 AIE2_STATUS_AIE_DMA_ERROR = 0x1000009, 49 AIE2_STATUS_AIE_MEM_PARITY_ERROR = 0x100000a, 50 AIE2_STATUS_AIE_PWR_CFG_ERROR = 0x100000b, 51 AIE2_STATUS_AIE_BACKTRACK_ERROR = 0x100000c, 52 AIE2_STATUS_MAX_AIE_STATUS_CODE, 53 /* MGMT ERT Error codes */ 54 AIE2_STATUS_MGMT_ERT_SELF_TEST_FAILURE = 0x2000001, 55 AIE2_STATUS_MGMT_ERT_HASH_MISMATCH, 56 AIE2_STATUS_MGMT_ERT_NOAVAIL, 57 AIE2_STATUS_MGMT_ERT_INVALID_PARAM, 58 AIE2_STATUS_MGMT_ERT_ENTER_SUSPEND_FAILURE, 59 AIE2_STATUS_MGMT_ERT_BUSY, 60 AIE2_STATUS_MGMT_ERT_APPLICATION_ACTIVE, 61 MAX_MGMT_ERT_STATUS_CODE, 62 /* APP ERT Error codes */ 63 AIE2_STATUS_APP_ERT_FIRST_ERROR = 0x3000001, 64 AIE2_STATUS_APP_INVALID_INSTR, 65 AIE2_STATUS_APP_LOAD_PDI_FAIL, 66 MAX_APP_ERT_STATUS_CODE, 67 /* NPU RTOS Error Codes */ 68 AIE2_STATUS_INVALID_INPUT_BUFFER = 0x4000001, 69 AIE2_STATUS_INVALID_COMMAND, 70 AIE2_STATUS_INVALID_PARAM, 71 AIE2_STATUS_INVALID_OPERATION = 0x4000006, 72 AIE2_STATUS_ASYNC_EVENT_MSGS_FULL, 73 AIE2_STATUS_MAX_RTOS_STATUS_CODE, 74 MAX_AIE2_STATUS_CODE 75 }; 76 77 struct assign_mgmt_pasid_req { 78 __u16 pasid; 79 __u16 reserved; 80 } __packed; 81 82 struct assign_mgmt_pasid_resp { 83 enum aie2_msg_status status; 84 } __packed; 85 86 struct map_host_buffer_req { 87 __u32 context_id; 88 __u64 buf_addr; 89 __u64 buf_size; 90 } __packed; 91 92 struct map_host_buffer_resp { 93 enum aie2_msg_status status; 94 } __packed; 95 96 #define MAX_CQ_PAIRS 2 97 struct cq_info { 98 __u32 head_addr; 99 __u32 tail_addr; 100 __u32 buf_addr; 101 __u32 buf_size; 102 }; 103 104 struct cq_pair { 105 struct cq_info x2i_q; 106 struct cq_info i2x_q; 107 }; 108 109 struct create_ctx_req { 110 __u32 aie_type; 111 __u8 start_col; 112 __u8 num_col; 113 __u16 reserved; 114 __u8 num_cq_pairs_requested; 115 __u8 reserved1; 116 __u16 pasid; 117 __u32 pad[2]; 118 __u32 sec_comm_target_type; 119 __u32 context_priority; 120 } __packed; 121 122 struct create_ctx_resp { 123 enum aie2_msg_status status; 124 __u32 context_id; 125 __u16 msix_id; 126 __u8 num_cq_pairs_allocated; 127 __u8 reserved; 128 struct cq_pair cq_pair[MAX_CQ_PAIRS]; 129 } __packed; 130 131 struct destroy_ctx_req { 132 __u32 context_id; 133 } __packed; 134 135 struct destroy_ctx_resp { 136 enum aie2_msg_status status; 137 } __packed; 138 139 struct execute_buffer_req { 140 __u32 cu_idx; 141 __u32 payload[19]; 142 } __packed; 143 144 struct exec_dpu_req { 145 __u64 inst_buf_addr; 146 __u32 inst_size; 147 __u32 inst_prop_cnt; 148 __u32 cu_idx; 149 __u32 payload[35]; 150 } __packed; 151 152 struct execute_buffer_resp { 153 enum aie2_msg_status status; 154 } __packed; 155 156 struct aie_tile_info { 157 __u32 size; 158 __u16 major; 159 __u16 minor; 160 __u16 cols; 161 __u16 rows; 162 __u16 core_rows; 163 __u16 mem_rows; 164 __u16 shim_rows; 165 __u16 core_row_start; 166 __u16 mem_row_start; 167 __u16 shim_row_start; 168 __u16 core_dma_channels; 169 __u16 mem_dma_channels; 170 __u16 shim_dma_channels; 171 __u16 core_locks; 172 __u16 mem_locks; 173 __u16 shim_locks; 174 __u16 core_events; 175 __u16 mem_events; 176 __u16 shim_events; 177 __u16 reserved; 178 }; 179 180 struct aie_tile_info_req { 181 __u32 reserved; 182 } __packed; 183 184 struct aie_tile_info_resp { 185 enum aie2_msg_status status; 186 struct aie_tile_info info; 187 } __packed; 188 189 struct aie_version_info_req { 190 __u32 reserved; 191 } __packed; 192 193 struct aie_version_info_resp { 194 enum aie2_msg_status status; 195 __u16 major; 196 __u16 minor; 197 } __packed; 198 199 struct aie_column_info_req { 200 __u64 dump_buff_addr; 201 __u32 dump_buff_size; 202 __u32 num_cols; 203 __u32 aie_bitmap; 204 } __packed; 205 206 struct aie_column_info_resp { 207 enum aie2_msg_status status; 208 __u32 size; 209 } __packed; 210 211 struct suspend_req { 212 __u32 place_holder; 213 } __packed; 214 215 struct suspend_resp { 216 enum aie2_msg_status status; 217 } __packed; 218 219 struct resume_req { 220 __u32 place_holder; 221 } __packed; 222 223 struct resume_resp { 224 enum aie2_msg_status status; 225 } __packed; 226 227 struct check_header_hash_req { 228 __u64 hash_high; 229 __u64 hash_low; 230 } __packed; 231 232 struct check_header_hash_resp { 233 enum aie2_msg_status status; 234 } __packed; 235 236 struct query_error_req { 237 __u64 buf_addr; 238 __u32 buf_size; 239 __u32 next_row; 240 __u32 next_column; 241 __u32 next_module; 242 } __packed; 243 244 struct query_error_resp { 245 enum aie2_msg_status status; 246 __u32 num_err; 247 __u32 has_next_err; 248 __u32 next_row; 249 __u32 next_column; 250 __u32 next_module; 251 } __packed; 252 253 struct protocol_version_req { 254 __u32 reserved; 255 } __packed; 256 257 struct protocol_version_resp { 258 enum aie2_msg_status status; 259 __u32 major; 260 __u32 minor; 261 } __packed; 262 263 struct firmware_version_req { 264 __u32 reserved; 265 } __packed; 266 267 struct firmware_version_resp { 268 enum aie2_msg_status status; 269 __u32 major; 270 __u32 minor; 271 __u32 sub; 272 __u32 build; 273 } __packed; 274 275 #define MAX_NUM_CUS 32 276 #define AIE2_MSG_CFG_CU_PDI_ADDR GENMASK(16, 0) 277 #define AIE2_MSG_CFG_CU_FUNC GENMASK(24, 17) 278 struct config_cu_req { 279 __u32 num_cus; 280 __u32 cfgs[MAX_NUM_CUS]; 281 } __packed; 282 283 struct config_cu_resp { 284 enum aie2_msg_status status; 285 } __packed; 286 287 struct set_runtime_cfg_req { 288 __u32 type; 289 __u64 value; 290 } __packed; 291 292 struct set_runtime_cfg_resp { 293 enum aie2_msg_status status; 294 } __packed; 295 296 struct get_runtime_cfg_req { 297 __u32 type; 298 } __packed; 299 300 struct get_runtime_cfg_resp { 301 enum aie2_msg_status status; 302 __u64 value; 303 } __packed; 304 305 enum async_event_type { 306 ASYNC_EVENT_TYPE_AIE_ERROR, 307 ASYNC_EVENT_TYPE_EXCEPTION, 308 MAX_ASYNC_EVENT_TYPE 309 }; 310 311 #define ASYNC_BUF_SIZE SZ_8K 312 struct async_event_msg_req { 313 __u64 buf_addr; 314 __u32 buf_size; 315 } __packed; 316 317 struct async_event_msg_resp { 318 enum aie2_msg_status status; 319 enum async_event_type type; 320 } __packed; 321 322 #define MAX_CHAIN_CMDBUF_SIZE SZ_4K 323 #define slot_has_space(slot, offset, payload_size) \ 324 (MAX_CHAIN_CMDBUF_SIZE >= (offset) + (payload_size) + \ 325 sizeof(typeof(slot))) 326 327 struct cmd_chain_slot_execbuf_cf { 328 __u32 cu_idx; 329 __u32 arg_cnt; 330 __u32 args[] __counted_by(arg_cnt); 331 }; 332 333 struct cmd_chain_slot_dpu { 334 __u64 inst_buf_addr; 335 __u32 inst_size; 336 __u32 inst_prop_cnt; 337 __u32 cu_idx; 338 __u32 arg_cnt; 339 #define MAX_DPU_ARGS_SIZE (34 * sizeof(__u32)) 340 __u32 args[] __counted_by(arg_cnt); 341 }; 342 343 struct cmd_chain_req { 344 __u64 buf_addr; 345 __u32 buf_size; 346 __u32 count; 347 } __packed; 348 349 struct cmd_chain_resp { 350 enum aie2_msg_status status; 351 __u32 fail_cmd_idx; 352 enum aie2_msg_status fail_cmd_status; 353 } __packed; 354 355 #define AIE2_MSG_SYNC_BO_SRC_TYPE GENMASK(3, 0) 356 #define AIE2_MSG_SYNC_BO_DST_TYPE GENMASK(7, 4) 357 struct sync_bo_req { 358 __u64 src_addr; 359 __u64 dst_addr; 360 __u32 size; 361 #define SYNC_BO_DEV_MEM 0 362 #define SYNC_BO_HOST_MEM 2 363 __u32 type; 364 } __packed; 365 366 struct sync_bo_resp { 367 enum aie2_msg_status status; 368 } __packed; 369 370 #define DEBUG_BO_UNREGISTER 0 371 #define DEBUG_BO_REGISTER 1 372 struct config_debug_bo_req { 373 __u64 offset; 374 __u64 size; 375 /* 376 * config operations. 377 * DEBUG_BO_REGISTER: Register debug buffer 378 * DEBUG_BO_UNREGISTER: Unregister debug buffer 379 */ 380 __u32 config; 381 } __packed; 382 383 struct config_debug_bo_resp { 384 enum aie2_msg_status status; 385 } __packed; 386 #endif /* _AIE2_MSG_PRIV_H_ */ 387