1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #include <drm/amdxdna_accel.h> 7 #include <drm/drm_cache.h> 8 #include <drm/drm_device.h> 9 #include <drm/drm_gem.h> 10 #include <drm/drm_gem_shmem_helper.h> 11 #include <drm/drm_print.h> 12 #include <drm/gpu_scheduler.h> 13 #include <linux/bitfield.h> 14 #include <linux/errno.h> 15 #include <linux/pci.h> 16 #include <linux/types.h> 17 #include <linux/xarray.h> 18 19 #include "aie2_msg_priv.h" 20 #include "aie2_pci.h" 21 #include "amdxdna_ctx.h" 22 #include "amdxdna_gem.h" 23 #include "amdxdna_mailbox.h" 24 #include "amdxdna_mailbox_helper.h" 25 #include "amdxdna_pci_drv.h" 26 27 #define DECLARE_AIE2_MSG(name, op) \ 28 DECLARE_XDNA_MSG_COMMON(name, op, MAX_AIE2_STATUS_CODE) 29 30 #define EXEC_MSG_OPS(xdna) ((xdna)->dev_handle->exec_msg_ops) 31 32 static int aie2_send_mgmt_msg_wait(struct amdxdna_dev_hdl *ndev, 33 struct xdna_mailbox_msg *msg) 34 { 35 struct amdxdna_dev *xdna = ndev->xdna; 36 struct xdna_notify *hdl = msg->handle; 37 int ret; 38 39 if (!ndev->mgmt_chann) 40 return -ENODEV; 41 42 ret = xdna_send_msg_wait(xdna, ndev->mgmt_chann, msg); 43 if (ret == -ETIME) { 44 xdna_mailbox_stop_channel(ndev->mgmt_chann); 45 xdna_mailbox_destroy_channel(ndev->mgmt_chann); 46 ndev->mgmt_chann = NULL; 47 } 48 49 if (!ret && *hdl->status != AIE2_STATUS_SUCCESS) { 50 XDNA_ERR(xdna, "command opcode 0x%x failed, status 0x%x", 51 msg->opcode, *hdl->data); 52 ret = -EINVAL; 53 } 54 55 return ret; 56 } 57 58 void *aie2_alloc_msg_buffer(struct amdxdna_dev_hdl *ndev, u32 *size, 59 dma_addr_t *dma_addr) 60 { 61 struct amdxdna_dev *xdna = ndev->xdna; 62 int order; 63 64 *size = max(*size, SZ_8K); 65 order = get_order(*size); 66 if (order > MAX_PAGE_ORDER) 67 return NULL; 68 *size = PAGE_SIZE << order; 69 70 return dma_alloc_noncoherent(xdna->ddev.dev, *size, dma_addr, 71 DMA_FROM_DEVICE, GFP_KERNEL); 72 } 73 74 int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev) 75 { 76 DECLARE_AIE2_MSG(suspend, MSG_OP_SUSPEND); 77 int ret; 78 79 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 80 if (ret) { 81 XDNA_ERR(ndev->xdna, "Failed to suspend fw, ret %d", ret); 82 return ret; 83 } 84 85 return aie2_psp_waitmode_poll(ndev->psp_hdl); 86 } 87 88 int aie2_resume_fw(struct amdxdna_dev_hdl *ndev) 89 { 90 DECLARE_AIE2_MSG(suspend, MSG_OP_RESUME); 91 92 return aie2_send_mgmt_msg_wait(ndev, &msg); 93 } 94 95 int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value) 96 { 97 DECLARE_AIE2_MSG(set_runtime_cfg, MSG_OP_SET_RUNTIME_CONFIG); 98 int ret; 99 100 req.type = type; 101 req.value = value; 102 103 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 104 if (ret) { 105 XDNA_ERR(ndev->xdna, "Failed to set runtime config, ret %d", ret); 106 return ret; 107 } 108 109 return 0; 110 } 111 112 int aie2_get_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 *value) 113 { 114 DECLARE_AIE2_MSG(get_runtime_cfg, MSG_OP_GET_RUNTIME_CONFIG); 115 int ret; 116 117 req.type = type; 118 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 119 if (ret) { 120 XDNA_ERR(ndev->xdna, "Failed to get runtime config, ret %d", ret); 121 return ret; 122 } 123 124 *value = resp.value; 125 return 0; 126 } 127 128 int aie2_assign_mgmt_pasid(struct amdxdna_dev_hdl *ndev, u16 pasid) 129 { 130 DECLARE_AIE2_MSG(assign_mgmt_pasid, MSG_OP_ASSIGN_MGMT_PASID); 131 132 req.pasid = pasid; 133 134 return aie2_send_mgmt_msg_wait(ndev, &msg); 135 } 136 137 int aie2_query_aie_version(struct amdxdna_dev_hdl *ndev, struct aie_version *version) 138 { 139 DECLARE_AIE2_MSG(aie_version_info, MSG_OP_QUERY_AIE_VERSION); 140 struct amdxdna_dev *xdna = ndev->xdna; 141 int ret; 142 143 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 144 if (ret) 145 return ret; 146 147 XDNA_DBG(xdna, "Query AIE version - major: %u minor: %u completed", 148 resp.major, resp.minor); 149 150 version->major = resp.major; 151 version->minor = resp.minor; 152 153 return 0; 154 } 155 156 int aie2_query_aie_metadata(struct amdxdna_dev_hdl *ndev, struct aie_metadata *metadata) 157 { 158 DECLARE_AIE2_MSG(aie_tile_info, MSG_OP_QUERY_AIE_TILE_INFO); 159 int ret; 160 161 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 162 if (ret) 163 return ret; 164 165 metadata->size = resp.info.size; 166 metadata->cols = resp.info.cols; 167 metadata->rows = resp.info.rows; 168 169 metadata->version.major = resp.info.major; 170 metadata->version.minor = resp.info.minor; 171 172 metadata->core.row_count = resp.info.core_rows; 173 metadata->core.row_start = resp.info.core_row_start; 174 metadata->core.dma_channel_count = resp.info.core_dma_channels; 175 metadata->core.lock_count = resp.info.core_locks; 176 metadata->core.event_reg_count = resp.info.core_events; 177 178 metadata->mem.row_count = resp.info.mem_rows; 179 metadata->mem.row_start = resp.info.mem_row_start; 180 metadata->mem.dma_channel_count = resp.info.mem_dma_channels; 181 metadata->mem.lock_count = resp.info.mem_locks; 182 metadata->mem.event_reg_count = resp.info.mem_events; 183 184 metadata->shim.row_count = resp.info.shim_rows; 185 metadata->shim.row_start = resp.info.shim_row_start; 186 metadata->shim.dma_channel_count = resp.info.shim_dma_channels; 187 metadata->shim.lock_count = resp.info.shim_locks; 188 metadata->shim.event_reg_count = resp.info.shim_events; 189 190 return 0; 191 } 192 193 int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev, 194 struct amdxdna_fw_ver *fw_ver) 195 { 196 DECLARE_AIE2_MSG(firmware_version, MSG_OP_GET_FIRMWARE_VERSION); 197 int ret; 198 199 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 200 if (ret) 201 return ret; 202 203 fw_ver->major = resp.major; 204 fw_ver->minor = resp.minor; 205 fw_ver->sub = resp.sub; 206 fw_ver->build = resp.build; 207 208 return 0; 209 } 210 211 static int aie2_destroy_context_req(struct amdxdna_dev_hdl *ndev, u32 id) 212 { 213 DECLARE_AIE2_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT); 214 struct amdxdna_dev *xdna = ndev->xdna; 215 int ret; 216 217 req.context_id = id; 218 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 219 if (ret) 220 XDNA_WARN(xdna, "Destroy context failed, ret %d", ret); 221 222 return ret; 223 } 224 225 static u32 aie2_get_context_priority(struct amdxdna_dev_hdl *ndev, 226 struct amdxdna_hwctx *hwctx) 227 { 228 if (!AIE2_FEATURE_ON(ndev, AIE2_PREEMPT)) 229 return PRIORITY_HIGH; 230 231 switch (hwctx->qos.priority) { 232 case AMDXDNA_QOS_REALTIME_PRIORITY: 233 return PRIORITY_REALTIME; 234 case AMDXDNA_QOS_HIGH_PRIORITY: 235 return PRIORITY_HIGH; 236 case AMDXDNA_QOS_NORMAL_PRIORITY: 237 return PRIORITY_NORMAL; 238 case AMDXDNA_QOS_LOW_PRIORITY: 239 return PRIORITY_LOW; 240 default: 241 return PRIORITY_HIGH; 242 } 243 } 244 245 int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) 246 { 247 DECLARE_AIE2_MSG(create_ctx, MSG_OP_CREATE_CONTEXT); 248 struct amdxdna_dev *xdna = ndev->xdna; 249 struct xdna_mailbox_chann_res x2i; 250 struct xdna_mailbox_chann_res i2x; 251 struct cq_pair *cq_pair; 252 u32 intr_reg; 253 int ret; 254 255 req.aie_type = 1; 256 req.start_col = hwctx->start_col; 257 req.num_col = hwctx->num_col; 258 req.num_unused_col = hwctx->num_unused_col; 259 req.num_cq_pairs_requested = 1; 260 req.pasid = hwctx->client->pasid; 261 req.context_priority = aie2_get_context_priority(ndev, hwctx); 262 263 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 264 if (ret) 265 return ret; 266 267 hwctx->fw_ctx_id = resp.context_id; 268 if (WARN_ON_ONCE(hwctx->fw_ctx_id == -1)) 269 return -EINVAL; 270 271 if (ndev->force_preempt_enabled) { 272 ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_FORCE_PREEMPT, &hwctx->fw_ctx_id); 273 if (ret) { 274 XDNA_ERR(xdna, "failed to enable force preempt %d", ret); 275 goto del_ctx_req; 276 } 277 } 278 279 cq_pair = &resp.cq_pair[0]; 280 x2i.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.head_addr); 281 x2i.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->x2i_q.tail_addr); 282 x2i.rb_start_addr = AIE2_SRAM_OFF(ndev, cq_pair->x2i_q.buf_addr); 283 x2i.rb_size = cq_pair->x2i_q.buf_size; 284 285 i2x.mb_head_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.head_addr); 286 i2x.mb_tail_ptr_reg = AIE2_MBOX_OFF(ndev, cq_pair->i2x_q.tail_addr); 287 i2x.rb_start_addr = AIE2_SRAM_OFF(ndev, cq_pair->i2x_q.buf_addr); 288 i2x.rb_size = cq_pair->i2x_q.buf_size; 289 290 ret = pci_irq_vector(to_pci_dev(xdna->ddev.dev), resp.msix_id); 291 if (ret == -EINVAL) { 292 XDNA_ERR(xdna, "Alloc IRQ failed %d", ret); 293 goto del_ctx_req; 294 } 295 296 intr_reg = i2x.mb_head_ptr_reg + 4; 297 hwctx->priv->mbox_chann = xdna_mailbox_create_channel(ndev->mbox, &x2i, &i2x, 298 intr_reg, ret); 299 if (!hwctx->priv->mbox_chann) { 300 XDNA_ERR(xdna, "Not able to create channel"); 301 ret = -EINVAL; 302 goto del_ctx_req; 303 } 304 ndev->hwctx_num++; 305 306 XDNA_DBG(xdna, "Mailbox channel irq: %d, msix_id: %d", ret, resp.msix_id); 307 XDNA_DBG(xdna, "Created fw ctx %d pasid %d", hwctx->fw_ctx_id, hwctx->client->pasid); 308 309 return 0; 310 311 del_ctx_req: 312 aie2_destroy_context_req(ndev, hwctx->fw_ctx_id); 313 return ret; 314 } 315 316 int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) 317 { 318 struct amdxdna_dev *xdna = ndev->xdna; 319 int ret; 320 321 xdna_mailbox_stop_channel(hwctx->priv->mbox_chann); 322 ret = aie2_destroy_context_req(ndev, hwctx->fw_ctx_id); 323 xdna_mailbox_destroy_channel(hwctx->priv->mbox_chann); 324 XDNA_DBG(xdna, "Destroyed fw ctx %d", hwctx->fw_ctx_id); 325 hwctx->priv->mbox_chann = NULL; 326 hwctx->fw_ctx_id = -1; 327 ndev->hwctx_num--; 328 329 return ret; 330 } 331 332 int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size) 333 { 334 DECLARE_AIE2_MSG(map_host_buffer, MSG_OP_MAP_HOST_BUFFER); 335 struct amdxdna_dev *xdna = ndev->xdna; 336 int ret; 337 338 req.context_id = context_id; 339 req.buf_addr = addr; 340 req.buf_size = size; 341 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 342 if (ret) 343 return ret; 344 345 XDNA_DBG(xdna, "fw ctx %d map host buf addr 0x%llx size 0x%llx", 346 context_id, addr, size); 347 348 return 0; 349 } 350 351 static int amdxdna_hwctx_col_map(struct amdxdna_hwctx *hwctx, void *arg) 352 { 353 u32 *bitmap = arg; 354 355 *bitmap |= GENMASK(hwctx->start_col + hwctx->num_col - 1, hwctx->start_col); 356 357 return 0; 358 } 359 360 int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, 361 u32 size, u32 *cols_filled) 362 { 363 DECLARE_AIE2_MSG(aie_column_info, MSG_OP_QUERY_COL_STATUS); 364 struct amdxdna_dev *xdna = ndev->xdna; 365 u32 buf_sz = size, aie_bitmap = 0; 366 struct amdxdna_client *client; 367 dma_addr_t dma_addr; 368 u8 *buff_addr; 369 int ret; 370 371 buff_addr = aie2_alloc_msg_buffer(ndev, &buf_sz, &dma_addr); 372 if (!buff_addr) 373 return -ENOMEM; 374 375 /* Go through each hardware context and mark the AIE columns that are active */ 376 list_for_each_entry(client, &xdna->client_list, node) 377 amdxdna_hwctx_walk(client, &aie_bitmap, amdxdna_hwctx_col_map); 378 379 *cols_filled = 0; 380 req.dump_buff_addr = dma_addr; 381 req.dump_buff_size = buf_sz; 382 req.num_cols = hweight32(aie_bitmap); 383 req.aie_bitmap = aie_bitmap; 384 385 drm_clflush_virt_range(buff_addr, size); /* device can access */ 386 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 387 if (ret) { 388 XDNA_ERR(xdna, "Error during NPU query, status %d", ret); 389 goto fail; 390 } 391 392 XDNA_DBG(xdna, "Query NPU status completed"); 393 394 if (size < resp.size) { 395 ret = -EINVAL; 396 XDNA_ERR(xdna, "Bad buffer size. Available: %u. Needs: %u", size, resp.size); 397 goto fail; 398 } 399 400 if (copy_to_user(buf, buff_addr, resp.size)) { 401 ret = -EFAULT; 402 XDNA_ERR(xdna, "Failed to copy NPU status to user space"); 403 goto fail; 404 } 405 406 *cols_filled = aie_bitmap; 407 408 fail: 409 aie2_free_msg_buffer(ndev, buf_sz, buff_addr, dma_addr); 410 return ret; 411 } 412 413 int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev, 414 char __user *buf, u32 size, 415 struct amdxdna_drm_query_telemetry_header *header) 416 { 417 DECLARE_AIE2_MSG(get_telemetry, MSG_OP_GET_TELEMETRY); 418 struct amdxdna_dev *xdna = ndev->xdna; 419 dma_addr_t dma_addr; 420 u32 buf_sz = size; 421 u8 *addr; 422 int ret; 423 424 if (header->type >= MAX_TELEMETRY_TYPE) 425 return -EINVAL; 426 427 addr = aie2_alloc_msg_buffer(ndev, &buf_sz, &dma_addr); 428 if (!addr) 429 return -ENOMEM; 430 431 req.buf_addr = dma_addr; 432 req.buf_size = buf_sz; 433 req.type = header->type; 434 435 drm_clflush_virt_range(addr, size); /* device can access */ 436 ret = aie2_send_mgmt_msg_wait(ndev, &msg); 437 if (ret) { 438 XDNA_ERR(xdna, "Query telemetry failed, status %d", ret); 439 goto free_buf; 440 } 441 442 if (size < resp.size) { 443 ret = -EINVAL; 444 XDNA_ERR(xdna, "Bad buffer size. Available: %u. Needs: %u", size, resp.size); 445 goto free_buf; 446 } 447 448 if (copy_to_user(buf, addr, resp.size)) { 449 ret = -EFAULT; 450 XDNA_ERR(xdna, "Failed to copy telemetry to user space"); 451 goto free_buf; 452 } 453 454 header->major = resp.major; 455 header->minor = resp.minor; 456 457 free_buf: 458 aie2_free_msg_buffer(ndev, buf_sz, addr, dma_addr); 459 return ret; 460 } 461 462 int aie2_register_asyn_event_msg(struct amdxdna_dev_hdl *ndev, dma_addr_t addr, u32 size, 463 void *handle, int (*cb)(void*, void __iomem *, size_t)) 464 { 465 struct async_event_msg_req req = { 0 }; 466 struct xdna_mailbox_msg msg = { 467 .send_data = (u8 *)&req, 468 .send_size = sizeof(req), 469 .handle = handle, 470 .opcode = MSG_OP_REGISTER_ASYNC_EVENT_MSG, 471 .notify_cb = cb, 472 }; 473 474 req.buf_addr = addr; 475 req.buf_size = size; 476 477 XDNA_DBG(ndev->xdna, "Register addr 0x%llx size 0x%x", addr, size); 478 return xdna_mailbox_send_msg(ndev->mgmt_chann, &msg, TX_TIMEOUT); 479 } 480 481 int aie2_config_cu(struct amdxdna_hwctx *hwctx, 482 int (*notify_cb)(void *, void __iomem *, size_t)) 483 { 484 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 485 struct amdxdna_dev *xdna = hwctx->client->xdna; 486 u32 shift = xdna->dev_info->dev_mem_buf_shift; 487 struct config_cu_req req = { 0 }; 488 struct xdna_mailbox_msg msg; 489 struct drm_gem_object *gobj; 490 struct amdxdna_gem_obj *abo; 491 int i; 492 493 if (!chann) 494 return -ENODEV; 495 496 if (!hwctx->cus) 497 return 0; 498 499 if (hwctx->cus->num_cus > MAX_NUM_CUS) { 500 XDNA_DBG(xdna, "Exceed maximum CU %d", MAX_NUM_CUS); 501 return -EINVAL; 502 } 503 504 for (i = 0; i < hwctx->cus->num_cus; i++) { 505 struct amdxdna_cu_config *cu = &hwctx->cus->cu_configs[i]; 506 507 if (XDNA_MBZ_DBG(xdna, cu->pad, sizeof(cu->pad))) 508 return -EINVAL; 509 510 gobj = drm_gem_object_lookup(hwctx->client->filp, cu->cu_bo); 511 if (!gobj) { 512 XDNA_ERR(xdna, "Lookup GEM object failed"); 513 return -EINVAL; 514 } 515 abo = to_xdna_obj(gobj); 516 517 if (abo->type != AMDXDNA_BO_DEV) { 518 drm_gem_object_put(gobj); 519 XDNA_ERR(xdna, "Invalid BO type"); 520 return -EINVAL; 521 } 522 523 req.cfgs[i] = FIELD_PREP(AIE2_MSG_CFG_CU_PDI_ADDR, 524 abo->mem.dev_addr >> shift); 525 req.cfgs[i] |= FIELD_PREP(AIE2_MSG_CFG_CU_FUNC, cu->cu_func); 526 XDNA_DBG(xdna, "CU %d full addr 0x%llx, cfg 0x%x", i, 527 abo->mem.dev_addr, req.cfgs[i]); 528 drm_gem_object_put(gobj); 529 } 530 req.num_cus = hwctx->cus->num_cus; 531 532 msg.send_data = (u8 *)&req; 533 msg.send_size = sizeof(req); 534 msg.handle = hwctx; 535 msg.opcode = MSG_OP_CONFIG_CU; 536 msg.notify_cb = notify_cb; 537 return xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 538 } 539 540 static int aie2_init_exec_cu_req(struct amdxdna_gem_obj *cmd_bo, void *req, 541 size_t *size, u32 *msg_op) 542 { 543 struct execute_buffer_req *cu_req = req; 544 u32 cmd_len; 545 void *cmd; 546 547 cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 548 if (cmd_len > sizeof(cu_req->payload)) 549 return -EINVAL; 550 551 cu_req->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 552 if (cu_req->cu_idx == INVALID_CU_IDX) 553 return -EINVAL; 554 555 memcpy(cu_req->payload, cmd, cmd_len); 556 557 *size = sizeof(*cu_req); 558 *msg_op = MSG_OP_EXECUTE_BUFFER_CF; 559 return 0; 560 } 561 562 static int aie2_init_exec_dpu_req(struct amdxdna_gem_obj *cmd_bo, void *req, 563 size_t *size, u32 *msg_op) 564 { 565 struct exec_dpu_req *dpu_req = req; 566 struct amdxdna_cmd_start_npu *sn; 567 u32 cmd_len; 568 569 sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 570 if (cmd_len - sizeof(*sn) > sizeof(dpu_req->payload)) 571 return -EINVAL; 572 573 dpu_req->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 574 if (dpu_req->cu_idx == INVALID_CU_IDX) 575 return -EINVAL; 576 577 dpu_req->inst_buf_addr = sn->buffer; 578 dpu_req->inst_size = sn->buffer_size; 579 dpu_req->inst_prop_cnt = sn->prop_count; 580 memcpy(dpu_req->payload, sn->prop_args, cmd_len - sizeof(*sn)); 581 582 *size = sizeof(*dpu_req); 583 *msg_op = MSG_OP_EXEC_DPU; 584 return 0; 585 } 586 587 static void aie2_init_exec_chain_req(void *req, u64 slot_addr, size_t size, u32 cmd_cnt) 588 { 589 struct cmd_chain_req *chain_req = req; 590 591 chain_req->buf_addr = slot_addr; 592 chain_req->buf_size = size; 593 chain_req->count = cmd_cnt; 594 } 595 596 static void aie2_init_npu_chain_req(void *req, u64 slot_addr, size_t size, u32 cmd_cnt) 597 { 598 struct cmd_chain_npu_req *npu_chain_req = req; 599 600 npu_chain_req->flags = 0; 601 npu_chain_req->reserved = 0; 602 npu_chain_req->buf_addr = slot_addr; 603 npu_chain_req->buf_size = size; 604 npu_chain_req->count = cmd_cnt; 605 } 606 607 static int 608 aie2_cmdlist_fill_cf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 609 { 610 struct cmd_chain_slot_execbuf_cf *cf_slot = slot; 611 u32 cmd_len; 612 void *cmd; 613 614 cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 615 if (*size < sizeof(*cf_slot) + cmd_len) 616 return -EINVAL; 617 618 cf_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 619 if (cf_slot->cu_idx == INVALID_CU_IDX) 620 return -EINVAL; 621 622 cf_slot->arg_cnt = cmd_len / sizeof(u32); 623 memcpy(cf_slot->args, cmd, cmd_len); 624 /* Accurate slot size to hint firmware to do necessary copy */ 625 *size = sizeof(*cf_slot) + cmd_len; 626 return 0; 627 } 628 629 static int 630 aie2_cmdlist_fill_dpu(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 631 { 632 struct cmd_chain_slot_dpu *dpu_slot = slot; 633 struct amdxdna_cmd_start_npu *sn; 634 u32 cmd_len; 635 u32 arg_sz; 636 637 sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 638 arg_sz = cmd_len - sizeof(*sn); 639 if (cmd_len < sizeof(*sn) || arg_sz > MAX_DPU_ARGS_SIZE) 640 return -EINVAL; 641 642 if (*size < sizeof(*dpu_slot) + arg_sz) 643 return -EINVAL; 644 645 dpu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 646 if (dpu_slot->cu_idx == INVALID_CU_IDX) 647 return -EINVAL; 648 649 dpu_slot->inst_buf_addr = sn->buffer; 650 dpu_slot->inst_size = sn->buffer_size; 651 dpu_slot->inst_prop_cnt = sn->prop_count; 652 dpu_slot->arg_cnt = arg_sz / sizeof(u32); 653 memcpy(dpu_slot->args, sn->prop_args, arg_sz); 654 655 /* Accurate slot size to hint firmware to do necessary copy */ 656 *size = sizeof(*dpu_slot) + arg_sz; 657 return 0; 658 } 659 660 static int aie2_cmdlist_unsupp(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 661 { 662 return -EOPNOTSUPP; 663 } 664 665 static u32 aie2_get_chain_msg_op(u32 cmd_op) 666 { 667 switch (cmd_op) { 668 case ERT_START_CU: 669 return MSG_OP_CHAIN_EXEC_BUFFER_CF; 670 case ERT_START_NPU: 671 return MSG_OP_CHAIN_EXEC_DPU; 672 default: 673 break; 674 } 675 676 return MSG_OP_MAX_OPCODE; 677 } 678 679 static struct aie2_exec_msg_ops legacy_exec_message_ops = { 680 .init_cu_req = aie2_init_exec_cu_req, 681 .init_dpu_req = aie2_init_exec_dpu_req, 682 .init_chain_req = aie2_init_exec_chain_req, 683 .fill_cf_slot = aie2_cmdlist_fill_cf, 684 .fill_dpu_slot = aie2_cmdlist_fill_dpu, 685 .fill_preempt_slot = aie2_cmdlist_unsupp, 686 .fill_elf_slot = aie2_cmdlist_unsupp, 687 .get_chain_msg_op = aie2_get_chain_msg_op, 688 }; 689 690 static int 691 aie2_cmdlist_fill_npu_cf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 692 { 693 struct cmd_chain_slot_npu *npu_slot = slot; 694 u32 cmd_len; 695 void *cmd; 696 697 memset(npu_slot, 0, sizeof(*npu_slot)); 698 cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 699 if (*size < sizeof(*npu_slot) + cmd_len) 700 return -EINVAL; 701 702 npu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 703 if (npu_slot->cu_idx == INVALID_CU_IDX) 704 return -EINVAL; 705 706 npu_slot->type = EXEC_NPU_TYPE_NON_ELF; 707 npu_slot->arg_cnt = cmd_len / sizeof(u32); 708 memcpy(npu_slot->args, cmd, cmd_len); 709 710 *size = sizeof(*npu_slot) + cmd_len; 711 return 0; 712 } 713 714 static int 715 aie2_cmdlist_fill_npu_dpu(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 716 { 717 struct cmd_chain_slot_npu *npu_slot = slot; 718 struct amdxdna_cmd_start_npu *sn; 719 u32 cmd_len; 720 u32 arg_sz; 721 722 memset(npu_slot, 0, sizeof(*npu_slot)); 723 sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 724 arg_sz = cmd_len - sizeof(*sn); 725 if (cmd_len < sizeof(*sn) || arg_sz > MAX_NPU_ARGS_SIZE) 726 return -EINVAL; 727 728 if (*size < sizeof(*npu_slot) + arg_sz) 729 return -EINVAL; 730 731 npu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 732 if (npu_slot->cu_idx == INVALID_CU_IDX) 733 return -EINVAL; 734 735 npu_slot->type = EXEC_NPU_TYPE_PARTIAL_ELF; 736 npu_slot->inst_buf_addr = sn->buffer; 737 npu_slot->inst_size = sn->buffer_size; 738 npu_slot->inst_prop_cnt = sn->prop_count; 739 npu_slot->arg_cnt = arg_sz / sizeof(u32); 740 memcpy(npu_slot->args, sn->prop_args, arg_sz); 741 742 *size = sizeof(*npu_slot) + arg_sz; 743 return 0; 744 } 745 746 static int 747 aie2_cmdlist_fill_npu_preempt(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 748 { 749 struct cmd_chain_slot_npu *npu_slot = slot; 750 struct amdxdna_cmd_preempt_data *pd; 751 u32 cmd_len; 752 u32 arg_sz; 753 754 memset(npu_slot, 0, sizeof(*npu_slot)); 755 pd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 756 arg_sz = cmd_len - sizeof(*pd); 757 if (cmd_len < sizeof(*pd) || arg_sz > MAX_NPU_ARGS_SIZE) 758 return -EINVAL; 759 760 if (*size < sizeof(*npu_slot) + arg_sz) 761 return -EINVAL; 762 763 npu_slot->cu_idx = amdxdna_cmd_get_cu_idx(cmd_bo); 764 if (npu_slot->cu_idx == INVALID_CU_IDX) 765 return -EINVAL; 766 767 npu_slot->type = EXEC_NPU_TYPE_PREEMPT; 768 npu_slot->inst_buf_addr = pd->inst_buf; 769 npu_slot->save_buf_addr = pd->save_buf; 770 npu_slot->restore_buf_addr = pd->restore_buf; 771 npu_slot->inst_size = pd->inst_size; 772 npu_slot->save_size = pd->save_size; 773 npu_slot->restore_size = pd->restore_size; 774 npu_slot->inst_prop_cnt = pd->inst_prop_cnt; 775 npu_slot->arg_cnt = arg_sz / sizeof(u32); 776 memcpy(npu_slot->args, pd->prop_args, arg_sz); 777 778 *size = sizeof(*npu_slot) + arg_sz; 779 return 0; 780 } 781 782 static int 783 aie2_cmdlist_fill_npu_elf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size) 784 { 785 struct cmd_chain_slot_npu *npu_slot = slot; 786 struct amdxdna_cmd_preempt_data *pd; 787 u32 cmd_len; 788 u32 arg_sz; 789 790 memset(npu_slot, 0, sizeof(*npu_slot)); 791 pd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); 792 arg_sz = cmd_len - sizeof(*pd); 793 if (cmd_len < sizeof(*pd) || arg_sz > MAX_NPU_ARGS_SIZE) 794 return -EINVAL; 795 796 if (*size < sizeof(*npu_slot) + arg_sz) 797 return -EINVAL; 798 799 npu_slot->type = EXEC_NPU_TYPE_ELF; 800 npu_slot->inst_buf_addr = pd->inst_buf; 801 npu_slot->save_buf_addr = pd->save_buf; 802 npu_slot->restore_buf_addr = pd->restore_buf; 803 npu_slot->inst_size = pd->inst_size; 804 npu_slot->save_size = pd->save_size; 805 npu_slot->restore_size = pd->restore_size; 806 npu_slot->inst_prop_cnt = pd->inst_prop_cnt; 807 npu_slot->arg_cnt = 1; 808 npu_slot->args[0] = AIE2_EXEC_BUFFER_KERNEL_OP_TXN; 809 810 *size = struct_size(npu_slot, args, npu_slot->arg_cnt); 811 return 0; 812 } 813 814 static u32 aie2_get_npu_chain_msg_op(u32 cmd_op) 815 { 816 return MSG_OP_CHAIN_EXEC_NPU; 817 } 818 819 static struct aie2_exec_msg_ops npu_exec_message_ops = { 820 .init_cu_req = aie2_init_exec_cu_req, 821 .init_dpu_req = aie2_init_exec_dpu_req, 822 .init_chain_req = aie2_init_npu_chain_req, 823 .fill_cf_slot = aie2_cmdlist_fill_npu_cf, 824 .fill_dpu_slot = aie2_cmdlist_fill_npu_dpu, 825 .fill_preempt_slot = aie2_cmdlist_fill_npu_preempt, 826 .fill_elf_slot = aie2_cmdlist_fill_npu_elf, 827 .get_chain_msg_op = aie2_get_npu_chain_msg_op, 828 }; 829 830 static int aie2_init_exec_req(void *req, struct amdxdna_gem_obj *cmd_abo, 831 size_t *size, u32 *msg_op) 832 { 833 struct amdxdna_dev *xdna = cmd_abo->client->xdna; 834 int ret; 835 u32 op; 836 837 838 op = amdxdna_cmd_get_op(cmd_abo); 839 switch (op) { 840 case ERT_START_CU: 841 ret = EXEC_MSG_OPS(xdna)->init_cu_req(cmd_abo, req, size, msg_op); 842 if (ret) { 843 XDNA_DBG(xdna, "Init CU req failed ret %d", ret); 844 return ret; 845 } 846 break; 847 case ERT_START_NPU: 848 ret = EXEC_MSG_OPS(xdna)->init_dpu_req(cmd_abo, req, size, msg_op); 849 if (ret) { 850 XDNA_DBG(xdna, "Init DPU req failed ret %d", ret); 851 return ret; 852 } 853 854 break; 855 default: 856 XDNA_ERR(xdna, "Unsupported op %d", op); 857 ret = -EOPNOTSUPP; 858 break; 859 } 860 861 return ret; 862 } 863 864 static int 865 aie2_cmdlist_fill_slot(void *slot, struct amdxdna_gem_obj *cmd_abo, 866 size_t *size, u32 *cmd_op) 867 { 868 struct amdxdna_dev *xdna = cmd_abo->client->xdna; 869 int ret; 870 u32 op; 871 872 op = amdxdna_cmd_get_op(cmd_abo); 873 if (*cmd_op == ERT_INVALID_CMD) 874 *cmd_op = op; 875 else if (op != *cmd_op) 876 return -EINVAL; 877 878 switch (op) { 879 case ERT_START_CU: 880 ret = EXEC_MSG_OPS(xdna)->fill_cf_slot(cmd_abo, slot, size); 881 break; 882 case ERT_START_NPU: 883 ret = EXEC_MSG_OPS(xdna)->fill_dpu_slot(cmd_abo, slot, size); 884 break; 885 case ERT_START_NPU_PREEMPT: 886 if (!AIE2_FEATURE_ON(xdna->dev_handle, AIE2_PREEMPT)) 887 return -EOPNOTSUPP; 888 ret = EXEC_MSG_OPS(xdna)->fill_preempt_slot(cmd_abo, slot, size); 889 break; 890 case ERT_START_NPU_PREEMPT_ELF: 891 if (!AIE2_FEATURE_ON(xdna->dev_handle, AIE2_PREEMPT)) 892 return -EOPNOTSUPP; 893 ret = EXEC_MSG_OPS(xdna)->fill_elf_slot(cmd_abo, slot, size); 894 break; 895 default: 896 XDNA_INFO(xdna, "Unsupported op %d", op); 897 ret = -EOPNOTSUPP; 898 break; 899 } 900 901 return ret; 902 } 903 904 void aie2_msg_init(struct amdxdna_dev_hdl *ndev) 905 { 906 if (AIE2_FEATURE_ON(ndev, AIE2_NPU_COMMAND)) 907 ndev->exec_msg_ops = &npu_exec_message_ops; 908 else 909 ndev->exec_msg_ops = &legacy_exec_message_ops; 910 } 911 912 static inline struct amdxdna_gem_obj * 913 aie2_cmdlist_get_cmd_buf(struct amdxdna_sched_job *job) 914 { 915 int idx = get_job_idx(job->seq); 916 917 return job->hwctx->priv->cmd_buf[idx]; 918 } 919 920 int aie2_execbuf(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, 921 int (*notify_cb)(void *, void __iomem *, size_t)) 922 { 923 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 924 struct amdxdna_dev *xdna = hwctx->client->xdna; 925 struct amdxdna_gem_obj *cmd_abo = job->cmd_bo; 926 struct xdna_mailbox_msg msg; 927 union exec_req req; 928 int ret; 929 930 if (!chann) 931 return -ENODEV; 932 933 ret = aie2_init_exec_req(&req, cmd_abo, &msg.send_size, &msg.opcode); 934 if (ret) 935 return ret; 936 937 msg.handle = job; 938 msg.notify_cb = notify_cb; 939 msg.send_data = (u8 *)&req; 940 print_hex_dump_debug("cmd: ", DUMP_PREFIX_OFFSET, 16, 4, &req, 941 0x40, false); 942 943 ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 944 if (ret) { 945 XDNA_ERR(xdna, "Send message failed"); 946 return ret; 947 } 948 949 return 0; 950 } 951 952 int aie2_cmdlist_multi_execbuf(struct amdxdna_hwctx *hwctx, 953 struct amdxdna_sched_job *job, 954 int (*notify_cb)(void *, void __iomem *, size_t)) 955 { 956 struct amdxdna_gem_obj *cmdbuf_abo = aie2_cmdlist_get_cmd_buf(job); 957 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 958 struct amdxdna_client *client = hwctx->client; 959 struct amdxdna_gem_obj *cmd_abo = job->cmd_bo; 960 struct amdxdna_dev *xdna = client->xdna; 961 struct amdxdna_cmd_chain *payload; 962 struct xdna_mailbox_msg msg; 963 union exec_chain_req req; 964 u32 payload_len; 965 u32 offset = 0; 966 size_t size; 967 int ret; 968 u32 op; 969 u32 i; 970 971 op = amdxdna_cmd_get_op(cmd_abo); 972 payload = amdxdna_cmd_get_payload(cmd_abo, &payload_len); 973 if (op != ERT_CMD_CHAIN || !payload || 974 payload_len < struct_size(payload, data, payload->command_count)) 975 return -EINVAL; 976 977 op = ERT_INVALID_CMD; 978 for (i = 0; i < payload->command_count; i++) { 979 u32 boh = (u32)(payload->data[i]); 980 struct amdxdna_gem_obj *abo; 981 982 abo = amdxdna_gem_get_obj(client, boh, AMDXDNA_BO_CMD); 983 if (!abo) { 984 XDNA_ERR(xdna, "Failed to find cmd BO %d", boh); 985 return -ENOENT; 986 } 987 988 size = cmdbuf_abo->mem.size - offset; 989 ret = aie2_cmdlist_fill_slot(cmdbuf_abo->mem.kva + offset, 990 abo, &size, &op); 991 amdxdna_gem_put_obj(abo); 992 if (ret) 993 return ret; 994 995 offset += size; 996 } 997 msg.opcode = EXEC_MSG_OPS(xdna)->get_chain_msg_op(op); 998 if (msg.opcode == MSG_OP_MAX_OPCODE) 999 return -EOPNOTSUPP; 1000 1001 /* The offset is the accumulated total size of the cmd buffer */ 1002 EXEC_MSG_OPS(xdna)->init_chain_req(&req, cmdbuf_abo->mem.dev_addr, 1003 offset, payload->command_count); 1004 drm_clflush_virt_range(cmdbuf_abo->mem.kva, offset); 1005 1006 msg.handle = job; 1007 msg.notify_cb = notify_cb; 1008 msg.send_data = (u8 *)&req; 1009 msg.send_size = sizeof(req); 1010 ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 1011 if (ret) { 1012 XDNA_ERR(xdna, "Send message failed"); 1013 return ret; 1014 } 1015 1016 return 0; 1017 } 1018 1019 int aie2_cmdlist_single_execbuf(struct amdxdna_hwctx *hwctx, 1020 struct amdxdna_sched_job *job, 1021 int (*notify_cb)(void *, void __iomem *, size_t)) 1022 { 1023 struct amdxdna_gem_obj *cmdbuf_abo = aie2_cmdlist_get_cmd_buf(job); 1024 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 1025 struct amdxdna_dev *xdna = hwctx->client->xdna; 1026 struct amdxdna_gem_obj *cmd_abo = job->cmd_bo; 1027 struct xdna_mailbox_msg msg; 1028 union exec_chain_req req; 1029 u32 op = ERT_INVALID_CMD; 1030 size_t size; 1031 int ret; 1032 1033 size = cmdbuf_abo->mem.size; 1034 ret = aie2_cmdlist_fill_slot(cmdbuf_abo->mem.kva, cmd_abo, &size, &op); 1035 if (ret) 1036 return ret; 1037 1038 msg.opcode = EXEC_MSG_OPS(xdna)->get_chain_msg_op(op); 1039 if (msg.opcode == MSG_OP_MAX_OPCODE) 1040 return -EOPNOTSUPP; 1041 1042 EXEC_MSG_OPS(xdna)->init_chain_req(&req, cmdbuf_abo->mem.dev_addr, 1043 size, 1); 1044 drm_clflush_virt_range(cmdbuf_abo->mem.kva, size); 1045 1046 msg.handle = job; 1047 msg.notify_cb = notify_cb; 1048 msg.send_data = (u8 *)&req; 1049 msg.send_size = sizeof(req); 1050 ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 1051 if (ret) { 1052 XDNA_ERR(hwctx->client->xdna, "Send message failed"); 1053 return ret; 1054 } 1055 1056 return 0; 1057 } 1058 1059 int aie2_sync_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, 1060 int (*notify_cb)(void *, void __iomem *, size_t)) 1061 { 1062 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 1063 struct amdxdna_gem_obj *abo = to_xdna_obj(job->bos[0]); 1064 struct amdxdna_dev *xdna = hwctx->client->xdna; 1065 struct xdna_mailbox_msg msg; 1066 struct sync_bo_req req; 1067 int ret = 0; 1068 1069 req.src_addr = 0; 1070 req.dst_addr = amdxdna_dev_bo_offset(abo); 1071 req.size = abo->mem.size; 1072 1073 /* Device to Host */ 1074 req.type = FIELD_PREP(AIE2_MSG_SYNC_BO_SRC_TYPE, SYNC_BO_DEV_MEM) | 1075 FIELD_PREP(AIE2_MSG_SYNC_BO_DST_TYPE, SYNC_BO_HOST_MEM); 1076 1077 XDNA_DBG(xdna, "sync %d bytes src(0x%llx) to dst(0x%llx) completed", 1078 req.size, req.src_addr, req.dst_addr); 1079 1080 msg.handle = job; 1081 msg.notify_cb = notify_cb; 1082 msg.send_data = (u8 *)&req; 1083 msg.send_size = sizeof(req); 1084 msg.opcode = MSG_OP_SYNC_BO; 1085 1086 ret = xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 1087 if (ret) { 1088 XDNA_ERR(xdna, "Send message failed"); 1089 return ret; 1090 } 1091 1092 return 0; 1093 } 1094 1095 int aie2_config_debug_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, 1096 int (*notify_cb)(void *, void __iomem *, size_t)) 1097 { 1098 struct mailbox_channel *chann = hwctx->priv->mbox_chann; 1099 struct amdxdna_gem_obj *abo = to_xdna_obj(job->bos[0]); 1100 struct amdxdna_dev *xdna = hwctx->client->xdna; 1101 struct config_debug_bo_req req; 1102 struct xdna_mailbox_msg msg; 1103 1104 if (job->drv_cmd->opcode == ATTACH_DEBUG_BO) 1105 req.config = DEBUG_BO_REGISTER; 1106 else 1107 req.config = DEBUG_BO_UNREGISTER; 1108 1109 req.offset = amdxdna_dev_bo_offset(abo); 1110 req.size = abo->mem.size; 1111 1112 XDNA_DBG(xdna, "offset 0x%llx size 0x%llx config %d", 1113 req.offset, req.size, req.config); 1114 1115 msg.handle = job; 1116 msg.notify_cb = notify_cb; 1117 msg.send_data = (u8 *)&req; 1118 msg.send_size = sizeof(req); 1119 msg.opcode = MSG_OP_CONFIG_DEBUG_BO; 1120 1121 return xdna_mailbox_send_msg(chann, &msg, TX_TIMEOUT); 1122 } 1123