1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2026, Advanced Micro Devices, Inc. 4 */ 5 #ifndef _AIE_H_ 6 #define _AIE_H_ 7 8 #include <drm/amdxdna_accel.h> 9 #include "amdxdna_pci_drv.h" 10 #include "amdxdna_mailbox.h" 11 12 #define AIE_INTERVAL 20000 /* us */ 13 #define AIE_TIMEOUT 1000000 /* us */ 14 15 struct psp_device; 16 struct smu_device; 17 18 struct aie_device { 19 struct amdxdna_dev *xdna; 20 struct mailbox_channel *mgmt_chann; 21 struct xdna_mailbox_chann_res mgmt_x2i; 22 struct xdna_mailbox_chann_res mgmt_i2x; 23 u32 mgmt_chan_idx; 24 u32 mgmt_prot_major; 25 u32 mgmt_prot_minor; 26 unsigned long feature_mask; 27 28 struct psp_device *psp_hdl; 29 struct smu_device *smu_hdl; 30 31 struct amdxdna_drm_query_aie_metadata metadata; 32 }; 33 34 #define DECLARE_AIE_MSG(name, op) \ 35 DECLARE_XDNA_MSG_COMMON(name, op, -1) 36 #define AIE_FEATURE_ON(aie, feature) test_bit(feature, &(aie)->feature_mask) 37 38 #define PSP_REG_BAR(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].bar_idx) 39 #define PSP_REG_OFF(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].offset) 40 41 #define SMU_REG_BAR(ndev, idx) ((ndev)->priv->smu_regs_off[(idx)].bar_idx) 42 #define SMU_REG_OFF(ndev, idx) ((ndev)->priv->smu_regs_off[(idx)].offset) 43 44 #define DEFINE_BAR_OFFSET(reg_name, bar, reg_addr) \ 45 [reg_name] = {bar##_BAR_INDEX, (reg_addr) - bar##_BAR_BASE} 46 47 enum smu_reg_idx { 48 SMU_CMD_REG = 0, 49 SMU_ARG_REG, 50 SMU_INTR_REG, 51 SMU_RESP_REG, 52 SMU_OUT_REG, 53 SMU_MAX_REGS /* Keep this at the end */ 54 }; 55 56 enum psp_reg_idx { 57 PSP_CMD_REG = 0, 58 PSP_ARG0_REG, 59 PSP_ARG1_REG, 60 PSP_ARG2_REG, 61 PSP_NUM_IN_REGS, /* number of input registers */ 62 PSP_INTR_REG = PSP_NUM_IN_REGS, 63 PSP_STATUS_REG, 64 PSP_RESP_REG, 65 PSP_PWAITMODE_REG, 66 PSP_MAX_REGS /* Keep this at the end */ 67 }; 68 69 struct aie_bar_off_pair { 70 int bar_idx; 71 u32 offset; 72 }; 73 74 struct smu_config { 75 void __iomem *smu_regs[SMU_MAX_REGS]; 76 }; 77 78 struct psp_config { 79 const void *fw_buf; 80 u32 fw_size; 81 const void *certfw_buf; 82 u32 certfw_size; 83 void __iomem *psp_regs[PSP_MAX_REGS]; 84 u32 arg2_mask; 85 u32 notify_val; 86 }; 87 88 /* Device revision to VBNV string mapping table entry */ 89 struct amdxdna_rev_vbnv { 90 u32 revision; 91 const char *vbnv; 92 }; 93 94 /* aie.c */ 95 void aie_dump_mgmt_chann_debug(struct aie_device *aie); 96 void aie_destroy_chann(struct aie_device *aie, struct mailbox_channel **chann); 97 int aie_send_mgmt_msg_wait(struct aie_device *aie, struct xdna_mailbox_msg *msg); 98 int aie_check_protocol(struct aie_device *aie, u32 fw_major, u32 fw_minor); 99 void amdxdna_vbnv_init(struct amdxdna_dev *xdna); 100 int amdxdna_get_metadata(struct aie_device *aie, struct amdxdna_client *client, 101 struct amdxdna_drm_get_info *args); 102 void *amdxdna_alloc_msg_buffer(struct amdxdna_dev *xdna, u32 *size, 103 dma_addr_t *dma_addr); 104 void amdxdna_free_msg_buffer(struct amdxdna_dev *xdna, size_t size, 105 void *cpu_addr, dma_addr_t dma_addr); 106 107 /* aie_psp.c */ 108 struct psp_device *aiem_psp_create(struct drm_device *ddev, struct psp_config *conf); 109 int aie_psp_start(struct psp_device *psp); 110 void aie_psp_stop(struct psp_device *psp); 111 int aie_psp_waitmode_poll(struct psp_device *psp); 112 113 /* aie_smu.c */ 114 struct smu_device *aiem_smu_create(struct drm_device *ddev, struct smu_config *conf); 115 int aie_smu_init(struct smu_device *smu); 116 void aie_smu_fini(struct smu_device *smu); 117 int aie_smu_set_clocks(struct smu_device *smu, u32 *npuclk, u32 *hclk); 118 int aie_smu_set_dpm(struct smu_device *smu, u32 dpm_level); 119 120 #endif /* _AIE_H_ */ 121