1 /* 2 * This header file describes this specific Xtensa processor's TIE extensions 3 * that extend basic Xtensa core functionality. It is customized to this 4 * Xtensa processor configuration. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 * 10 * Copyright (C) 1999-2007 Tensilica Inc. 11 */ 12 13 #ifndef _XTENSA_CORE_TIE_H 14 #define _XTENSA_CORE_TIE_H 15 16 #define XCHAL_CP_NUM 0 /* number of coprocessors */ 17 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ 18 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ 19 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ 20 21 /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 22 #define XCHAL_NCP_SA_SIZE 0 23 #define XCHAL_NCP_SA_ALIGN 1 24 #define XCHAL_CP0_SA_SIZE 0 25 #define XCHAL_CP0_SA_ALIGN 1 26 #define XCHAL_CP1_SA_SIZE 0 27 #define XCHAL_CP1_SA_ALIGN 1 28 #define XCHAL_CP2_SA_SIZE 0 29 #define XCHAL_CP2_SA_ALIGN 1 30 #define XCHAL_CP3_SA_SIZE 0 31 #define XCHAL_CP3_SA_ALIGN 1 32 #define XCHAL_CP4_SA_SIZE 0 33 #define XCHAL_CP4_SA_ALIGN 1 34 #define XCHAL_CP5_SA_SIZE 0 35 #define XCHAL_CP5_SA_ALIGN 1 36 #define XCHAL_CP6_SA_SIZE 0 37 #define XCHAL_CP6_SA_ALIGN 1 38 #define XCHAL_CP7_SA_SIZE 0 39 #define XCHAL_CP7_SA_ALIGN 1 40 41 /* Save area for non-coprocessor optional and custom (TIE) state: */ 42 #define XCHAL_NCP_SA_SIZE 0 43 #define XCHAL_NCP_SA_ALIGN 1 44 45 /* Total save area for optional and custom state (NCP + CPn): */ 46 #define XCHAL_TOTAL_SA_SIZE 0 /* with 16-byte align padding */ 47 #define XCHAL_TOTAL_SA_ALIGN 1 /* actual minimum alignment */ 48 49 #define XCHAL_NCP_SA_NUM 0 50 #define XCHAL_NCP_SA_LIST(s) 51 #define XCHAL_CP0_SA_NUM 0 52 #define XCHAL_CP0_SA_LIST(s) 53 #define XCHAL_CP1_SA_NUM 0 54 #define XCHAL_CP1_SA_LIST(s) 55 #define XCHAL_CP2_SA_NUM 0 56 #define XCHAL_CP2_SA_LIST(s) 57 #define XCHAL_CP3_SA_NUM 0 58 #define XCHAL_CP3_SA_LIST(s) 59 #define XCHAL_CP4_SA_NUM 0 60 #define XCHAL_CP4_SA_LIST(s) 61 #define XCHAL_CP5_SA_NUM 0 62 #define XCHAL_CP5_SA_LIST(s) 63 #define XCHAL_CP6_SA_NUM 0 64 #define XCHAL_CP6_SA_LIST(s) 65 #define XCHAL_CP7_SA_NUM 0 66 #define XCHAL_CP7_SA_LIST(s) 67 68 /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 69 #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 70 71 #endif /*_XTENSA_CORE_TIE_H*/ 72 73