1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * arch/xtensa/platform/xtavnet/setup.c 5 * 6 * ... 7 * 8 * Authors: Chris Zankel <chris@zankel.net> 9 * Joe Taylor <joe@tensilica.com> 10 * 11 * Copyright 2001 - 2006 Tensilica Inc. 12 */ 13 #include <linux/stddef.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/errno.h> 18 #include <linux/reboot.h> 19 #include <linux/kdev_t.h> 20 #include <linux/types.h> 21 #include <linux/major.h> 22 #include <linux/console.h> 23 #include <linux/delay.h> 24 #include <linux/of.h> 25 #include <linux/clk-provider.h> 26 #include <linux/of_address.h> 27 #include <linux/slab.h> 28 29 #include <asm/timex.h> 30 #include <asm/processor.h> 31 #include <asm/platform.h> 32 #include <asm/bootparam.h> 33 #include <platform/lcd.h> 34 #include <platform/hardware.h> 35 36 void platform_halt(void) 37 { 38 lcd_disp_at_pos(" HALT ", 0); 39 local_irq_disable(); 40 while (1) 41 cpu_relax(); 42 } 43 44 void platform_power_off(void) 45 { 46 lcd_disp_at_pos("POWEROFF", 0); 47 local_irq_disable(); 48 while (1) 49 cpu_relax(); 50 } 51 52 void platform_restart(void) 53 { 54 /* Try software reset first. */ 55 WRITE_ONCE(*(u32 *)XTFPGA_SWRST_VADDR, 0xdead); 56 57 /* If software reset did not work, flush and reset the mmu, 58 * simulate a processor reset, and jump to the reset vector. 59 */ 60 cpu_reset(); 61 /* control never gets here */ 62 } 63 64 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT 65 66 void __init platform_calibrate_ccount(void) 67 { 68 ccount_freq = *(long *)XTFPGA_CLKFRQ_VADDR; 69 } 70 71 #endif 72 73 #ifdef CONFIG_USE_OF 74 75 static void __init xtfpga_clk_setup(struct device_node *np) 76 { 77 void __iomem *base = of_iomap(np, 0); 78 struct clk *clk; 79 u32 freq; 80 81 if (!base) { 82 pr_err("%pOFn: invalid address\n", np); 83 return; 84 } 85 86 freq = __raw_readl(base); 87 iounmap(base); 88 clk = clk_register_fixed_rate(NULL, np->name, NULL, 0, freq); 89 90 if (IS_ERR(clk)) { 91 pr_err("%pOFn: clk registration failed\n", np); 92 return; 93 } 94 95 if (of_clk_add_provider(np, of_clk_src_simple_get, clk)) { 96 pr_err("%pOFn: clk provider registration failed\n", np); 97 return; 98 } 99 } 100 CLK_OF_DECLARE(xtfpga_clk, "cdns,xtfpga-clock", xtfpga_clk_setup); 101 102 #define MAC_LEN 6 103 static void __init update_local_mac(struct device_node *node) 104 { 105 struct property *newmac; 106 const u8* macaddr; 107 int prop_len; 108 109 macaddr = of_get_property(node, "local-mac-address", &prop_len); 110 if (macaddr == NULL || prop_len != MAC_LEN) 111 return; 112 113 newmac = kzalloc(sizeof(*newmac) + MAC_LEN, GFP_KERNEL); 114 if (newmac == NULL) 115 return; 116 117 newmac->value = newmac + 1; 118 newmac->length = MAC_LEN; 119 newmac->name = kstrdup("local-mac-address", GFP_KERNEL); 120 if (newmac->name == NULL) { 121 kfree(newmac); 122 return; 123 } 124 125 memcpy(newmac->value, macaddr, MAC_LEN); 126 ((u8*)newmac->value)[5] = (*(u32*)DIP_SWITCHES_VADDR) & 0x3f; 127 of_update_property(node, newmac); 128 } 129 130 static int __init machine_setup(void) 131 { 132 struct device_node *eth = NULL; 133 134 if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc"))) 135 update_local_mac(eth); 136 of_node_put(eth); 137 return 0; 138 } 139 arch_initcall(machine_setup); 140 141 #else 142 143 #include <linux/serial_8250.h> 144 #include <linux/if.h> 145 #include <net/ethoc.h> 146 #include <linux/usb/c67x00.h> 147 148 /*---------------------------------------------------------------------------- 149 * Ethernet -- OpenCores Ethernet MAC (ethoc driver) 150 */ 151 152 static struct resource ethoc_res[] = { 153 [0] = { /* register space */ 154 .start = OETH_REGS_PADDR, 155 .end = OETH_REGS_PADDR + OETH_REGS_SIZE - 1, 156 .flags = IORESOURCE_MEM, 157 }, 158 [1] = { /* buffer space */ 159 .start = OETH_SRAMBUFF_PADDR, 160 .end = OETH_SRAMBUFF_PADDR + OETH_SRAMBUFF_SIZE - 1, 161 .flags = IORESOURCE_MEM, 162 }, 163 [2] = { /* IRQ number */ 164 .start = XTENSA_PIC_LINUX_IRQ(OETH_IRQ), 165 .end = XTENSA_PIC_LINUX_IRQ(OETH_IRQ), 166 .flags = IORESOURCE_IRQ, 167 }, 168 }; 169 170 static struct ethoc_platform_data ethoc_pdata = { 171 /* 172 * The MAC address for these boards is 00:50:c2:13:6f:xx. 173 * The last byte (here as zero) is read from the DIP switches on the 174 * board. 175 */ 176 .hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 }, 177 .phy_id = -1, 178 .big_endian = XCHAL_HAVE_BE, 179 }; 180 181 static struct platform_device ethoc_device = { 182 .name = "ethoc", 183 .id = -1, 184 .num_resources = ARRAY_SIZE(ethoc_res), 185 .resource = ethoc_res, 186 .dev = { 187 .platform_data = ðoc_pdata, 188 }, 189 }; 190 191 /*---------------------------------------------------------------------------- 192 * USB Host/Device -- Cypress CY7C67300 193 */ 194 195 static struct resource c67x00_res[] = { 196 [0] = { /* register space */ 197 .start = C67X00_PADDR, 198 .end = C67X00_PADDR + C67X00_SIZE - 1, 199 .flags = IORESOURCE_MEM, 200 }, 201 [1] = { /* IRQ number */ 202 .start = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ), 203 .end = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ), 204 .flags = IORESOURCE_IRQ, 205 }, 206 }; 207 208 static struct c67x00_platform_data c67x00_pdata = { 209 .sie_config = C67X00_SIE1_HOST | C67X00_SIE2_UNUSED, 210 .hpi_regstep = 4, 211 }; 212 213 static struct platform_device c67x00_device = { 214 .name = "c67x00", 215 .id = -1, 216 .num_resources = ARRAY_SIZE(c67x00_res), 217 .resource = c67x00_res, 218 .dev = { 219 .platform_data = &c67x00_pdata, 220 }, 221 }; 222 223 /*---------------------------------------------------------------------------- 224 * UART 225 */ 226 227 static struct resource serial_resource = { 228 .start = DUART16552_PADDR, 229 .end = DUART16552_PADDR + 0x1f, 230 .flags = IORESOURCE_MEM, 231 }; 232 233 static struct plat_serial8250_port serial_platform_data[] = { 234 [0] = { 235 .mapbase = DUART16552_PADDR, 236 .irq = XTENSA_PIC_LINUX_IRQ(DUART16552_INTNUM), 237 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 238 UPF_IOREMAP, 239 .iotype = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32, 240 .regshift = 2, 241 .uartclk = 0, /* set in xtavnet_init() */ 242 }, 243 { }, 244 }; 245 246 static struct platform_device xtavnet_uart = { 247 .name = "serial8250", 248 .id = PLAT8250_DEV_PLATFORM, 249 .dev = { 250 .platform_data = serial_platform_data, 251 }, 252 .num_resources = 1, 253 .resource = &serial_resource, 254 }; 255 256 /* platform devices */ 257 static struct platform_device *platform_devices[] __initdata = { 258 ðoc_device, 259 &c67x00_device, 260 &xtavnet_uart, 261 }; 262 263 264 static int __init xtavnet_init(void) 265 { 266 /* Ethernet MAC address. */ 267 ethoc_pdata.hwaddr[5] = *(u32 *)DIP_SWITCHES_VADDR; 268 269 /* Clock rate varies among FPGA bitstreams; board specific FPGA register 270 * reports the actual clock rate. 271 */ 272 serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR; 273 274 275 /* register platform devices */ 276 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 277 278 /* ETHOC driver is a bit quiet; at least display Ethernet MAC, so user 279 * knows whether they set it correctly on the DIP switches. 280 */ 281 pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr); 282 ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR; 283 284 return 0; 285 } 286 287 /* 288 * Register to be done during do_initcalls(). 289 */ 290 arch_initcall(xtavnet_init); 291 292 #endif /* CONFIG_USE_OF */ 293