1*2874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2249ac17eSChris Zankel /* 3f30c2269SUwe Zeisberger * arch/xtensa/lib/pci-auto.c 4249ac17eSChris Zankel * 5249ac17eSChris Zankel * PCI autoconfiguration library 6249ac17eSChris Zankel * 7249ac17eSChris Zankel * Copyright (C) 2001 - 2005 Tensilica Inc. 8249ac17eSChris Zankel * 9249ac17eSChris Zankel * Chris Zankel <zankel@tensilica.com, cez@zankel.net> 10249ac17eSChris Zankel * 11249ac17eSChris Zankel * Based on work from Matt Porter <mporter@mvista.com> 12249ac17eSChris Zankel */ 13249ac17eSChris Zankel 14249ac17eSChris Zankel #include <linux/kernel.h> 15249ac17eSChris Zankel #include <linux/init.h> 16249ac17eSChris Zankel #include <linux/pci.h> 17249ac17eSChris Zankel 18249ac17eSChris Zankel #include <asm/pci-bridge.h> 19249ac17eSChris Zankel 20249ac17eSChris Zankel 21249ac17eSChris Zankel /* 22249ac17eSChris Zankel * 23249ac17eSChris Zankel * Setting up a PCI 24249ac17eSChris Zankel * 25249ac17eSChris Zankel * pci_ctrl->first_busno = <first bus number (0)> 26249ac17eSChris Zankel * pci_ctrl->last_busno = <last bus number (0xff)> 27249ac17eSChris Zankel * pci_ctrl->ops = <PCI config operations> 28249ac17eSChris Zankel * pci_ctrl->map_irq = <function to return the interrupt number for a device> 29249ac17eSChris Zankel * 30249ac17eSChris Zankel * pci_ctrl->io_space.start = <IO space start address (PCI view)> 31249ac17eSChris Zankel * pci_ctrl->io_space.end = <IO space end address (PCI view)> 32249ac17eSChris Zankel * pci_ctrl->io_space.base = <IO space offset: address 0 from CPU space> 33249ac17eSChris Zankel * pci_ctrl->mem_space.start = <MEM space start address (PCI view)> 34249ac17eSChris Zankel * pci_ctrl->mem_space.end = <MEM space end address (PCI view)> 35249ac17eSChris Zankel * pci_ctrl->mem_space.base = <MEM space offset: address 0 from CPU space> 36249ac17eSChris Zankel * 37249ac17eSChris Zankel * pcibios_init_resource(&pci_ctrl->io_resource, <IO space start>, 38249ac17eSChris Zankel * <IO space end>, IORESOURCE_IO, "PCI host bridge"); 39249ac17eSChris Zankel * pcibios_init_resource(&pci_ctrl->mem_resources[0], <MEM space start>, 40249ac17eSChris Zankel * <MEM space end>, IORESOURCE_MEM, "PCI host bridge"); 41249ac17eSChris Zankel * 42249ac17eSChris Zankel * pci_ctrl->last_busno = pciauto_bus_scan(pci_ctrl,pci_ctrl->first_busno); 43249ac17eSChris Zankel * 44249ac17eSChris Zankel * int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus) 45249ac17eSChris Zankel * 46249ac17eSChris Zankel */ 47249ac17eSChris Zankel 48249ac17eSChris Zankel static int pciauto_upper_iospc; 49249ac17eSChris Zankel static int pciauto_upper_memspc; 50249ac17eSChris Zankel 51249ac17eSChris Zankel static struct pci_dev pciauto_dev; 52249ac17eSChris Zankel static struct pci_bus pciauto_bus; 53249ac17eSChris Zankel 54249ac17eSChris Zankel /* 55249ac17eSChris Zankel * Helper functions 56249ac17eSChris Zankel */ 57249ac17eSChris Zankel 58249ac17eSChris Zankel /* Initialize the bars of a PCI device. */ 59249ac17eSChris Zankel 60249ac17eSChris Zankel static void __init 61249ac17eSChris Zankel pciauto_setup_bars(struct pci_dev *dev, int bar_limit) 62249ac17eSChris Zankel { 63249ac17eSChris Zankel int bar_size; 64249ac17eSChris Zankel int bar, bar_nr; 65249ac17eSChris Zankel int *upper_limit; 66249ac17eSChris Zankel int found_mem64 = 0; 67249ac17eSChris Zankel 68249ac17eSChris Zankel for (bar = PCI_BASE_ADDRESS_0, bar_nr = 0; 69249ac17eSChris Zankel bar <= bar_limit; 70249ac17eSChris Zankel bar+=4, bar_nr++) 71249ac17eSChris Zankel { 72249ac17eSChris Zankel /* Tickle the BAR and get the size */ 73249ac17eSChris Zankel pci_write_config_dword(dev, bar, 0xffffffff); 74249ac17eSChris Zankel pci_read_config_dword(dev, bar, &bar_size); 75249ac17eSChris Zankel 76249ac17eSChris Zankel /* If BAR is not implemented go to the next BAR */ 77249ac17eSChris Zankel if (!bar_size) 78249ac17eSChris Zankel continue; 79249ac17eSChris Zankel 80249ac17eSChris Zankel /* Check the BAR type and set our address mask */ 81249ac17eSChris Zankel if (bar_size & PCI_BASE_ADDRESS_SPACE_IO) 82249ac17eSChris Zankel { 83249ac17eSChris Zankel bar_size &= PCI_BASE_ADDRESS_IO_MASK; 84249ac17eSChris Zankel upper_limit = &pciauto_upper_iospc; 85c130d3beSMax Filippov pr_debug("PCI Autoconfig: BAR %d, I/O, ", bar_nr); 86249ac17eSChris Zankel } 87249ac17eSChris Zankel else 88249ac17eSChris Zankel { 89249ac17eSChris Zankel if ((bar_size & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 90249ac17eSChris Zankel PCI_BASE_ADDRESS_MEM_TYPE_64) 91249ac17eSChris Zankel found_mem64 = 1; 92249ac17eSChris Zankel 93249ac17eSChris Zankel bar_size &= PCI_BASE_ADDRESS_MEM_MASK; 94249ac17eSChris Zankel upper_limit = &pciauto_upper_memspc; 95c130d3beSMax Filippov pr_debug("PCI Autoconfig: BAR %d, Mem, ", bar_nr); 96249ac17eSChris Zankel } 97249ac17eSChris Zankel 98249ac17eSChris Zankel /* Allocate a base address (bar_size is negative!) */ 99249ac17eSChris Zankel *upper_limit = (*upper_limit + bar_size) & bar_size; 100249ac17eSChris Zankel 101249ac17eSChris Zankel /* Write it out and update our limit */ 102249ac17eSChris Zankel pci_write_config_dword(dev, bar, *upper_limit); 103249ac17eSChris Zankel 104249ac17eSChris Zankel /* 105249ac17eSChris Zankel * If we are a 64-bit decoder then increment to the 106249ac17eSChris Zankel * upper 32 bits of the bar and force it to locate 107249ac17eSChris Zankel * in the lower 4GB of memory. 108249ac17eSChris Zankel */ 109249ac17eSChris Zankel 110249ac17eSChris Zankel if (found_mem64) 111249ac17eSChris Zankel pci_write_config_dword(dev, (bar+=4), 0x00000000); 112249ac17eSChris Zankel 113c130d3beSMax Filippov pr_debug("size=0x%x, address=0x%x\n", 114c130d3beSMax Filippov ~bar_size + 1, *upper_limit); 115249ac17eSChris Zankel } 116249ac17eSChris Zankel } 117249ac17eSChris Zankel 118249ac17eSChris Zankel /* Initialize the interrupt number. */ 119249ac17eSChris Zankel 120249ac17eSChris Zankel static void __init 121249ac17eSChris Zankel pciauto_setup_irq(struct pci_controller* pci_ctrl,struct pci_dev *dev,int devfn) 122249ac17eSChris Zankel { 123249ac17eSChris Zankel u8 pin; 124249ac17eSChris Zankel int irq = 0; 125249ac17eSChris Zankel 126249ac17eSChris Zankel pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 127249ac17eSChris Zankel 128249ac17eSChris Zankel /* Fix illegal pin numbers. */ 129249ac17eSChris Zankel 130249ac17eSChris Zankel if (pin == 0 || pin > 4) 131249ac17eSChris Zankel pin = 1; 132249ac17eSChris Zankel 133249ac17eSChris Zankel if (pci_ctrl->map_irq) 134249ac17eSChris Zankel irq = pci_ctrl->map_irq(dev, PCI_SLOT(devfn), pin); 135249ac17eSChris Zankel 136249ac17eSChris Zankel if (irq == -1) 137249ac17eSChris Zankel irq = 0; 138249ac17eSChris Zankel 139c130d3beSMax Filippov pr_debug("PCI Autoconfig: Interrupt %d, pin %d\n", irq, pin); 140249ac17eSChris Zankel 141249ac17eSChris Zankel pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 142249ac17eSChris Zankel } 143249ac17eSChris Zankel 144249ac17eSChris Zankel 145249ac17eSChris Zankel static void __init 146249ac17eSChris Zankel pciauto_prescan_setup_bridge(struct pci_dev *dev, int current_bus, 147249ac17eSChris Zankel int sub_bus, int *iosave, int *memsave) 148249ac17eSChris Zankel { 149249ac17eSChris Zankel /* Configure bus number registers */ 150249ac17eSChris Zankel pci_write_config_byte(dev, PCI_PRIMARY_BUS, current_bus); 151249ac17eSChris Zankel pci_write_config_byte(dev, PCI_SECONDARY_BUS, sub_bus + 1); 152249ac17eSChris Zankel pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, 0xff); 153249ac17eSChris Zankel 154249ac17eSChris Zankel /* Round memory allocator to 1MB boundary */ 155249ac17eSChris Zankel pciauto_upper_memspc &= ~(0x100000 - 1); 156249ac17eSChris Zankel *memsave = pciauto_upper_memspc; 157249ac17eSChris Zankel 158249ac17eSChris Zankel /* Round I/O allocator to 4KB boundary */ 159249ac17eSChris Zankel pciauto_upper_iospc &= ~(0x1000 - 1); 160249ac17eSChris Zankel *iosave = pciauto_upper_iospc; 161249ac17eSChris Zankel 162249ac17eSChris Zankel /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 163249ac17eSChris Zankel pci_write_config_word(dev, PCI_MEMORY_LIMIT, 164249ac17eSChris Zankel ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16); 165249ac17eSChris Zankel pci_write_config_byte(dev, PCI_IO_LIMIT, 166249ac17eSChris Zankel ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8); 167249ac17eSChris Zankel pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 168249ac17eSChris Zankel ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16); 169249ac17eSChris Zankel } 170249ac17eSChris Zankel 171249ac17eSChris Zankel static void __init 172249ac17eSChris Zankel pciauto_postscan_setup_bridge(struct pci_dev *dev, int current_bus, int sub_bus, 173249ac17eSChris Zankel int *iosave, int *memsave) 174249ac17eSChris Zankel { 175249ac17eSChris Zankel int cmdstat; 176249ac17eSChris Zankel 177249ac17eSChris Zankel /* Configure bus number registers */ 178249ac17eSChris Zankel pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, sub_bus); 179249ac17eSChris Zankel 180249ac17eSChris Zankel /* 181249ac17eSChris Zankel * Round memory allocator to 1MB boundary. 182249ac17eSChris Zankel * If no space used, allocate minimum. 183249ac17eSChris Zankel */ 184249ac17eSChris Zankel pciauto_upper_memspc &= ~(0x100000 - 1); 185249ac17eSChris Zankel if (*memsave == pciauto_upper_memspc) 186249ac17eSChris Zankel pciauto_upper_memspc -= 0x00100000; 187249ac17eSChris Zankel 188249ac17eSChris Zankel pci_write_config_word(dev, PCI_MEMORY_BASE, pciauto_upper_memspc >> 16); 189249ac17eSChris Zankel 190249ac17eSChris Zankel /* Allocate 1MB for pre-fretch */ 191249ac17eSChris Zankel pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 192249ac17eSChris Zankel ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16); 193249ac17eSChris Zankel 194249ac17eSChris Zankel pciauto_upper_memspc -= 0x100000; 195249ac17eSChris Zankel 196249ac17eSChris Zankel pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 197249ac17eSChris Zankel pciauto_upper_memspc >> 16); 198249ac17eSChris Zankel 199249ac17eSChris Zankel /* Round I/O allocator to 4KB boundary */ 200249ac17eSChris Zankel pciauto_upper_iospc &= ~(0x1000 - 1); 201249ac17eSChris Zankel if (*iosave == pciauto_upper_iospc) 202249ac17eSChris Zankel pciauto_upper_iospc -= 0x1000; 203249ac17eSChris Zankel 204249ac17eSChris Zankel pci_write_config_byte(dev, PCI_IO_BASE, 205249ac17eSChris Zankel (pciauto_upper_iospc & 0x0000f000) >> 8); 206249ac17eSChris Zankel pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 207249ac17eSChris Zankel pciauto_upper_iospc >> 16); 208249ac17eSChris Zankel 209249ac17eSChris Zankel /* Enable memory and I/O accesses, enable bus master */ 210249ac17eSChris Zankel pci_read_config_dword(dev, PCI_COMMAND, &cmdstat); 211249ac17eSChris Zankel pci_write_config_dword(dev, PCI_COMMAND, 212249ac17eSChris Zankel cmdstat | 213249ac17eSChris Zankel PCI_COMMAND_IO | 214249ac17eSChris Zankel PCI_COMMAND_MEMORY | 215249ac17eSChris Zankel PCI_COMMAND_MASTER); 216249ac17eSChris Zankel } 217249ac17eSChris Zankel 218249ac17eSChris Zankel /* 219249ac17eSChris Zankel * Scan the current PCI bus. 220249ac17eSChris Zankel */ 221249ac17eSChris Zankel 222249ac17eSChris Zankel 223249ac17eSChris Zankel int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus) 224249ac17eSChris Zankel { 225249ac17eSChris Zankel int sub_bus, pci_devfn, pci_class, cmdstat, found_multi=0; 226249ac17eSChris Zankel unsigned short vid; 227249ac17eSChris Zankel unsigned char header_type; 228249ac17eSChris Zankel struct pci_dev *dev = &pciauto_dev; 229249ac17eSChris Zankel 230249ac17eSChris Zankel pciauto_dev.bus = &pciauto_bus; 231249ac17eSChris Zankel pciauto_dev.sysdata = pci_ctrl; 232249ac17eSChris Zankel pciauto_bus.ops = pci_ctrl->ops; 233249ac17eSChris Zankel 234249ac17eSChris Zankel /* 235249ac17eSChris Zankel * Fetch our I/O and memory space upper boundaries used 236249ac17eSChris Zankel * to allocated base addresses on this pci_controller. 237249ac17eSChris Zankel */ 238249ac17eSChris Zankel 239249ac17eSChris Zankel if (current_bus == pci_ctrl->first_busno) 240249ac17eSChris Zankel { 241249ac17eSChris Zankel pciauto_upper_iospc = pci_ctrl->io_resource.end + 1; 242249ac17eSChris Zankel pciauto_upper_memspc = pci_ctrl->mem_resources[0].end + 1; 243249ac17eSChris Zankel } 244249ac17eSChris Zankel 245249ac17eSChris Zankel sub_bus = current_bus; 246249ac17eSChris Zankel 247249ac17eSChris Zankel for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) 248249ac17eSChris Zankel { 249249ac17eSChris Zankel /* Skip our host bridge */ 250249ac17eSChris Zankel if ((current_bus == pci_ctrl->first_busno) && (pci_devfn == 0)) 251249ac17eSChris Zankel continue; 252249ac17eSChris Zankel 253249ac17eSChris Zankel if (PCI_FUNC(pci_devfn) && !found_multi) 254249ac17eSChris Zankel continue; 255249ac17eSChris Zankel 256249ac17eSChris Zankel pciauto_bus.number = current_bus; 257249ac17eSChris Zankel pciauto_dev.devfn = pci_devfn; 258249ac17eSChris Zankel 259249ac17eSChris Zankel /* If config space read fails from this device, move on */ 260249ac17eSChris Zankel if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type)) 261249ac17eSChris Zankel continue; 262249ac17eSChris Zankel 263249ac17eSChris Zankel if (!PCI_FUNC(pci_devfn)) 264249ac17eSChris Zankel found_multi = header_type & 0x80; 265249ac17eSChris Zankel pci_read_config_word(dev, PCI_VENDOR_ID, &vid); 266249ac17eSChris Zankel 267249ac17eSChris Zankel if (vid == 0xffff || vid == 0x0000) { 268249ac17eSChris Zankel found_multi = 0; 269249ac17eSChris Zankel continue; 270249ac17eSChris Zankel } 271249ac17eSChris Zankel 272249ac17eSChris Zankel pci_read_config_dword(dev, PCI_CLASS_REVISION, &pci_class); 273249ac17eSChris Zankel 274249ac17eSChris Zankel if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) { 275249ac17eSChris Zankel 276249ac17eSChris Zankel int iosave, memsave; 277249ac17eSChris Zankel 278c130d3beSMax Filippov pr_debug("PCI Autoconfig: Found P2P bridge, device %d\n", 279249ac17eSChris Zankel PCI_SLOT(pci_devfn)); 280249ac17eSChris Zankel 281249ac17eSChris Zankel /* Allocate PCI I/O and/or memory space */ 282249ac17eSChris Zankel pciauto_setup_bars(dev, PCI_BASE_ADDRESS_1); 283249ac17eSChris Zankel 284249ac17eSChris Zankel pciauto_prescan_setup_bridge(dev, current_bus, sub_bus, 285249ac17eSChris Zankel &iosave, &memsave); 286249ac17eSChris Zankel sub_bus = pciauto_bus_scan(pci_ctrl, sub_bus+1); 287249ac17eSChris Zankel pciauto_postscan_setup_bridge(dev, current_bus, sub_bus, 288249ac17eSChris Zankel &iosave, &memsave); 289249ac17eSChris Zankel pciauto_bus.number = current_bus; 290249ac17eSChris Zankel 291249ac17eSChris Zankel continue; 292249ac17eSChris Zankel 293249ac17eSChris Zankel } 294249ac17eSChris Zankel 295249ac17eSChris Zankel /* 296249ac17eSChris Zankel * Found a peripheral, enable some standard 297249ac17eSChris Zankel * settings 298249ac17eSChris Zankel */ 299249ac17eSChris Zankel 300249ac17eSChris Zankel pci_read_config_dword(dev, PCI_COMMAND, &cmdstat); 301249ac17eSChris Zankel pci_write_config_dword(dev, PCI_COMMAND, 302249ac17eSChris Zankel cmdstat | 303249ac17eSChris Zankel PCI_COMMAND_IO | 304249ac17eSChris Zankel PCI_COMMAND_MEMORY | 305249ac17eSChris Zankel PCI_COMMAND_MASTER); 306249ac17eSChris Zankel pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80); 307249ac17eSChris Zankel 308249ac17eSChris Zankel /* Allocate PCI I/O and/or memory space */ 309c130d3beSMax Filippov pr_debug("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n", 310249ac17eSChris Zankel current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn)); 311249ac17eSChris Zankel 312249ac17eSChris Zankel pciauto_setup_bars(dev, PCI_BASE_ADDRESS_5); 313249ac17eSChris Zankel pciauto_setup_irq(pci_ctrl, dev, pci_devfn); 314249ac17eSChris Zankel } 315249ac17eSChris Zankel return sub_bus; 316249ac17eSChris Zankel } 317