1*249ac17eSChris Zankel /* 2*249ac17eSChris Zankel * arch/xtensa/kernel/pci-auto.c 3*249ac17eSChris Zankel * 4*249ac17eSChris Zankel * PCI autoconfiguration library 5*249ac17eSChris Zankel * 6*249ac17eSChris Zankel * Copyright (C) 2001 - 2005 Tensilica Inc. 7*249ac17eSChris Zankel * 8*249ac17eSChris Zankel * Chris Zankel <zankel@tensilica.com, cez@zankel.net> 9*249ac17eSChris Zankel * 10*249ac17eSChris Zankel * Based on work from Matt Porter <mporter@mvista.com> 11*249ac17eSChris Zankel * 12*249ac17eSChris Zankel * This program is free software; you can redistribute it and/or modify it 13*249ac17eSChris Zankel * under the terms of the GNU General Public License as published by the 14*249ac17eSChris Zankel * Free Software Foundation; either version 2 of the License, or (at your 15*249ac17eSChris Zankel * option) any later version. 16*249ac17eSChris Zankel */ 17*249ac17eSChris Zankel 18*249ac17eSChris Zankel #include <linux/kernel.h> 19*249ac17eSChris Zankel #include <linux/init.h> 20*249ac17eSChris Zankel #include <linux/pci.h> 21*249ac17eSChris Zankel 22*249ac17eSChris Zankel #include <asm/pci-bridge.h> 23*249ac17eSChris Zankel 24*249ac17eSChris Zankel 25*249ac17eSChris Zankel /* 26*249ac17eSChris Zankel * 27*249ac17eSChris Zankel * Setting up a PCI 28*249ac17eSChris Zankel * 29*249ac17eSChris Zankel * pci_ctrl->first_busno = <first bus number (0)> 30*249ac17eSChris Zankel * pci_ctrl->last_busno = <last bus number (0xff)> 31*249ac17eSChris Zankel * pci_ctrl->ops = <PCI config operations> 32*249ac17eSChris Zankel * pci_ctrl->map_irq = <function to return the interrupt number for a device> 33*249ac17eSChris Zankel * 34*249ac17eSChris Zankel * pci_ctrl->io_space.start = <IO space start address (PCI view)> 35*249ac17eSChris Zankel * pci_ctrl->io_space.end = <IO space end address (PCI view)> 36*249ac17eSChris Zankel * pci_ctrl->io_space.base = <IO space offset: address 0 from CPU space> 37*249ac17eSChris Zankel * pci_ctrl->mem_space.start = <MEM space start address (PCI view)> 38*249ac17eSChris Zankel * pci_ctrl->mem_space.end = <MEM space end address (PCI view)> 39*249ac17eSChris Zankel * pci_ctrl->mem_space.base = <MEM space offset: address 0 from CPU space> 40*249ac17eSChris Zankel * 41*249ac17eSChris Zankel * pcibios_init_resource(&pci_ctrl->io_resource, <IO space start>, 42*249ac17eSChris Zankel * <IO space end>, IORESOURCE_IO, "PCI host bridge"); 43*249ac17eSChris Zankel * pcibios_init_resource(&pci_ctrl->mem_resources[0], <MEM space start>, 44*249ac17eSChris Zankel * <MEM space end>, IORESOURCE_MEM, "PCI host bridge"); 45*249ac17eSChris Zankel * 46*249ac17eSChris Zankel * pci_ctrl->last_busno = pciauto_bus_scan(pci_ctrl,pci_ctrl->first_busno); 47*249ac17eSChris Zankel * 48*249ac17eSChris Zankel * int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus) 49*249ac17eSChris Zankel * 50*249ac17eSChris Zankel */ 51*249ac17eSChris Zankel 52*249ac17eSChris Zankel 53*249ac17eSChris Zankel /* define DEBUG to print some debugging messages. */ 54*249ac17eSChris Zankel 55*249ac17eSChris Zankel #undef DEBUG 56*249ac17eSChris Zankel 57*249ac17eSChris Zankel #ifdef DEBUG 58*249ac17eSChris Zankel # define DBG(x...) printk(x) 59*249ac17eSChris Zankel #else 60*249ac17eSChris Zankel # define DBG(x...) 61*249ac17eSChris Zankel #endif 62*249ac17eSChris Zankel 63*249ac17eSChris Zankel static int pciauto_upper_iospc; 64*249ac17eSChris Zankel static int pciauto_upper_memspc; 65*249ac17eSChris Zankel 66*249ac17eSChris Zankel static struct pci_dev pciauto_dev; 67*249ac17eSChris Zankel static struct pci_bus pciauto_bus; 68*249ac17eSChris Zankel 69*249ac17eSChris Zankel /* 70*249ac17eSChris Zankel * Helper functions 71*249ac17eSChris Zankel */ 72*249ac17eSChris Zankel 73*249ac17eSChris Zankel /* Initialize the bars of a PCI device. */ 74*249ac17eSChris Zankel 75*249ac17eSChris Zankel static void __init 76*249ac17eSChris Zankel pciauto_setup_bars(struct pci_dev *dev, int bar_limit) 77*249ac17eSChris Zankel { 78*249ac17eSChris Zankel int bar_size; 79*249ac17eSChris Zankel int bar, bar_nr; 80*249ac17eSChris Zankel int *upper_limit; 81*249ac17eSChris Zankel int found_mem64 = 0; 82*249ac17eSChris Zankel 83*249ac17eSChris Zankel for (bar = PCI_BASE_ADDRESS_0, bar_nr = 0; 84*249ac17eSChris Zankel bar <= bar_limit; 85*249ac17eSChris Zankel bar+=4, bar_nr++) 86*249ac17eSChris Zankel { 87*249ac17eSChris Zankel /* Tickle the BAR and get the size */ 88*249ac17eSChris Zankel pci_write_config_dword(dev, bar, 0xffffffff); 89*249ac17eSChris Zankel pci_read_config_dword(dev, bar, &bar_size); 90*249ac17eSChris Zankel 91*249ac17eSChris Zankel /* If BAR is not implemented go to the next BAR */ 92*249ac17eSChris Zankel if (!bar_size) 93*249ac17eSChris Zankel continue; 94*249ac17eSChris Zankel 95*249ac17eSChris Zankel /* Check the BAR type and set our address mask */ 96*249ac17eSChris Zankel if (bar_size & PCI_BASE_ADDRESS_SPACE_IO) 97*249ac17eSChris Zankel { 98*249ac17eSChris Zankel bar_size &= PCI_BASE_ADDRESS_IO_MASK; 99*249ac17eSChris Zankel upper_limit = &pciauto_upper_iospc; 100*249ac17eSChris Zankel DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr); 101*249ac17eSChris Zankel } 102*249ac17eSChris Zankel else 103*249ac17eSChris Zankel { 104*249ac17eSChris Zankel if ((bar_size & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == 105*249ac17eSChris Zankel PCI_BASE_ADDRESS_MEM_TYPE_64) 106*249ac17eSChris Zankel found_mem64 = 1; 107*249ac17eSChris Zankel 108*249ac17eSChris Zankel bar_size &= PCI_BASE_ADDRESS_MEM_MASK; 109*249ac17eSChris Zankel upper_limit = &pciauto_upper_memspc; 110*249ac17eSChris Zankel DBG("PCI Autoconfig: BAR %d, Mem, ", bar_nr); 111*249ac17eSChris Zankel } 112*249ac17eSChris Zankel 113*249ac17eSChris Zankel /* Allocate a base address (bar_size is negative!) */ 114*249ac17eSChris Zankel *upper_limit = (*upper_limit + bar_size) & bar_size; 115*249ac17eSChris Zankel 116*249ac17eSChris Zankel /* Write it out and update our limit */ 117*249ac17eSChris Zankel pci_write_config_dword(dev, bar, *upper_limit); 118*249ac17eSChris Zankel 119*249ac17eSChris Zankel /* 120*249ac17eSChris Zankel * If we are a 64-bit decoder then increment to the 121*249ac17eSChris Zankel * upper 32 bits of the bar and force it to locate 122*249ac17eSChris Zankel * in the lower 4GB of memory. 123*249ac17eSChris Zankel */ 124*249ac17eSChris Zankel 125*249ac17eSChris Zankel if (found_mem64) 126*249ac17eSChris Zankel pci_write_config_dword(dev, (bar+=4), 0x00000000); 127*249ac17eSChris Zankel 128*249ac17eSChris Zankel DBG("size=0x%x, address=0x%x\n", ~bar_size + 1, *upper_limit); 129*249ac17eSChris Zankel } 130*249ac17eSChris Zankel } 131*249ac17eSChris Zankel 132*249ac17eSChris Zankel /* Initialize the interrupt number. */ 133*249ac17eSChris Zankel 134*249ac17eSChris Zankel static void __init 135*249ac17eSChris Zankel pciauto_setup_irq(struct pci_controller* pci_ctrl,struct pci_dev *dev,int devfn) 136*249ac17eSChris Zankel { 137*249ac17eSChris Zankel u8 pin; 138*249ac17eSChris Zankel int irq = 0; 139*249ac17eSChris Zankel 140*249ac17eSChris Zankel pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 141*249ac17eSChris Zankel 142*249ac17eSChris Zankel /* Fix illegal pin numbers. */ 143*249ac17eSChris Zankel 144*249ac17eSChris Zankel if (pin == 0 || pin > 4) 145*249ac17eSChris Zankel pin = 1; 146*249ac17eSChris Zankel 147*249ac17eSChris Zankel if (pci_ctrl->map_irq) 148*249ac17eSChris Zankel irq = pci_ctrl->map_irq(dev, PCI_SLOT(devfn), pin); 149*249ac17eSChris Zankel 150*249ac17eSChris Zankel if (irq == -1) 151*249ac17eSChris Zankel irq = 0; 152*249ac17eSChris Zankel 153*249ac17eSChris Zankel DBG("PCI Autoconfig: Interrupt %d, pin %d\n", irq, pin); 154*249ac17eSChris Zankel 155*249ac17eSChris Zankel pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 156*249ac17eSChris Zankel } 157*249ac17eSChris Zankel 158*249ac17eSChris Zankel 159*249ac17eSChris Zankel static void __init 160*249ac17eSChris Zankel pciauto_prescan_setup_bridge(struct pci_dev *dev, int current_bus, 161*249ac17eSChris Zankel int sub_bus, int *iosave, int *memsave) 162*249ac17eSChris Zankel { 163*249ac17eSChris Zankel /* Configure bus number registers */ 164*249ac17eSChris Zankel pci_write_config_byte(dev, PCI_PRIMARY_BUS, current_bus); 165*249ac17eSChris Zankel pci_write_config_byte(dev, PCI_SECONDARY_BUS, sub_bus + 1); 166*249ac17eSChris Zankel pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, 0xff); 167*249ac17eSChris Zankel 168*249ac17eSChris Zankel /* Round memory allocator to 1MB boundary */ 169*249ac17eSChris Zankel pciauto_upper_memspc &= ~(0x100000 - 1); 170*249ac17eSChris Zankel *memsave = pciauto_upper_memspc; 171*249ac17eSChris Zankel 172*249ac17eSChris Zankel /* Round I/O allocator to 4KB boundary */ 173*249ac17eSChris Zankel pciauto_upper_iospc &= ~(0x1000 - 1); 174*249ac17eSChris Zankel *iosave = pciauto_upper_iospc; 175*249ac17eSChris Zankel 176*249ac17eSChris Zankel /* Set up memory and I/O filter limits, assume 32-bit I/O space */ 177*249ac17eSChris Zankel pci_write_config_word(dev, PCI_MEMORY_LIMIT, 178*249ac17eSChris Zankel ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16); 179*249ac17eSChris Zankel pci_write_config_byte(dev, PCI_IO_LIMIT, 180*249ac17eSChris Zankel ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8); 181*249ac17eSChris Zankel pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 182*249ac17eSChris Zankel ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16); 183*249ac17eSChris Zankel } 184*249ac17eSChris Zankel 185*249ac17eSChris Zankel static void __init 186*249ac17eSChris Zankel pciauto_postscan_setup_bridge(struct pci_dev *dev, int current_bus, int sub_bus, 187*249ac17eSChris Zankel int *iosave, int *memsave) 188*249ac17eSChris Zankel { 189*249ac17eSChris Zankel int cmdstat; 190*249ac17eSChris Zankel 191*249ac17eSChris Zankel /* Configure bus number registers */ 192*249ac17eSChris Zankel pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, sub_bus); 193*249ac17eSChris Zankel 194*249ac17eSChris Zankel /* 195*249ac17eSChris Zankel * Round memory allocator to 1MB boundary. 196*249ac17eSChris Zankel * If no space used, allocate minimum. 197*249ac17eSChris Zankel */ 198*249ac17eSChris Zankel pciauto_upper_memspc &= ~(0x100000 - 1); 199*249ac17eSChris Zankel if (*memsave == pciauto_upper_memspc) 200*249ac17eSChris Zankel pciauto_upper_memspc -= 0x00100000; 201*249ac17eSChris Zankel 202*249ac17eSChris Zankel pci_write_config_word(dev, PCI_MEMORY_BASE, pciauto_upper_memspc >> 16); 203*249ac17eSChris Zankel 204*249ac17eSChris Zankel /* Allocate 1MB for pre-fretch */ 205*249ac17eSChris Zankel pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 206*249ac17eSChris Zankel ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16); 207*249ac17eSChris Zankel 208*249ac17eSChris Zankel pciauto_upper_memspc -= 0x100000; 209*249ac17eSChris Zankel 210*249ac17eSChris Zankel pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 211*249ac17eSChris Zankel pciauto_upper_memspc >> 16); 212*249ac17eSChris Zankel 213*249ac17eSChris Zankel /* Round I/O allocator to 4KB boundary */ 214*249ac17eSChris Zankel pciauto_upper_iospc &= ~(0x1000 - 1); 215*249ac17eSChris Zankel if (*iosave == pciauto_upper_iospc) 216*249ac17eSChris Zankel pciauto_upper_iospc -= 0x1000; 217*249ac17eSChris Zankel 218*249ac17eSChris Zankel pci_write_config_byte(dev, PCI_IO_BASE, 219*249ac17eSChris Zankel (pciauto_upper_iospc & 0x0000f000) >> 8); 220*249ac17eSChris Zankel pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 221*249ac17eSChris Zankel pciauto_upper_iospc >> 16); 222*249ac17eSChris Zankel 223*249ac17eSChris Zankel /* Enable memory and I/O accesses, enable bus master */ 224*249ac17eSChris Zankel pci_read_config_dword(dev, PCI_COMMAND, &cmdstat); 225*249ac17eSChris Zankel pci_write_config_dword(dev, PCI_COMMAND, 226*249ac17eSChris Zankel cmdstat | 227*249ac17eSChris Zankel PCI_COMMAND_IO | 228*249ac17eSChris Zankel PCI_COMMAND_MEMORY | 229*249ac17eSChris Zankel PCI_COMMAND_MASTER); 230*249ac17eSChris Zankel } 231*249ac17eSChris Zankel 232*249ac17eSChris Zankel /* 233*249ac17eSChris Zankel * Scan the current PCI bus. 234*249ac17eSChris Zankel */ 235*249ac17eSChris Zankel 236*249ac17eSChris Zankel 237*249ac17eSChris Zankel int __init pciauto_bus_scan(struct pci_controller *pci_ctrl, int current_bus) 238*249ac17eSChris Zankel { 239*249ac17eSChris Zankel int sub_bus, pci_devfn, pci_class, cmdstat, found_multi=0; 240*249ac17eSChris Zankel unsigned short vid; 241*249ac17eSChris Zankel unsigned char header_type; 242*249ac17eSChris Zankel struct pci_dev *dev = &pciauto_dev; 243*249ac17eSChris Zankel 244*249ac17eSChris Zankel pciauto_dev.bus = &pciauto_bus; 245*249ac17eSChris Zankel pciauto_dev.sysdata = pci_ctrl; 246*249ac17eSChris Zankel pciauto_bus.ops = pci_ctrl->ops; 247*249ac17eSChris Zankel 248*249ac17eSChris Zankel /* 249*249ac17eSChris Zankel * Fetch our I/O and memory space upper boundaries used 250*249ac17eSChris Zankel * to allocated base addresses on this pci_controller. 251*249ac17eSChris Zankel */ 252*249ac17eSChris Zankel 253*249ac17eSChris Zankel if (current_bus == pci_ctrl->first_busno) 254*249ac17eSChris Zankel { 255*249ac17eSChris Zankel pciauto_upper_iospc = pci_ctrl->io_resource.end + 1; 256*249ac17eSChris Zankel pciauto_upper_memspc = pci_ctrl->mem_resources[0].end + 1; 257*249ac17eSChris Zankel } 258*249ac17eSChris Zankel 259*249ac17eSChris Zankel sub_bus = current_bus; 260*249ac17eSChris Zankel 261*249ac17eSChris Zankel for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) 262*249ac17eSChris Zankel { 263*249ac17eSChris Zankel /* Skip our host bridge */ 264*249ac17eSChris Zankel if ((current_bus == pci_ctrl->first_busno) && (pci_devfn == 0)) 265*249ac17eSChris Zankel continue; 266*249ac17eSChris Zankel 267*249ac17eSChris Zankel if (PCI_FUNC(pci_devfn) && !found_multi) 268*249ac17eSChris Zankel continue; 269*249ac17eSChris Zankel 270*249ac17eSChris Zankel pciauto_bus.number = current_bus; 271*249ac17eSChris Zankel pciauto_dev.devfn = pci_devfn; 272*249ac17eSChris Zankel 273*249ac17eSChris Zankel /* If config space read fails from this device, move on */ 274*249ac17eSChris Zankel if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type)) 275*249ac17eSChris Zankel continue; 276*249ac17eSChris Zankel 277*249ac17eSChris Zankel if (!PCI_FUNC(pci_devfn)) 278*249ac17eSChris Zankel found_multi = header_type & 0x80; 279*249ac17eSChris Zankel pci_read_config_word(dev, PCI_VENDOR_ID, &vid); 280*249ac17eSChris Zankel 281*249ac17eSChris Zankel if (vid == 0xffff || vid == 0x0000) { 282*249ac17eSChris Zankel found_multi = 0; 283*249ac17eSChris Zankel continue; 284*249ac17eSChris Zankel } 285*249ac17eSChris Zankel 286*249ac17eSChris Zankel pci_read_config_dword(dev, PCI_CLASS_REVISION, &pci_class); 287*249ac17eSChris Zankel 288*249ac17eSChris Zankel if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) { 289*249ac17eSChris Zankel 290*249ac17eSChris Zankel int iosave, memsave; 291*249ac17eSChris Zankel 292*249ac17eSChris Zankel DBG("PCI Autoconfig: Found P2P bridge, device %d\n", 293*249ac17eSChris Zankel PCI_SLOT(pci_devfn)); 294*249ac17eSChris Zankel 295*249ac17eSChris Zankel /* Allocate PCI I/O and/or memory space */ 296*249ac17eSChris Zankel pciauto_setup_bars(dev, PCI_BASE_ADDRESS_1); 297*249ac17eSChris Zankel 298*249ac17eSChris Zankel pciauto_prescan_setup_bridge(dev, current_bus, sub_bus, 299*249ac17eSChris Zankel &iosave, &memsave); 300*249ac17eSChris Zankel sub_bus = pciauto_bus_scan(pci_ctrl, sub_bus+1); 301*249ac17eSChris Zankel pciauto_postscan_setup_bridge(dev, current_bus, sub_bus, 302*249ac17eSChris Zankel &iosave, &memsave); 303*249ac17eSChris Zankel pciauto_bus.number = current_bus; 304*249ac17eSChris Zankel 305*249ac17eSChris Zankel continue; 306*249ac17eSChris Zankel 307*249ac17eSChris Zankel } 308*249ac17eSChris Zankel 309*249ac17eSChris Zankel 310*249ac17eSChris Zankel #if 0 311*249ac17eSChris Zankel /* Skip legacy mode IDE controller */ 312*249ac17eSChris Zankel 313*249ac17eSChris Zankel if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) { 314*249ac17eSChris Zankel 315*249ac17eSChris Zankel unsigned char prg_iface; 316*249ac17eSChris Zankel pci_read_config_byte(dev, PCI_CLASS_PROG, &prg_iface); 317*249ac17eSChris Zankel 318*249ac17eSChris Zankel if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { 319*249ac17eSChris Zankel DBG("PCI Autoconfig: Skipping legacy mode " 320*249ac17eSChris Zankel "IDE controller\n"); 321*249ac17eSChris Zankel continue; 322*249ac17eSChris Zankel } 323*249ac17eSChris Zankel } 324*249ac17eSChris Zankel #endif 325*249ac17eSChris Zankel 326*249ac17eSChris Zankel /* 327*249ac17eSChris Zankel * Found a peripheral, enable some standard 328*249ac17eSChris Zankel * settings 329*249ac17eSChris Zankel */ 330*249ac17eSChris Zankel 331*249ac17eSChris Zankel pci_read_config_dword(dev, PCI_COMMAND, &cmdstat); 332*249ac17eSChris Zankel pci_write_config_dword(dev, PCI_COMMAND, 333*249ac17eSChris Zankel cmdstat | 334*249ac17eSChris Zankel PCI_COMMAND_IO | 335*249ac17eSChris Zankel PCI_COMMAND_MEMORY | 336*249ac17eSChris Zankel PCI_COMMAND_MASTER); 337*249ac17eSChris Zankel pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80); 338*249ac17eSChris Zankel 339*249ac17eSChris Zankel /* Allocate PCI I/O and/or memory space */ 340*249ac17eSChris Zankel DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n", 341*249ac17eSChris Zankel current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) ); 342*249ac17eSChris Zankel 343*249ac17eSChris Zankel pciauto_setup_bars(dev, PCI_BASE_ADDRESS_5); 344*249ac17eSChris Zankel pciauto_setup_irq(pci_ctrl, dev, pci_devfn); 345*249ac17eSChris Zankel } 346*249ac17eSChris Zankel return sub_bus; 347*249ac17eSChris Zankel } 348*249ac17eSChris Zankel 349*249ac17eSChris Zankel 350*249ac17eSChris Zankel 351*249ac17eSChris Zankel 352*249ac17eSChris Zankel 353