xref: /linux/arch/xtensa/kernel/setup.c (revision c130d3be84afb9b5a30ce4f715f88a1c1dcc4114) 
1 /*
2  * arch/xtensa/kernel/setup.c
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1995  Linus Torvalds
9  * Copyright (C) 2001 - 2005  Tensilica Inc.
10  * Copyright (C) 2014 - 2016  Cadence Design Systems Inc.
11  *
12  * Chris Zankel	<chris@zankel.net>
13  * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
14  * Kevin Chea
15  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
16  */
17 
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/mm.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/bootmem.h>
24 #include <linux/kernel.h>
25 #include <linux/percpu.h>
26 #include <linux/cpu.h>
27 #include <linux/of.h>
28 #include <linux/of_fdt.h>
29 
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
32 #endif
33 
34 #ifdef CONFIG_PROC_FS
35 # include <linux/seq_file.h>
36 #endif
37 
38 #include <asm/bootparam.h>
39 #include <asm/mmu_context.h>
40 #include <asm/pgtable.h>
41 #include <asm/processor.h>
42 #include <asm/timex.h>
43 #include <asm/platform.h>
44 #include <asm/page.h>
45 #include <asm/setup.h>
46 #include <asm/param.h>
47 #include <asm/smp.h>
48 #include <asm/sysmem.h>
49 
50 #include <platform/hardware.h>
51 
52 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
53 struct screen_info screen_info = {
54 	.orig_x = 0,
55 	.orig_y = 24,
56 	.orig_video_cols = 80,
57 	.orig_video_lines = 24,
58 	.orig_video_isVGA = 1,
59 	.orig_video_points = 16,
60 };
61 #endif
62 
63 #ifdef CONFIG_BLK_DEV_INITRD
64 extern unsigned long initrd_start;
65 extern unsigned long initrd_end;
66 int initrd_is_mapped = 0;
67 extern int initrd_below_start_ok;
68 #endif
69 
70 #ifdef CONFIG_OF
71 void *dtb_start = __dtb_start;
72 #endif
73 
74 extern unsigned long loops_per_jiffy;
75 
76 /* Command line specified as configuration option. */
77 
78 static char __initdata command_line[COMMAND_LINE_SIZE];
79 
80 #ifdef CONFIG_CMDLINE_BOOL
81 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
82 #endif
83 
84 /*
85  * Boot parameter parsing.
86  *
87  * The Xtensa port uses a list of variable-sized tags to pass data to
88  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
89  * to be recognised. The list is terminated with a zero-sized
90  * BP_TAG_LAST tag.
91  */
92 
93 typedef struct tagtable {
94 	u32 tag;
95 	int (*parse)(const bp_tag_t*);
96 } tagtable_t;
97 
98 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
99 	__attribute__((used, section(".taglist"))) = { tag, fn }
100 
101 /* parse current tag */
102 
103 static int __init parse_tag_mem(const bp_tag_t *tag)
104 {
105 	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
106 
107 	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
108 		return -1;
109 
110 	return memblock_add(mi->start, mi->end - mi->start);
111 }
112 
113 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
114 
115 #ifdef CONFIG_BLK_DEV_INITRD
116 
117 static int __init parse_tag_initrd(const bp_tag_t* tag)
118 {
119 	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
120 
121 	initrd_start = (unsigned long)__va(mi->start);
122 	initrd_end = (unsigned long)__va(mi->end);
123 
124 	return 0;
125 }
126 
127 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
128 
129 #endif /* CONFIG_BLK_DEV_INITRD */
130 
131 #ifdef CONFIG_OF
132 
133 static int __init parse_tag_fdt(const bp_tag_t *tag)
134 {
135 	dtb_start = __va(tag->data[0]);
136 	return 0;
137 }
138 
139 __tagtable(BP_TAG_FDT, parse_tag_fdt);
140 
141 #endif /* CONFIG_OF */
142 
143 static int __init parse_tag_cmdline(const bp_tag_t* tag)
144 {
145 	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
146 	return 0;
147 }
148 
149 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
150 
151 static int __init parse_bootparam(const bp_tag_t* tag)
152 {
153 	extern tagtable_t __tagtable_begin, __tagtable_end;
154 	tagtable_t *t;
155 
156 	/* Boot parameters must start with a BP_TAG_FIRST tag. */
157 
158 	if (tag->id != BP_TAG_FIRST) {
159 		pr_warn("Invalid boot parameters!\n");
160 		return 0;
161 	}
162 
163 	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
164 
165 	/* Parse all tags. */
166 
167 	while (tag != NULL && tag->id != BP_TAG_LAST) {
168 		for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
169 			if (tag->id == t->tag) {
170 				t->parse(tag);
171 				break;
172 			}
173 		}
174 		if (t == &__tagtable_end)
175 			pr_warn("Ignoring tag 0x%08x\n", tag->id);
176 		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
177 	}
178 
179 	return 0;
180 }
181 
182 #ifdef CONFIG_OF
183 
184 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
185 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
186 EXPORT_SYMBOL(xtensa_kio_paddr);
187 
188 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
189 		int depth, void *data)
190 {
191 	const __be32 *ranges;
192 	int len;
193 
194 	if (depth > 1)
195 		return 0;
196 
197 	if (!of_flat_dt_is_compatible(node, "simple-bus"))
198 		return 0;
199 
200 	ranges = of_get_flat_dt_prop(node, "ranges", &len);
201 	if (!ranges)
202 		return 1;
203 	if (len == 0)
204 		return 1;
205 
206 	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
207 	/* round down to nearest 256MB boundary */
208 	xtensa_kio_paddr &= 0xf0000000;
209 
210 	return 1;
211 }
212 #else
213 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
214 		int depth, void *data)
215 {
216 	return 1;
217 }
218 #endif
219 
220 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
221 {
222 	size &= PAGE_MASK;
223 	memblock_add(base, size);
224 }
225 
226 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
227 {
228 	return __alloc_bootmem(size, align, 0);
229 }
230 
231 void __init early_init_devtree(void *params)
232 {
233 	early_init_dt_scan(params);
234 	of_scan_flat_dt(xtensa_dt_io_area, NULL);
235 
236 	if (!command_line[0])
237 		strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
238 }
239 
240 #endif /* CONFIG_OF */
241 
242 /*
243  * Initialize architecture. (Early stage)
244  */
245 
246 void __init init_arch(bp_tag_t *bp_start)
247 {
248 	/* Parse boot parameters */
249 
250 	if (bp_start)
251 		parse_bootparam(bp_start);
252 
253 #ifdef CONFIG_OF
254 	early_init_devtree(dtb_start);
255 #endif
256 
257 #ifdef CONFIG_CMDLINE_BOOL
258 	if (!command_line[0])
259 		strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
260 #endif
261 
262 	/* Early hook for platforms */
263 
264 	platform_init(bp_start);
265 
266 	/* Initialize MMU. */
267 
268 	init_mmu();
269 }
270 
271 /*
272  * Initialize system. Setup memory and reserve regions.
273  */
274 
275 extern char _end[];
276 extern char _stext[];
277 extern char _WindowVectors_text_start;
278 extern char _WindowVectors_text_end;
279 extern char _DebugInterruptVector_text_start;
280 extern char _DebugInterruptVector_text_end;
281 extern char _KernelExceptionVector_text_start;
282 extern char _KernelExceptionVector_text_end;
283 extern char _UserExceptionVector_text_start;
284 extern char _UserExceptionVector_text_end;
285 extern char _DoubleExceptionVector_text_start;
286 extern char _DoubleExceptionVector_text_end;
287 #if XCHAL_EXCM_LEVEL >= 2
288 extern char _Level2InterruptVector_text_start;
289 extern char _Level2InterruptVector_text_end;
290 #endif
291 #if XCHAL_EXCM_LEVEL >= 3
292 extern char _Level3InterruptVector_text_start;
293 extern char _Level3InterruptVector_text_end;
294 #endif
295 #if XCHAL_EXCM_LEVEL >= 4
296 extern char _Level4InterruptVector_text_start;
297 extern char _Level4InterruptVector_text_end;
298 #endif
299 #if XCHAL_EXCM_LEVEL >= 5
300 extern char _Level5InterruptVector_text_start;
301 extern char _Level5InterruptVector_text_end;
302 #endif
303 #if XCHAL_EXCM_LEVEL >= 6
304 extern char _Level6InterruptVector_text_start;
305 extern char _Level6InterruptVector_text_end;
306 #endif
307 #ifdef CONFIG_SMP
308 extern char _SecondaryResetVector_text_start;
309 extern char _SecondaryResetVector_text_end;
310 #endif
311 
312 static inline int mem_reserve(unsigned long start, unsigned long end)
313 {
314 	return memblock_reserve(start, end - start);
315 }
316 
317 void __init setup_arch(char **cmdline_p)
318 {
319 	pr_info("config ID: %08x:%08x\n",
320 		get_sr(SREG_EPC), get_sr(SREG_EXCSAVE));
321 	if (get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
322 	    get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
323 		pr_info("built for config ID: %08x:%08x\n",
324 			XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
325 
326 	*cmdline_p = command_line;
327 	platform_setup(cmdline_p);
328 	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
329 
330 	/* Reserve some memory regions */
331 
332 #ifdef CONFIG_BLK_DEV_INITRD
333 	if (initrd_start < initrd_end) {
334 		initrd_is_mapped = mem_reserve(__pa(initrd_start),
335 					       __pa(initrd_end)) == 0;
336 		initrd_below_start_ok = 1;
337 	} else {
338 		initrd_start = 0;
339 	}
340 #endif
341 
342 	mem_reserve(__pa(_stext), __pa(_end));
343 
344 #ifdef CONFIG_VECTORS_OFFSET
345 	mem_reserve(__pa(&_WindowVectors_text_start),
346 		    __pa(&_WindowVectors_text_end));
347 
348 	mem_reserve(__pa(&_DebugInterruptVector_text_start),
349 		    __pa(&_DebugInterruptVector_text_end));
350 
351 	mem_reserve(__pa(&_KernelExceptionVector_text_start),
352 		    __pa(&_KernelExceptionVector_text_end));
353 
354 	mem_reserve(__pa(&_UserExceptionVector_text_start),
355 		    __pa(&_UserExceptionVector_text_end));
356 
357 	mem_reserve(__pa(&_DoubleExceptionVector_text_start),
358 		    __pa(&_DoubleExceptionVector_text_end));
359 
360 #if XCHAL_EXCM_LEVEL >= 2
361 	mem_reserve(__pa(&_Level2InterruptVector_text_start),
362 		    __pa(&_Level2InterruptVector_text_end));
363 #endif
364 #if XCHAL_EXCM_LEVEL >= 3
365 	mem_reserve(__pa(&_Level3InterruptVector_text_start),
366 		    __pa(&_Level3InterruptVector_text_end));
367 #endif
368 #if XCHAL_EXCM_LEVEL >= 4
369 	mem_reserve(__pa(&_Level4InterruptVector_text_start),
370 		    __pa(&_Level4InterruptVector_text_end));
371 #endif
372 #if XCHAL_EXCM_LEVEL >= 5
373 	mem_reserve(__pa(&_Level5InterruptVector_text_start),
374 		    __pa(&_Level5InterruptVector_text_end));
375 #endif
376 #if XCHAL_EXCM_LEVEL >= 6
377 	mem_reserve(__pa(&_Level6InterruptVector_text_start),
378 		    __pa(&_Level6InterruptVector_text_end));
379 #endif
380 
381 #endif /* CONFIG_VECTORS_OFFSET */
382 
383 #ifdef CONFIG_SMP
384 	mem_reserve(__pa(&_SecondaryResetVector_text_start),
385 		    __pa(&_SecondaryResetVector_text_end));
386 #endif
387 	parse_early_param();
388 	bootmem_init();
389 
390 	unflatten_and_copy_device_tree();
391 
392 #ifdef CONFIG_SMP
393 	smp_init_cpus();
394 #endif
395 
396 	paging_init();
397 	zones_init();
398 
399 #ifdef CONFIG_VT
400 # if defined(CONFIG_VGA_CONSOLE)
401 	conswitchp = &vga_con;
402 # elif defined(CONFIG_DUMMY_CONSOLE)
403 	conswitchp = &dummy_con;
404 # endif
405 #endif
406 
407 #ifdef CONFIG_PCI
408 	platform_pcibios_init();
409 #endif
410 }
411 
412 static DEFINE_PER_CPU(struct cpu, cpu_data);
413 
414 static int __init topology_init(void)
415 {
416 	int i;
417 
418 	for_each_possible_cpu(i) {
419 		struct cpu *cpu = &per_cpu(cpu_data, i);
420 		cpu->hotpluggable = !!i;
421 		register_cpu(cpu, i);
422 	}
423 
424 	return 0;
425 }
426 subsys_initcall(topology_init);
427 
428 void cpu_reset(void)
429 {
430 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
431 	local_irq_disable();
432 	/*
433 	 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
434 	 * be flushed.
435 	 * Way 4 is not currently used by linux.
436 	 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
437 	 * Way 5 shall be flushed and way 6 shall be set to identity mapping
438 	 * on MMUv3.
439 	 */
440 	local_flush_tlb_all();
441 	invalidate_page_directory();
442 #if XCHAL_HAVE_SPANNING_WAY
443 	/* MMU v3 */
444 	{
445 		unsigned long vaddr = (unsigned long)cpu_reset;
446 		unsigned long paddr = __pa(vaddr);
447 		unsigned long tmpaddr = vaddr + SZ_512M;
448 		unsigned long tmp0, tmp1, tmp2, tmp3;
449 
450 		/*
451 		 * Find a place for the temporary mapping. It must not be
452 		 * in the same 512MB region with vaddr or paddr, otherwise
453 		 * there may be multihit exception either on entry to the
454 		 * temporary mapping, or on entry to the identity mapping.
455 		 * (512MB is the biggest page size supported by TLB.)
456 		 */
457 		while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
458 			tmpaddr += SZ_512M;
459 
460 		/* Invalidate mapping in the selected temporary area */
461 		if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
462 			invalidate_itlb_entry(itlb_probe(tmpaddr));
463 		if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
464 			invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
465 
466 		/*
467 		 * Map two consecutive pages starting at the physical address
468 		 * of this function to the temporary mapping area.
469 		 */
470 		write_itlb_entry(__pte((paddr & PAGE_MASK) |
471 				       _PAGE_HW_VALID |
472 				       _PAGE_HW_EXEC |
473 				       _PAGE_CA_BYPASS),
474 				 tmpaddr & PAGE_MASK);
475 		write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
476 				       _PAGE_HW_VALID |
477 				       _PAGE_HW_EXEC |
478 				       _PAGE_CA_BYPASS),
479 				 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
480 
481 		/* Reinitialize TLB */
482 		__asm__ __volatile__ ("movi	%0, 1f\n\t"
483 				      "movi	%3, 2f\n\t"
484 				      "add	%0, %0, %4\n\t"
485 				      "add	%3, %3, %5\n\t"
486 				      "jx	%0\n"
487 				      /*
488 				       * No literal, data or stack access
489 				       * below this point
490 				       */
491 				      "1:\n\t"
492 				      /* Initialize *tlbcfg */
493 				      "movi	%0, 0\n\t"
494 				      "wsr	%0, itlbcfg\n\t"
495 				      "wsr	%0, dtlbcfg\n\t"
496 				      /* Invalidate TLB way 5 */
497 				      "movi	%0, 4\n\t"
498 				      "movi	%1, 5\n"
499 				      "1:\n\t"
500 				      "iitlb	%1\n\t"
501 				      "idtlb	%1\n\t"
502 				      "add	%1, %1, %6\n\t"
503 				      "addi	%0, %0, -1\n\t"
504 				      "bnez	%0, 1b\n\t"
505 				      /* Initialize TLB way 6 */
506 				      "movi	%0, 7\n\t"
507 				      "addi	%1, %9, 3\n\t"
508 				      "addi	%2, %9, 6\n"
509 				      "1:\n\t"
510 				      "witlb	%1, %2\n\t"
511 				      "wdtlb	%1, %2\n\t"
512 				      "add	%1, %1, %7\n\t"
513 				      "add	%2, %2, %7\n\t"
514 				      "addi	%0, %0, -1\n\t"
515 				      "bnez	%0, 1b\n\t"
516 				      /* Jump to identity mapping */
517 				      "jx	%3\n"
518 				      "2:\n\t"
519 				      /* Complete way 6 initialization */
520 				      "witlb	%1, %2\n\t"
521 				      "wdtlb	%1, %2\n\t"
522 				      /* Invalidate temporary mapping */
523 				      "sub	%0, %9, %7\n\t"
524 				      "iitlb	%0\n\t"
525 				      "add	%0, %0, %8\n\t"
526 				      "iitlb	%0"
527 				      : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
528 					"=&a"(tmp3)
529 				      : "a"(tmpaddr - vaddr),
530 					"a"(paddr - vaddr),
531 					"a"(SZ_128M), "a"(SZ_512M),
532 					"a"(PAGE_SIZE),
533 					"a"((tmpaddr + SZ_512M) & PAGE_MASK)
534 				      : "memory");
535 	}
536 #endif
537 #endif
538 	__asm__ __volatile__ ("movi	a2, 0\n\t"
539 			      "wsr	a2, icountlevel\n\t"
540 			      "movi	a2, 0\n\t"
541 			      "wsr	a2, icount\n\t"
542 #if XCHAL_NUM_IBREAK > 0
543 			      "wsr	a2, ibreakenable\n\t"
544 #endif
545 #if XCHAL_HAVE_LOOPS
546 			      "wsr	a2, lcount\n\t"
547 #endif
548 			      "movi	a2, 0x1f\n\t"
549 			      "wsr	a2, ps\n\t"
550 			      "isync\n\t"
551 			      "jx	%0\n\t"
552 			      :
553 			      : "a" (XCHAL_RESET_VECTOR_VADDR)
554 			      : "a2");
555 	for (;;)
556 		;
557 }
558 
559 void machine_restart(char * cmd)
560 {
561 	platform_restart();
562 }
563 
564 void machine_halt(void)
565 {
566 	platform_halt();
567 	while (1);
568 }
569 
570 void machine_power_off(void)
571 {
572 	platform_power_off();
573 	while (1);
574 }
575 #ifdef CONFIG_PROC_FS
576 
577 /*
578  * Display some core information through /proc/cpuinfo.
579  */
580 
581 static int
582 c_show(struct seq_file *f, void *slot)
583 {
584 	/* high-level stuff */
585 	seq_printf(f, "CPU count\t: %u\n"
586 		      "CPU list\t: %*pbl\n"
587 		      "vendor_id\t: Tensilica\n"
588 		      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
589 		      "core ID\t\t: " XCHAL_CORE_ID "\n"
590 		      "build ID\t: 0x%x\n"
591 		      "config ID\t: %08x:%08x\n"
592 		      "byte order\t: %s\n"
593 		      "cpu MHz\t\t: %lu.%02lu\n"
594 		      "bogomips\t: %lu.%02lu\n",
595 		      num_online_cpus(),
596 		      cpumask_pr_args(cpu_online_mask),
597 		      XCHAL_BUILD_UNIQUE_ID,
598 		      get_sr(SREG_EPC), get_sr(SREG_EXCSAVE),
599 		      XCHAL_HAVE_BE ?  "big" : "little",
600 		      ccount_freq/1000000,
601 		      (ccount_freq/10000) % 100,
602 		      loops_per_jiffy/(500000/HZ),
603 		      (loops_per_jiffy/(5000/HZ)) % 100);
604 	seq_puts(f, "flags\t\t: "
605 #if XCHAL_HAVE_NMI
606 		     "nmi "
607 #endif
608 #if XCHAL_HAVE_DEBUG
609 		     "debug "
610 # if XCHAL_HAVE_OCD
611 		     "ocd "
612 # endif
613 #endif
614 #if XCHAL_HAVE_DENSITY
615 	    	     "density "
616 #endif
617 #if XCHAL_HAVE_BOOLEANS
618 		     "boolean "
619 #endif
620 #if XCHAL_HAVE_LOOPS
621 		     "loop "
622 #endif
623 #if XCHAL_HAVE_NSA
624 		     "nsa "
625 #endif
626 #if XCHAL_HAVE_MINMAX
627 		     "minmax "
628 #endif
629 #if XCHAL_HAVE_SEXT
630 		     "sext "
631 #endif
632 #if XCHAL_HAVE_CLAMPS
633 		     "clamps "
634 #endif
635 #if XCHAL_HAVE_MAC16
636 		     "mac16 "
637 #endif
638 #if XCHAL_HAVE_MUL16
639 		     "mul16 "
640 #endif
641 #if XCHAL_HAVE_MUL32
642 		     "mul32 "
643 #endif
644 #if XCHAL_HAVE_MUL32_HIGH
645 		     "mul32h "
646 #endif
647 #if XCHAL_HAVE_FP
648 		     "fpu "
649 #endif
650 #if XCHAL_HAVE_S32C1I
651 		     "s32c1i "
652 #endif
653 		     "\n");
654 
655 	/* Registers. */
656 	seq_printf(f,"physical aregs\t: %d\n"
657 		     "misc regs\t: %d\n"
658 		     "ibreak\t\t: %d\n"
659 		     "dbreak\t\t: %d\n",
660 		     XCHAL_NUM_AREGS,
661 		     XCHAL_NUM_MISC_REGS,
662 		     XCHAL_NUM_IBREAK,
663 		     XCHAL_NUM_DBREAK);
664 
665 
666 	/* Interrupt. */
667 	seq_printf(f,"num ints\t: %d\n"
668 		     "ext ints\t: %d\n"
669 		     "int levels\t: %d\n"
670 		     "timers\t\t: %d\n"
671 		     "debug level\t: %d\n",
672 		     XCHAL_NUM_INTERRUPTS,
673 		     XCHAL_NUM_EXTINTERRUPTS,
674 		     XCHAL_NUM_INTLEVELS,
675 		     XCHAL_NUM_TIMERS,
676 		     XCHAL_DEBUGLEVEL);
677 
678 	/* Cache */
679 	seq_printf(f,"icache line size: %d\n"
680 		     "icache ways\t: %d\n"
681 		     "icache size\t: %d\n"
682 		     "icache flags\t: "
683 #if XCHAL_ICACHE_LINE_LOCKABLE
684 		     "lock "
685 #endif
686 		     "\n"
687 		     "dcache line size: %d\n"
688 		     "dcache ways\t: %d\n"
689 		     "dcache size\t: %d\n"
690 		     "dcache flags\t: "
691 #if XCHAL_DCACHE_IS_WRITEBACK
692 		     "writeback "
693 #endif
694 #if XCHAL_DCACHE_LINE_LOCKABLE
695 		     "lock "
696 #endif
697 		     "\n",
698 		     XCHAL_ICACHE_LINESIZE,
699 		     XCHAL_ICACHE_WAYS,
700 		     XCHAL_ICACHE_SIZE,
701 		     XCHAL_DCACHE_LINESIZE,
702 		     XCHAL_DCACHE_WAYS,
703 		     XCHAL_DCACHE_SIZE);
704 
705 	return 0;
706 }
707 
708 /*
709  * We show only CPU #0 info.
710  */
711 static void *
712 c_start(struct seq_file *f, loff_t *pos)
713 {
714 	return (*pos == 0) ? (void *)1 : NULL;
715 }
716 
717 static void *
718 c_next(struct seq_file *f, void *v, loff_t *pos)
719 {
720 	return NULL;
721 }
722 
723 static void
724 c_stop(struct seq_file *f, void *v)
725 {
726 }
727 
728 const struct seq_operations cpuinfo_op =
729 {
730 	.start	= c_start,
731 	.next	= c_next,
732 	.stop	= c_stop,
733 	.show	= c_show,
734 };
735 
736 #endif /* CONFIG_PROC_FS */
737