1 /* 2 * arch/xtensa/kernel/setup.c 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1995 Linus Torvalds 9 * Copyright (C) 2001 - 2005 Tensilica Inc. 10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 11 * 12 * Chris Zankel <chris@zankel.net> 13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> 14 * Kevin Chea 15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca> 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/mm.h> 21 #include <linux/proc_fs.h> 22 #include <linux/screen_info.h> 23 #include <linux/kernel.h> 24 #include <linux/percpu.h> 25 #include <linux/reboot.h> 26 #include <linux/cpu.h> 27 #include <linux/of.h> 28 #include <linux/of_fdt.h> 29 30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 31 # include <linux/console.h> 32 #endif 33 34 #ifdef CONFIG_PROC_FS 35 # include <linux/seq_file.h> 36 #endif 37 38 #include <asm/bootparam.h> 39 #include <asm/kasan.h> 40 #include <asm/mmu_context.h> 41 #include <asm/page.h> 42 #include <asm/param.h> 43 #include <asm/platform.h> 44 #include <asm/processor.h> 45 #include <asm/sections.h> 46 #include <asm/setup.h> 47 #include <asm/smp.h> 48 #include <asm/sysmem.h> 49 #include <asm/timex.h> 50 #include <asm/traps.h> 51 52 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 53 struct screen_info screen_info = { 54 .orig_x = 0, 55 .orig_y = 24, 56 .orig_video_cols = 80, 57 .orig_video_lines = 24, 58 .orig_video_isVGA = 1, 59 .orig_video_points = 16, 60 }; 61 #endif 62 63 #ifdef CONFIG_BLK_DEV_INITRD 64 extern unsigned long initrd_start; 65 extern unsigned long initrd_end; 66 extern int initrd_below_start_ok; 67 #endif 68 69 #ifdef CONFIG_USE_OF 70 void *dtb_start = __dtb_start; 71 #endif 72 73 extern unsigned long loops_per_jiffy; 74 75 /* Command line specified as configuration option. */ 76 77 static char __initdata command_line[COMMAND_LINE_SIZE]; 78 79 #ifdef CONFIG_CMDLINE_BOOL 80 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; 81 #endif 82 83 #ifdef CONFIG_PARSE_BOOTPARAM 84 /* 85 * Boot parameter parsing. 86 * 87 * The Xtensa port uses a list of variable-sized tags to pass data to 88 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list 89 * to be recognised. The list is terminated with a zero-sized 90 * BP_TAG_LAST tag. 91 */ 92 93 typedef struct tagtable { 94 u32 tag; 95 int (*parse)(const bp_tag_t*); 96 } tagtable_t; 97 98 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \ 99 __section(".taglist") __attribute__((used)) = { tag, fn } 100 101 /* parse current tag */ 102 103 static int __init parse_tag_mem(const bp_tag_t *tag) 104 { 105 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data); 106 107 if (mi->type != MEMORY_TYPE_CONVENTIONAL) 108 return -1; 109 110 return memblock_add(mi->start, mi->end - mi->start); 111 } 112 113 __tagtable(BP_TAG_MEMORY, parse_tag_mem); 114 115 #ifdef CONFIG_BLK_DEV_INITRD 116 117 static int __init parse_tag_initrd(const bp_tag_t* tag) 118 { 119 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data); 120 121 initrd_start = (unsigned long)__va(mi->start); 122 initrd_end = (unsigned long)__va(mi->end); 123 124 return 0; 125 } 126 127 __tagtable(BP_TAG_INITRD, parse_tag_initrd); 128 129 #endif /* CONFIG_BLK_DEV_INITRD */ 130 131 #ifdef CONFIG_USE_OF 132 133 static int __init parse_tag_fdt(const bp_tag_t *tag) 134 { 135 dtb_start = __va(tag->data[0]); 136 return 0; 137 } 138 139 __tagtable(BP_TAG_FDT, parse_tag_fdt); 140 141 #endif /* CONFIG_USE_OF */ 142 143 static int __init parse_tag_cmdline(const bp_tag_t* tag) 144 { 145 strscpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE); 146 return 0; 147 } 148 149 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline); 150 151 static int __init parse_bootparam(const bp_tag_t* tag) 152 { 153 extern tagtable_t __tagtable_begin, __tagtable_end; 154 tagtable_t *t; 155 156 /* Boot parameters must start with a BP_TAG_FIRST tag. */ 157 158 if (tag->id != BP_TAG_FIRST) { 159 pr_warn("Invalid boot parameters!\n"); 160 return 0; 161 } 162 163 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size); 164 165 /* Parse all tags. */ 166 167 while (tag != NULL && tag->id != BP_TAG_LAST) { 168 for (t = &__tagtable_begin; t < &__tagtable_end; t++) { 169 if (tag->id == t->tag) { 170 t->parse(tag); 171 break; 172 } 173 } 174 if (t == &__tagtable_end) 175 pr_warn("Ignoring tag 0x%08x\n", tag->id); 176 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size); 177 } 178 179 return 0; 180 } 181 #else 182 static int __init parse_bootparam(const bp_tag_t *tag) 183 { 184 pr_info("Ignoring boot parameters at %p\n", tag); 185 return 0; 186 } 187 #endif 188 189 #ifdef CONFIG_USE_OF 190 191 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY 192 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR; 193 EXPORT_SYMBOL(xtensa_kio_paddr); 194 195 static int __init xtensa_dt_io_area(unsigned long node, const char *uname, 196 int depth, void *data) 197 { 198 const __be32 *ranges; 199 int len; 200 201 if (depth > 1) 202 return 0; 203 204 if (!of_flat_dt_is_compatible(node, "simple-bus")) 205 return 0; 206 207 ranges = of_get_flat_dt_prop(node, "ranges", &len); 208 if (!ranges) 209 return 1; 210 if (len == 0) 211 return 1; 212 213 xtensa_kio_paddr = of_read_ulong(ranges+1, 1); 214 /* round down to nearest 256MB boundary */ 215 xtensa_kio_paddr &= 0xf0000000; 216 217 init_kio(); 218 219 return 1; 220 } 221 #else 222 static int __init xtensa_dt_io_area(unsigned long node, const char *uname, 223 int depth, void *data) 224 { 225 return 1; 226 } 227 #endif 228 229 void __init early_init_devtree(void *params) 230 { 231 early_init_dt_scan(params); 232 of_scan_flat_dt(xtensa_dt_io_area, NULL); 233 234 if (!command_line[0]) 235 strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE); 236 } 237 238 #endif /* CONFIG_USE_OF */ 239 240 /* 241 * Initialize architecture. (Early stage) 242 */ 243 244 void __init init_arch(bp_tag_t *bp_start) 245 { 246 /* Initialize basic exception handling if configuration may need it */ 247 248 if (IS_ENABLED(CONFIG_KASAN) || 249 IS_ENABLED(CONFIG_XTENSA_LOAD_STORE)) 250 early_trap_init(); 251 252 /* Initialize MMU. */ 253 254 init_mmu(); 255 256 /* Initialize initial KASAN shadow map */ 257 258 kasan_early_init(); 259 260 /* Parse boot parameters */ 261 262 if (bp_start) 263 parse_bootparam(bp_start); 264 265 #ifdef CONFIG_USE_OF 266 early_init_devtree(dtb_start); 267 #endif 268 269 #ifdef CONFIG_CMDLINE_BOOL 270 if (!command_line[0]) 271 strscpy(command_line, default_command_line, COMMAND_LINE_SIZE); 272 #endif 273 274 /* Early hook for platforms */ 275 276 platform_init(bp_start); 277 } 278 279 /* 280 * Initialize system. Setup memory and reserve regions. 281 */ 282 283 static inline int __init_memblock mem_reserve(unsigned long start, 284 unsigned long end) 285 { 286 return memblock_reserve(start, end - start); 287 } 288 289 void __init setup_arch(char **cmdline_p) 290 { 291 pr_info("config ID: %08x:%08x\n", 292 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE)); 293 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 || 294 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1) 295 pr_info("built for config ID: %08x:%08x\n", 296 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1); 297 298 *cmdline_p = command_line; 299 platform_setup(cmdline_p); 300 strscpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 301 302 /* Reserve some memory regions */ 303 304 #ifdef CONFIG_BLK_DEV_INITRD 305 if (initrd_start < initrd_end && 306 !mem_reserve(__pa(initrd_start), __pa(initrd_end))) 307 initrd_below_start_ok = 1; 308 else 309 initrd_start = 0; 310 #endif 311 312 mem_reserve(__pa(_stext), __pa(_end)); 313 #ifdef CONFIG_XIP_KERNEL 314 mem_reserve(__pa(_xip_start), __pa(_xip_end)); 315 #endif 316 317 #ifdef CONFIG_VECTORS_ADDR 318 #ifdef SUPPORT_WINDOWED 319 mem_reserve(__pa(_WindowVectors_text_start), 320 __pa(_WindowVectors_text_end)); 321 #endif 322 323 mem_reserve(__pa(_DebugInterruptVector_text_start), 324 __pa(_DebugInterruptVector_text_end)); 325 326 mem_reserve(__pa(_KernelExceptionVector_text_start), 327 __pa(_KernelExceptionVector_text_end)); 328 329 mem_reserve(__pa(_UserExceptionVector_text_start), 330 __pa(_UserExceptionVector_text_end)); 331 332 mem_reserve(__pa(_DoubleExceptionVector_text_start), 333 __pa(_DoubleExceptionVector_text_end)); 334 335 mem_reserve(__pa(_exception_text_start), 336 __pa(_exception_text_end)); 337 #if XCHAL_EXCM_LEVEL >= 2 338 mem_reserve(__pa(_Level2InterruptVector_text_start), 339 __pa(_Level2InterruptVector_text_end)); 340 #endif 341 #if XCHAL_EXCM_LEVEL >= 3 342 mem_reserve(__pa(_Level3InterruptVector_text_start), 343 __pa(_Level3InterruptVector_text_end)); 344 #endif 345 #if XCHAL_EXCM_LEVEL >= 4 346 mem_reserve(__pa(_Level4InterruptVector_text_start), 347 __pa(_Level4InterruptVector_text_end)); 348 #endif 349 #if XCHAL_EXCM_LEVEL >= 5 350 mem_reserve(__pa(_Level5InterruptVector_text_start), 351 __pa(_Level5InterruptVector_text_end)); 352 #endif 353 #if XCHAL_EXCM_LEVEL >= 6 354 mem_reserve(__pa(_Level6InterruptVector_text_start), 355 __pa(_Level6InterruptVector_text_end)); 356 #endif 357 358 #endif /* CONFIG_VECTORS_ADDR */ 359 360 #ifdef CONFIG_SECONDARY_RESET_VECTOR 361 mem_reserve(__pa(_SecondaryResetVector_text_start), 362 __pa(_SecondaryResetVector_text_end)); 363 #endif 364 parse_early_param(); 365 bootmem_init(); 366 kasan_init(); 367 unflatten_and_copy_device_tree(); 368 369 #ifdef CONFIG_SMP 370 smp_init_cpus(); 371 #endif 372 373 paging_init(); 374 zones_init(); 375 376 #ifdef CONFIG_VT 377 # if defined(CONFIG_VGA_CONSOLE) 378 conswitchp = &vga_con; 379 # endif 380 #endif 381 } 382 383 static DEFINE_PER_CPU(struct cpu, cpu_data); 384 385 static int __init topology_init(void) 386 { 387 int i; 388 389 for_each_possible_cpu(i) { 390 struct cpu *cpu = &per_cpu(cpu_data, i); 391 cpu->hotpluggable = !!i; 392 register_cpu(cpu, i); 393 } 394 395 return 0; 396 } 397 subsys_initcall(topology_init); 398 399 void cpu_reset(void) 400 { 401 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU) 402 local_irq_disable(); 403 /* 404 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must 405 * be flushed. 406 * Way 4 is not currently used by linux. 407 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired. 408 * Way 5 shall be flushed and way 6 shall be set to identity mapping 409 * on MMUv3. 410 */ 411 local_flush_tlb_all(); 412 invalidate_page_directory(); 413 #if XCHAL_HAVE_SPANNING_WAY 414 /* MMU v3 */ 415 { 416 unsigned long vaddr = (unsigned long)cpu_reset; 417 unsigned long paddr = __pa(vaddr); 418 unsigned long tmpaddr = vaddr + SZ_512M; 419 unsigned long tmp0, tmp1, tmp2, tmp3; 420 421 /* 422 * Find a place for the temporary mapping. It must not be 423 * in the same 512MB region with vaddr or paddr, otherwise 424 * there may be multihit exception either on entry to the 425 * temporary mapping, or on entry to the identity mapping. 426 * (512MB is the biggest page size supported by TLB.) 427 */ 428 while (((tmpaddr ^ paddr) & -SZ_512M) == 0) 429 tmpaddr += SZ_512M; 430 431 /* Invalidate mapping in the selected temporary area */ 432 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT)) 433 invalidate_itlb_entry(itlb_probe(tmpaddr)); 434 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT)) 435 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE)); 436 437 /* 438 * Map two consecutive pages starting at the physical address 439 * of this function to the temporary mapping area. 440 */ 441 write_itlb_entry(__pte((paddr & PAGE_MASK) | 442 _PAGE_HW_VALID | 443 _PAGE_HW_EXEC | 444 _PAGE_CA_BYPASS), 445 tmpaddr & PAGE_MASK); 446 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) | 447 _PAGE_HW_VALID | 448 _PAGE_HW_EXEC | 449 _PAGE_CA_BYPASS), 450 (tmpaddr & PAGE_MASK) + PAGE_SIZE); 451 452 /* Reinitialize TLB */ 453 __asm__ __volatile__ ("movi %0, 1f\n\t" 454 "movi %3, 2f\n\t" 455 "add %0, %0, %4\n\t" 456 "add %3, %3, %5\n\t" 457 "jx %0\n" 458 /* 459 * No literal, data or stack access 460 * below this point 461 */ 462 "1:\n\t" 463 /* Initialize *tlbcfg */ 464 "movi %0, 0\n\t" 465 "wsr %0, itlbcfg\n\t" 466 "wsr %0, dtlbcfg\n\t" 467 /* Invalidate TLB way 5 */ 468 "movi %0, 4\n\t" 469 "movi %1, 5\n" 470 "1:\n\t" 471 "iitlb %1\n\t" 472 "idtlb %1\n\t" 473 "add %1, %1, %6\n\t" 474 "addi %0, %0, -1\n\t" 475 "bnez %0, 1b\n\t" 476 /* Initialize TLB way 6 */ 477 "movi %0, 7\n\t" 478 "addi %1, %9, 3\n\t" 479 "addi %2, %9, 6\n" 480 "1:\n\t" 481 "witlb %1, %2\n\t" 482 "wdtlb %1, %2\n\t" 483 "add %1, %1, %7\n\t" 484 "add %2, %2, %7\n\t" 485 "addi %0, %0, -1\n\t" 486 "bnez %0, 1b\n\t" 487 "isync\n\t" 488 /* Jump to identity mapping */ 489 "jx %3\n" 490 "2:\n\t" 491 /* Complete way 6 initialization */ 492 "witlb %1, %2\n\t" 493 "wdtlb %1, %2\n\t" 494 /* Invalidate temporary mapping */ 495 "sub %0, %9, %7\n\t" 496 "iitlb %0\n\t" 497 "add %0, %0, %8\n\t" 498 "iitlb %0" 499 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2), 500 "=&a"(tmp3) 501 : "a"(tmpaddr - vaddr), 502 "a"(paddr - vaddr), 503 "a"(SZ_128M), "a"(SZ_512M), 504 "a"(PAGE_SIZE), 505 "a"((tmpaddr + SZ_512M) & PAGE_MASK) 506 : "memory"); 507 } 508 #endif 509 #endif 510 __asm__ __volatile__ ("movi a2, 0\n\t" 511 "wsr a2, icountlevel\n\t" 512 "movi a2, 0\n\t" 513 "wsr a2, icount\n\t" 514 #if XCHAL_NUM_IBREAK > 0 515 "wsr a2, ibreakenable\n\t" 516 #endif 517 #if XCHAL_HAVE_LOOPS 518 "wsr a2, lcount\n\t" 519 #endif 520 "movi a2, 0x1f\n\t" 521 "wsr a2, ps\n\t" 522 "isync\n\t" 523 "jx %0\n\t" 524 : 525 : "a" (XCHAL_RESET_VECTOR_VADDR) 526 : "a2"); 527 for (;;) 528 ; 529 } 530 531 void machine_restart(char * cmd) 532 { 533 local_irq_disable(); 534 smp_send_stop(); 535 do_kernel_restart(cmd); 536 pr_err("Reboot failed -- System halted\n"); 537 while (1) 538 cpu_relax(); 539 } 540 541 void machine_halt(void) 542 { 543 local_irq_disable(); 544 smp_send_stop(); 545 do_kernel_power_off(); 546 while (1) 547 cpu_relax(); 548 } 549 550 void machine_power_off(void) 551 { 552 local_irq_disable(); 553 smp_send_stop(); 554 do_kernel_power_off(); 555 while (1) 556 cpu_relax(); 557 } 558 #ifdef CONFIG_PROC_FS 559 560 /* 561 * Display some core information through /proc/cpuinfo. 562 */ 563 564 static int 565 c_show(struct seq_file *f, void *slot) 566 { 567 /* high-level stuff */ 568 seq_printf(f, "CPU count\t: %u\n" 569 "CPU list\t: %*pbl\n" 570 "vendor_id\t: Tensilica\n" 571 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n" 572 "core ID\t\t: " XCHAL_CORE_ID "\n" 573 "build ID\t: 0x%x\n" 574 "config ID\t: %08x:%08x\n" 575 "byte order\t: %s\n" 576 "cpu MHz\t\t: %lu.%02lu\n" 577 "bogomips\t: %lu.%02lu\n", 578 num_online_cpus(), 579 cpumask_pr_args(cpu_online_mask), 580 XCHAL_BUILD_UNIQUE_ID, 581 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE), 582 XCHAL_HAVE_BE ? "big" : "little", 583 ccount_freq/1000000, 584 (ccount_freq/10000) % 100, 585 loops_per_jiffy/(500000/HZ), 586 (loops_per_jiffy/(5000/HZ)) % 100); 587 seq_puts(f, "flags\t\t: " 588 #if XCHAL_HAVE_NMI 589 "nmi " 590 #endif 591 #if XCHAL_HAVE_DEBUG 592 "debug " 593 # if XCHAL_HAVE_OCD 594 "ocd " 595 # endif 596 #if XCHAL_HAVE_TRAX 597 "trax " 598 #endif 599 #if XCHAL_NUM_PERF_COUNTERS 600 "perf " 601 #endif 602 #endif 603 #if XCHAL_HAVE_DENSITY 604 "density " 605 #endif 606 #if XCHAL_HAVE_BOOLEANS 607 "boolean " 608 #endif 609 #if XCHAL_HAVE_LOOPS 610 "loop " 611 #endif 612 #if XCHAL_HAVE_NSA 613 "nsa " 614 #endif 615 #if XCHAL_HAVE_MINMAX 616 "minmax " 617 #endif 618 #if XCHAL_HAVE_SEXT 619 "sext " 620 #endif 621 #if XCHAL_HAVE_CLAMPS 622 "clamps " 623 #endif 624 #if XCHAL_HAVE_MAC16 625 "mac16 " 626 #endif 627 #if XCHAL_HAVE_MUL16 628 "mul16 " 629 #endif 630 #if XCHAL_HAVE_MUL32 631 "mul32 " 632 #endif 633 #if XCHAL_HAVE_MUL32_HIGH 634 "mul32h " 635 #endif 636 #if XCHAL_HAVE_FP 637 "fpu " 638 #endif 639 #if XCHAL_HAVE_S32C1I 640 "s32c1i " 641 #endif 642 #if XCHAL_HAVE_EXCLUSIVE 643 "exclusive " 644 #endif 645 "\n"); 646 647 /* Registers. */ 648 seq_printf(f,"physical aregs\t: %d\n" 649 "misc regs\t: %d\n" 650 "ibreak\t\t: %d\n" 651 "dbreak\t\t: %d\n" 652 "perf counters\t: %d\n", 653 XCHAL_NUM_AREGS, 654 XCHAL_NUM_MISC_REGS, 655 XCHAL_NUM_IBREAK, 656 XCHAL_NUM_DBREAK, 657 XCHAL_NUM_PERF_COUNTERS); 658 659 660 /* Interrupt. */ 661 seq_printf(f,"num ints\t: %d\n" 662 "ext ints\t: %d\n" 663 "int levels\t: %d\n" 664 "timers\t\t: %d\n" 665 "debug level\t: %d\n", 666 XCHAL_NUM_INTERRUPTS, 667 XCHAL_NUM_EXTINTERRUPTS, 668 XCHAL_NUM_INTLEVELS, 669 XCHAL_NUM_TIMERS, 670 XCHAL_DEBUGLEVEL); 671 672 /* Cache */ 673 seq_printf(f,"icache line size: %d\n" 674 "icache ways\t: %d\n" 675 "icache size\t: %d\n" 676 "icache flags\t: " 677 #if XCHAL_ICACHE_LINE_LOCKABLE 678 "lock " 679 #endif 680 "\n" 681 "dcache line size: %d\n" 682 "dcache ways\t: %d\n" 683 "dcache size\t: %d\n" 684 "dcache flags\t: " 685 #if XCHAL_DCACHE_IS_WRITEBACK 686 "writeback " 687 #endif 688 #if XCHAL_DCACHE_LINE_LOCKABLE 689 "lock " 690 #endif 691 "\n", 692 XCHAL_ICACHE_LINESIZE, 693 XCHAL_ICACHE_WAYS, 694 XCHAL_ICACHE_SIZE, 695 XCHAL_DCACHE_LINESIZE, 696 XCHAL_DCACHE_WAYS, 697 XCHAL_DCACHE_SIZE); 698 699 return 0; 700 } 701 702 /* 703 * We show only CPU #0 info. 704 */ 705 static void * 706 c_start(struct seq_file *f, loff_t *pos) 707 { 708 return (*pos == 0) ? (void *)1 : NULL; 709 } 710 711 static void * 712 c_next(struct seq_file *f, void *v, loff_t *pos) 713 { 714 ++*pos; 715 return c_start(f, pos); 716 } 717 718 static void 719 c_stop(struct seq_file *f, void *v) 720 { 721 } 722 723 const struct seq_operations cpuinfo_op = 724 { 725 .start = c_start, 726 .next = c_next, 727 .stop = c_stop, 728 .show = c_show, 729 }; 730 731 #endif /* CONFIG_PROC_FS */ 732