1 /* 2 * arch/xtensa/setup.c 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1995 Linus Torvalds 9 * Copyright (C) 2001 - 2005 Tensilica Inc. 10 * 11 * Chris Zankel <chris@zankel.net> 12 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> 13 * Kevin Chea 14 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca> 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/init.h> 19 #include <linux/proc_fs.h> 20 #include <linux/screen_info.h> 21 #include <linux/bootmem.h> 22 #include <linux/kernel.h> 23 24 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 25 # include <linux/console.h> 26 #endif 27 28 #ifdef CONFIG_RTC 29 # include <linux/timex.h> 30 #endif 31 32 #ifdef CONFIG_PROC_FS 33 # include <linux/seq_file.h> 34 #endif 35 36 #include <asm/system.h> 37 #include <asm/bootparam.h> 38 #include <asm/pgtable.h> 39 #include <asm/processor.h> 40 #include <asm/timex.h> 41 #include <asm/platform.h> 42 #include <asm/page.h> 43 #include <asm/setup.h> 44 45 #include <xtensa/config/system.h> 46 47 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 48 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; 49 #endif 50 51 #ifdef CONFIG_BLK_DEV_FD 52 extern struct fd_ops no_fd_ops; 53 struct fd_ops *fd_ops; 54 #endif 55 56 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) 57 extern struct ide_ops no_ide_ops; 58 struct ide_ops *ide_ops; 59 #endif 60 61 extern struct rtc_ops no_rtc_ops; 62 struct rtc_ops *rtc_ops; 63 64 #ifdef CONFIG_PC_KEYB 65 extern struct kbd_ops no_kbd_ops; 66 struct kbd_ops *kbd_ops; 67 #endif 68 69 #ifdef CONFIG_BLK_DEV_INITRD 70 extern void *initrd_start; 71 extern void *initrd_end; 72 extern void *__initrd_start; 73 extern void *__initrd_end; 74 int initrd_is_mapped = 0; 75 extern int initrd_below_start_ok; 76 #endif 77 78 unsigned char aux_device_present; 79 extern unsigned long loops_per_jiffy; 80 81 /* Command line specified as configuration option. */ 82 83 static char command_line[COMMAND_LINE_SIZE]; 84 85 #ifdef CONFIG_CMDLINE_BOOL 86 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; 87 #endif 88 89 sysmem_info_t __initdata sysmem; 90 91 #ifdef CONFIG_BLK_DEV_INITRD 92 int initrd_is_mapped; 93 #endif 94 95 extern void init_mmu(void); 96 97 /* 98 * Boot parameter parsing. 99 * 100 * The Xtensa port uses a list of variable-sized tags to pass data to 101 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list 102 * to be recognised. The list is terminated with a zero-sized 103 * BP_TAG_LAST tag. 104 */ 105 106 typedef struct tagtable { 107 u32 tag; 108 int (*parse)(const bp_tag_t*); 109 } tagtable_t; 110 111 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \ 112 __attribute__((unused, __section__(".taglist"))) = { tag, fn } 113 114 /* parse current tag */ 115 116 static int __init parse_tag_mem(const bp_tag_t *tag) 117 { 118 meminfo_t *mi = (meminfo_t*)(tag->data); 119 120 if (mi->type != MEMORY_TYPE_CONVENTIONAL) 121 return -1; 122 123 if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) { 124 printk(KERN_WARNING 125 "Ignoring memory bank 0x%08lx size %ldKB\n", 126 (unsigned long)mi->start, 127 (unsigned long)mi->end - (unsigned long)mi->start); 128 return -EINVAL; 129 } 130 sysmem.bank[sysmem.nr_banks].type = mi->type; 131 sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(mi->start); 132 sysmem.bank[sysmem.nr_banks].end = mi->end & PAGE_SIZE; 133 sysmem.nr_banks++; 134 135 return 0; 136 } 137 138 __tagtable(BP_TAG_MEMORY, parse_tag_mem); 139 140 #ifdef CONFIG_BLK_DEV_INITRD 141 142 static int __init parse_tag_initrd(const bp_tag_t* tag) 143 { 144 meminfo_t* mi; 145 mi = (meminfo_t*)(tag->data); 146 initrd_start = (void*)(mi->start); 147 initrd_end = (void*)(mi->end); 148 149 return 0; 150 } 151 152 __tagtable(BP_TAG_INITRD, parse_tag_initrd); 153 154 #endif /* CONFIG_BLK_DEV_INITRD */ 155 156 static int __init parse_tag_cmdline(const bp_tag_t* tag) 157 { 158 strncpy(command_line, (char*)(tag->data), COMMAND_LINE_SIZE); 159 command_line[COMMAND_LINE_SIZE - 1] = '\0'; 160 return 0; 161 } 162 163 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline); 164 165 static int __init parse_bootparam(const bp_tag_t* tag) 166 { 167 extern tagtable_t __tagtable_begin, __tagtable_end; 168 tagtable_t *t; 169 170 /* Boot parameters must start with a BP_TAG_FIRST tag. */ 171 172 if (tag->id != BP_TAG_FIRST) { 173 printk(KERN_WARNING "Invalid boot parameters!\n"); 174 return 0; 175 } 176 177 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size); 178 179 /* Parse all tags. */ 180 181 while (tag != NULL && tag->id != BP_TAG_LAST) { 182 for (t = &__tagtable_begin; t < &__tagtable_end; t++) { 183 if (tag->id == t->tag) { 184 t->parse(tag); 185 break; 186 } 187 } 188 if (t == &__tagtable_end) 189 printk(KERN_WARNING "Ignoring tag " 190 "0x%08x\n", tag->id); 191 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size); 192 } 193 194 return 0; 195 } 196 197 /* 198 * Initialize architecture. (Early stage) 199 */ 200 201 void __init init_arch(bp_tag_t *bp_start) 202 { 203 204 #ifdef CONFIG_BLK_DEV_INITRD 205 initrd_start = &__initrd_start; 206 initrd_end = &__initrd_end; 207 #endif 208 209 sysmem.nr_banks = 0; 210 211 #ifdef CONFIG_CMDLINE_BOOL 212 strcpy(command_line, default_command_line); 213 #endif 214 215 /* Parse boot parameters */ 216 217 if (bp_start) 218 parse_bootparam(bp_start); 219 220 if (sysmem.nr_banks == 0) { 221 sysmem.nr_banks = 1; 222 sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START; 223 sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START 224 + PLATFORM_DEFAULT_MEM_SIZE; 225 } 226 227 /* Early hook for platforms */ 228 229 platform_init(bp_start); 230 231 /* Initialize MMU. */ 232 233 init_mmu(); 234 } 235 236 /* 237 * Initialize system. Setup memory and reserve regions. 238 */ 239 240 extern char _end; 241 extern char _stext; 242 extern char _WindowVectors_text_start; 243 extern char _WindowVectors_text_end; 244 extern char _DebugInterruptVector_literal_start; 245 extern char _DebugInterruptVector_text_end; 246 extern char _KernelExceptionVector_literal_start; 247 extern char _KernelExceptionVector_text_end; 248 extern char _UserExceptionVector_literal_start; 249 extern char _UserExceptionVector_text_end; 250 extern char _DoubleExceptionVector_literal_start; 251 extern char _DoubleExceptionVector_text_end; 252 253 void __init setup_arch(char **cmdline_p) 254 { 255 extern int mem_reserve(unsigned long, unsigned long, int); 256 extern void bootmem_init(void); 257 258 memcpy(saved_command_line, command_line, COMMAND_LINE_SIZE); 259 saved_command_line[COMMAND_LINE_SIZE-1] = '\0'; 260 *cmdline_p = command_line; 261 262 /* Reserve some memory regions */ 263 264 #ifdef CONFIG_BLK_DEV_INITRD 265 if (initrd_start < initrd_end) { 266 initrd_is_mapped = mem_reserve(__pa(initrd_start), 267 __pa(initrd_end), 0); 268 initrd_below_start_ok = 1; 269 } else { 270 initrd_start = 0; 271 } 272 #endif 273 274 mem_reserve(__pa(&_stext),__pa(&_end), 1); 275 276 mem_reserve(__pa(&_WindowVectors_text_start), 277 __pa(&_WindowVectors_text_end), 0); 278 279 mem_reserve(__pa(&_DebugInterruptVector_literal_start), 280 __pa(&_DebugInterruptVector_text_end), 0); 281 282 mem_reserve(__pa(&_KernelExceptionVector_literal_start), 283 __pa(&_KernelExceptionVector_text_end), 0); 284 285 mem_reserve(__pa(&_UserExceptionVector_literal_start), 286 __pa(&_UserExceptionVector_text_end), 0); 287 288 mem_reserve(__pa(&_DoubleExceptionVector_literal_start), 289 __pa(&_DoubleExceptionVector_text_end), 0); 290 291 bootmem_init(); 292 293 platform_setup(cmdline_p); 294 295 296 paging_init(); 297 298 #ifdef CONFIG_VT 299 # if defined(CONFIG_VGA_CONSOLE) 300 conswitchp = &vga_con; 301 # elif defined(CONFIG_DUMMY_CONSOLE) 302 conswitchp = &dummy_con; 303 # endif 304 #endif 305 306 #ifdef CONFIG_PCI 307 platform_pcibios_init(); 308 #endif 309 } 310 311 void machine_restart(char * cmd) 312 { 313 platform_restart(); 314 } 315 316 void machine_halt(void) 317 { 318 platform_halt(); 319 while (1); 320 } 321 322 void machine_power_off(void) 323 { 324 platform_power_off(); 325 while (1); 326 } 327 #ifdef CONFIG_PROC_FS 328 329 /* 330 * Display some core information through /proc/cpuinfo. 331 */ 332 333 static int 334 c_show(struct seq_file *f, void *slot) 335 { 336 /* high-level stuff */ 337 seq_printf(f,"processor\t: 0\n" 338 "vendor_id\t: Tensilica\n" 339 "model\t\t: Xtensa " XCHAL_HW_RELEASE_NAME "\n" 340 "core ID\t\t: " XCHAL_CORE_ID "\n" 341 "build ID\t: 0x%x\n" 342 "byte order\t: %s\n" 343 "cpu MHz\t\t: %lu.%02lu\n" 344 "bogomips\t: %lu.%02lu\n", 345 XCHAL_BUILD_UNIQUE_ID, 346 XCHAL_HAVE_BE ? "big" : "little", 347 CCOUNT_PER_JIFFY/(1000000/HZ), 348 (CCOUNT_PER_JIFFY/(10000/HZ)) % 100, 349 loops_per_jiffy/(500000/HZ), 350 (loops_per_jiffy/(5000/HZ)) % 100); 351 352 seq_printf(f,"flags\t\t: " 353 #if XCHAL_HAVE_NMI 354 "nmi " 355 #endif 356 #if XCHAL_HAVE_DEBUG 357 "debug " 358 # if XCHAL_HAVE_OCD 359 "ocd " 360 # endif 361 #endif 362 #if XCHAL_HAVE_DENSITY 363 "density " 364 #endif 365 #if XCHAL_HAVE_BOOLEANS 366 "boolean " 367 #endif 368 #if XCHAL_HAVE_LOOPS 369 "loop " 370 #endif 371 #if XCHAL_HAVE_NSA 372 "nsa " 373 #endif 374 #if XCHAL_HAVE_MINMAX 375 "minmax " 376 #endif 377 #if XCHAL_HAVE_SEXT 378 "sext " 379 #endif 380 #if XCHAL_HAVE_CLAMPS 381 "clamps " 382 #endif 383 #if XCHAL_HAVE_MAC16 384 "mac16 " 385 #endif 386 #if XCHAL_HAVE_MUL16 387 "mul16 " 388 #endif 389 #if XCHAL_HAVE_MUL32 390 "mul32 " 391 #endif 392 #if XCHAL_HAVE_MUL32_HIGH 393 "mul32h " 394 #endif 395 #if XCHAL_HAVE_FP 396 "fpu " 397 #endif 398 "\n"); 399 400 /* Registers. */ 401 seq_printf(f,"physical aregs\t: %d\n" 402 "misc regs\t: %d\n" 403 "ibreak\t\t: %d\n" 404 "dbreak\t\t: %d\n", 405 XCHAL_NUM_AREGS, 406 XCHAL_NUM_MISC_REGS, 407 XCHAL_NUM_IBREAK, 408 XCHAL_NUM_DBREAK); 409 410 411 /* Interrupt. */ 412 seq_printf(f,"num ints\t: %d\n" 413 "ext ints\t: %d\n" 414 "int levels\t: %d\n" 415 "timers\t\t: %d\n" 416 "debug level\t: %d\n", 417 XCHAL_NUM_INTERRUPTS, 418 XCHAL_NUM_EXTINTERRUPTS, 419 XCHAL_NUM_INTLEVELS, 420 XCHAL_NUM_TIMERS, 421 XCHAL_DEBUGLEVEL); 422 423 /* Coprocessors */ 424 #if XCHAL_HAVE_CP 425 seq_printf(f, "coprocessors\t: %d\n", XCHAL_CP_NUM); 426 #else 427 seq_printf(f, "coprocessors\t: none\n"); 428 #endif 429 430 /* {I,D}{RAM,ROM} and XLMI */ 431 seq_printf(f,"inst ROMs\t: %d\n" 432 "inst RAMs\t: %d\n" 433 "data ROMs\t: %d\n" 434 "data RAMs\t: %d\n" 435 "XLMI ports\t: %d\n", 436 XCHAL_NUM_IROM, 437 XCHAL_NUM_IRAM, 438 XCHAL_NUM_DROM, 439 XCHAL_NUM_DRAM, 440 XCHAL_NUM_XLMI); 441 442 /* Cache */ 443 seq_printf(f,"icache line size: %d\n" 444 "icache ways\t: %d\n" 445 "icache size\t: %d\n" 446 "icache flags\t: " 447 #if XCHAL_ICACHE_LINE_LOCKABLE 448 "lock" 449 #endif 450 "\n" 451 "dcache line size: %d\n" 452 "dcache ways\t: %d\n" 453 "dcache size\t: %d\n" 454 "dcache flags\t: " 455 #if XCHAL_DCACHE_IS_WRITEBACK 456 "writeback" 457 #endif 458 #if XCHAL_DCACHE_LINE_LOCKABLE 459 "lock" 460 #endif 461 "\n", 462 XCHAL_ICACHE_LINESIZE, 463 XCHAL_ICACHE_WAYS, 464 XCHAL_ICACHE_SIZE, 465 XCHAL_DCACHE_LINESIZE, 466 XCHAL_DCACHE_WAYS, 467 XCHAL_DCACHE_SIZE); 468 469 /* MMU */ 470 seq_printf(f,"ASID bits\t: %d\n" 471 "ASID invalid\t: %d\n" 472 "ASID kernel\t: %d\n" 473 "rings\t\t: %d\n" 474 "itlb ways\t: %d\n" 475 "itlb AR ways\t: %d\n" 476 "dtlb ways\t: %d\n" 477 "dtlb AR ways\t: %d\n", 478 XCHAL_MMU_ASID_BITS, 479 XCHAL_MMU_ASID_INVALID, 480 XCHAL_MMU_ASID_KERNEL, 481 XCHAL_MMU_RINGS, 482 XCHAL_ITLB_WAYS, 483 XCHAL_ITLB_ARF_WAYS, 484 XCHAL_DTLB_WAYS, 485 XCHAL_DTLB_ARF_WAYS); 486 487 return 0; 488 } 489 490 /* 491 * We show only CPU #0 info. 492 */ 493 static void * 494 c_start(struct seq_file *f, loff_t *pos) 495 { 496 return (void *) ((*pos == 0) ? (void *)1 : NULL); 497 } 498 499 static void * 500 c_next(struct seq_file *f, void *v, loff_t *pos) 501 { 502 return NULL; 503 } 504 505 static void 506 c_stop(struct seq_file *f, void *v) 507 { 508 } 509 510 struct seq_operations cpuinfo_op = 511 { 512 start: c_start, 513 next: c_next, 514 stop: c_stop, 515 show: c_show 516 }; 517 518 #endif /* CONFIG_PROC_FS */ 519 520