xref: /linux/arch/xtensa/kernel/setup.c (revision 148f9bb87745ed45f7a11b2cbd3bc0f017d5d257) 
1 /*
2  * arch/xtensa/kernel/setup.c
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1995  Linus Torvalds
9  * Copyright (C) 2001 - 2005  Tensilica Inc.
10  *
11  * Chris Zankel	<chris@zankel.net>
12  * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
13  * Kevin Chea
14  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
15  */
16 
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/mm.h>
20 #include <linux/proc_fs.h>
21 #include <linux/screen_info.h>
22 #include <linux/bootmem.h>
23 #include <linux/kernel.h>
24 
25 #ifdef CONFIG_OF
26 #include <linux/of_fdt.h>
27 #include <linux/of_platform.h>
28 #endif
29 
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
32 #endif
33 
34 #ifdef CONFIG_RTC
35 # include <linux/timex.h>
36 #endif
37 
38 #ifdef CONFIG_PROC_FS
39 # include <linux/seq_file.h>
40 #endif
41 
42 #include <asm/bootparam.h>
43 #include <asm/pgtable.h>
44 #include <asm/processor.h>
45 #include <asm/timex.h>
46 #include <asm/platform.h>
47 #include <asm/page.h>
48 #include <asm/setup.h>
49 #include <asm/param.h>
50 #include <asm/traps.h>
51 
52 #include <platform/hardware.h>
53 
54 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
55 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
56 #endif
57 
58 #ifdef CONFIG_BLK_DEV_FD
59 extern struct fd_ops no_fd_ops;
60 struct fd_ops *fd_ops;
61 #endif
62 
63 extern struct rtc_ops no_rtc_ops;
64 struct rtc_ops *rtc_ops;
65 
66 #ifdef CONFIG_BLK_DEV_INITRD
67 extern void *initrd_start;
68 extern void *initrd_end;
69 int initrd_is_mapped = 0;
70 extern int initrd_below_start_ok;
71 #endif
72 
73 #ifdef CONFIG_OF
74 extern u32 __dtb_start[];
75 void *dtb_start = __dtb_start;
76 #endif
77 
78 unsigned char aux_device_present;
79 extern unsigned long loops_per_jiffy;
80 
81 /* Command line specified as configuration option. */
82 
83 static char __initdata command_line[COMMAND_LINE_SIZE];
84 
85 #ifdef CONFIG_CMDLINE_BOOL
86 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
87 #endif
88 
89 sysmem_info_t __initdata sysmem;
90 
91 #ifdef CONFIG_MMU
92 extern void init_mmu(void);
93 #else
94 static inline void init_mmu(void) { }
95 #endif
96 
97 extern int mem_reserve(unsigned long, unsigned long, int);
98 extern void bootmem_init(void);
99 extern void zones_init(void);
100 
101 /*
102  * Boot parameter parsing.
103  *
104  * The Xtensa port uses a list of variable-sized tags to pass data to
105  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
106  * to be recognised. The list is terminated with a zero-sized
107  * BP_TAG_LAST tag.
108  */
109 
110 typedef struct tagtable {
111 	u32 tag;
112 	int (*parse)(const bp_tag_t*);
113 } tagtable_t;
114 
115 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
116 	__attribute__((used, section(".taglist"))) = { tag, fn }
117 
118 /* parse current tag */
119 
120 static int __init add_sysmem_bank(unsigned long type, unsigned long start,
121 		unsigned long end)
122 {
123 	if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) {
124 		printk(KERN_WARNING
125 				"Ignoring memory bank 0x%08lx size %ldKB\n",
126 				start, end - start);
127 		return -EINVAL;
128 	}
129 	sysmem.bank[sysmem.nr_banks].type  = type;
130 	sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(start);
131 	sysmem.bank[sysmem.nr_banks].end   = end & PAGE_MASK;
132 	sysmem.nr_banks++;
133 
134 	return 0;
135 }
136 
137 static int __init parse_tag_mem(const bp_tag_t *tag)
138 {
139 	meminfo_t *mi = (meminfo_t *)(tag->data);
140 
141 	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
142 		return -1;
143 
144 	return add_sysmem_bank(mi->type, mi->start, mi->end);
145 }
146 
147 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
148 
149 #ifdef CONFIG_BLK_DEV_INITRD
150 
151 static int __init parse_tag_initrd(const bp_tag_t* tag)
152 {
153 	meminfo_t* mi;
154 	mi = (meminfo_t*)(tag->data);
155 	initrd_start = __va(mi->start);
156 	initrd_end = __va(mi->end);
157 
158 	return 0;
159 }
160 
161 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
162 
163 #ifdef CONFIG_OF
164 
165 static int __init parse_tag_fdt(const bp_tag_t *tag)
166 {
167 	dtb_start = __va(tag->data[0]);
168 	return 0;
169 }
170 
171 __tagtable(BP_TAG_FDT, parse_tag_fdt);
172 
173 void __init early_init_dt_setup_initrd_arch(unsigned long start,
174 		unsigned long end)
175 {
176 	initrd_start = (void *)__va(start);
177 	initrd_end = (void *)__va(end);
178 	initrd_below_start_ok = 1;
179 }
180 
181 #endif /* CONFIG_OF */
182 
183 #endif /* CONFIG_BLK_DEV_INITRD */
184 
185 static int __init parse_tag_cmdline(const bp_tag_t* tag)
186 {
187 	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
188 	return 0;
189 }
190 
191 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
192 
193 static int __init parse_bootparam(const bp_tag_t* tag)
194 {
195 	extern tagtable_t __tagtable_begin, __tagtable_end;
196 	tagtable_t *t;
197 
198 	/* Boot parameters must start with a BP_TAG_FIRST tag. */
199 
200 	if (tag->id != BP_TAG_FIRST) {
201 		printk(KERN_WARNING "Invalid boot parameters!\n");
202 		return 0;
203 	}
204 
205 	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
206 
207 	/* Parse all tags. */
208 
209 	while (tag != NULL && tag->id != BP_TAG_LAST) {
210 	 	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
211 			if (tag->id == t->tag) {
212 				t->parse(tag);
213 				break;
214 			}
215 		}
216 		if (t == &__tagtable_end)
217 			printk(KERN_WARNING "Ignoring tag "
218 			       "0x%08x\n", tag->id);
219 		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
220 	}
221 
222 	return 0;
223 }
224 
225 #ifdef CONFIG_OF
226 
227 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
228 {
229 	size &= PAGE_MASK;
230 	add_sysmem_bank(MEMORY_TYPE_CONVENTIONAL, base, base + size);
231 }
232 
233 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
234 {
235 	return __alloc_bootmem(size, align, 0);
236 }
237 
238 void __init early_init_devtree(void *params)
239 {
240 	/* Setup flat device-tree pointer */
241 	initial_boot_params = params;
242 
243 	/* Retrieve various informations from the /chosen node of the
244 	 * device-tree, including the platform type, initrd location and
245 	 * size, TCE reserve, and more ...
246 	 */
247 	if (!command_line[0])
248 		of_scan_flat_dt(early_init_dt_scan_chosen, command_line);
249 
250 	/* Scan memory nodes and rebuild MEMBLOCKs */
251 	of_scan_flat_dt(early_init_dt_scan_root, NULL);
252 	if (sysmem.nr_banks == 0)
253 		of_scan_flat_dt(early_init_dt_scan_memory, NULL);
254 }
255 
256 static void __init copy_devtree(void)
257 {
258 	void *alloc = early_init_dt_alloc_memory_arch(
259 			be32_to_cpu(initial_boot_params->totalsize), 8);
260 	if (alloc) {
261 		memcpy(alloc, initial_boot_params,
262 				be32_to_cpu(initial_boot_params->totalsize));
263 		initial_boot_params = alloc;
264 	}
265 }
266 
267 static int __init xtensa_device_probe(void)
268 {
269 	of_platform_populate(NULL, NULL, NULL, NULL);
270 	return 0;
271 }
272 
273 device_initcall(xtensa_device_probe);
274 
275 #endif /* CONFIG_OF */
276 
277 /*
278  * Initialize architecture. (Early stage)
279  */
280 
281 void __init init_arch(bp_tag_t *bp_start)
282 {
283 	sysmem.nr_banks = 0;
284 
285 	/* Parse boot parameters */
286 
287 	if (bp_start)
288 		parse_bootparam(bp_start);
289 
290 #ifdef CONFIG_OF
291 	early_init_devtree(dtb_start);
292 #endif
293 
294 	if (sysmem.nr_banks == 0) {
295 		sysmem.nr_banks = 1;
296 		sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START;
297 		sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START
298 				     + PLATFORM_DEFAULT_MEM_SIZE;
299 	}
300 
301 #ifdef CONFIG_CMDLINE_BOOL
302 	if (!command_line[0])
303 		strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
304 #endif
305 
306 	/* Early hook for platforms */
307 
308 	platform_init(bp_start);
309 
310 	/* Initialize MMU. */
311 
312 	init_mmu();
313 }
314 
315 /*
316  * Initialize system. Setup memory and reserve regions.
317  */
318 
319 extern char _end;
320 extern char _stext;
321 extern char _WindowVectors_text_start;
322 extern char _WindowVectors_text_end;
323 extern char _DebugInterruptVector_literal_start;
324 extern char _DebugInterruptVector_text_end;
325 extern char _KernelExceptionVector_literal_start;
326 extern char _KernelExceptionVector_text_end;
327 extern char _UserExceptionVector_literal_start;
328 extern char _UserExceptionVector_text_end;
329 extern char _DoubleExceptionVector_literal_start;
330 extern char _DoubleExceptionVector_text_end;
331 #if XCHAL_EXCM_LEVEL >= 2
332 extern char _Level2InterruptVector_text_start;
333 extern char _Level2InterruptVector_text_end;
334 #endif
335 #if XCHAL_EXCM_LEVEL >= 3
336 extern char _Level3InterruptVector_text_start;
337 extern char _Level3InterruptVector_text_end;
338 #endif
339 #if XCHAL_EXCM_LEVEL >= 4
340 extern char _Level4InterruptVector_text_start;
341 extern char _Level4InterruptVector_text_end;
342 #endif
343 #if XCHAL_EXCM_LEVEL >= 5
344 extern char _Level5InterruptVector_text_start;
345 extern char _Level5InterruptVector_text_end;
346 #endif
347 #if XCHAL_EXCM_LEVEL >= 6
348 extern char _Level6InterruptVector_text_start;
349 extern char _Level6InterruptVector_text_end;
350 #endif
351 
352 
353 
354 #ifdef CONFIG_S32C1I_SELFTEST
355 #if XCHAL_HAVE_S32C1I
356 
357 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
358 
359 /*
360  * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
361  *
362  * If *v == cmp, set *v = set.  Return previous *v.
363  */
364 static inline int probed_compare_swap(int *v, int cmp, int set)
365 {
366 	int tmp;
367 
368 	__asm__ __volatile__(
369 			"	movi	%1, 1f\n"
370 			"	s32i	%1, %4, 0\n"
371 			"	wsr	%2, scompare1\n"
372 			"1:	s32c1i	%0, %3, 0\n"
373 			: "=a" (set), "=&a" (tmp)
374 			: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
375 			: "memory"
376 			);
377 	return set;
378 }
379 
380 /* Handle probed exception */
381 
382 void __init do_probed_exception(struct pt_regs *regs, unsigned long exccause)
383 {
384 	if (regs->pc == rcw_probe_pc) {	/* exception on s32c1i ? */
385 		regs->pc += 3;		/* skip the s32c1i instruction */
386 		rcw_exc = exccause;
387 	} else {
388 		do_unhandled(regs, exccause);
389 	}
390 }
391 
392 /* Simple test of S32C1I (soc bringup assist) */
393 
394 void __init check_s32c1i(void)
395 {
396 	int n, cause1, cause2;
397 	void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
398 
399 	rcw_probe_pc = 0;
400 	handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
401 			do_probed_exception);
402 	handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
403 			do_probed_exception);
404 	handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
405 			do_probed_exception);
406 
407 	/* First try an S32C1I that does not store: */
408 	rcw_exc = 0;
409 	rcw_word = 1;
410 	n = probed_compare_swap(&rcw_word, 0, 2);
411 	cause1 = rcw_exc;
412 
413 	/* took exception? */
414 	if (cause1 != 0) {
415 		/* unclean exception? */
416 		if (n != 2 || rcw_word != 1)
417 			panic("S32C1I exception error");
418 	} else if (rcw_word != 1 || n != 1) {
419 		panic("S32C1I compare error");
420 	}
421 
422 	/* Then an S32C1I that stores: */
423 	rcw_exc = 0;
424 	rcw_word = 0x1234567;
425 	n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
426 	cause2 = rcw_exc;
427 
428 	if (cause2 != 0) {
429 		/* unclean exception? */
430 		if (n != 0xabcde || rcw_word != 0x1234567)
431 			panic("S32C1I exception error (b)");
432 	} else if (rcw_word != 0xabcde || n != 0x1234567) {
433 		panic("S32C1I store error");
434 	}
435 
436 	/* Verify consistency of exceptions: */
437 	if (cause1 || cause2) {
438 		pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
439 		/* If emulation of S32C1I upon bus error gets implemented,
440 		   we can get rid of this panic for single core (not SMP) */
441 		panic("S32C1I exceptions not currently supported");
442 	}
443 	if (cause1 != cause2)
444 		panic("inconsistent S32C1I exceptions");
445 
446 	trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
447 	trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
448 	trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
449 }
450 
451 #else /* XCHAL_HAVE_S32C1I */
452 
453 /* This condition should not occur with a commercially deployed processor.
454    Display reminder for early engr test or demo chips / FPGA bitstreams */
455 void __init check_s32c1i(void)
456 {
457 	pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
458 }
459 
460 #endif /* XCHAL_HAVE_S32C1I */
461 #else /* CONFIG_S32C1I_SELFTEST */
462 
463 void __init check_s32c1i(void)
464 {
465 }
466 
467 #endif /* CONFIG_S32C1I_SELFTEST */
468 
469 
470 void __init setup_arch(char **cmdline_p)
471 {
472 	strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
473 	*cmdline_p = command_line;
474 
475 	check_s32c1i();
476 
477 	/* Reserve some memory regions */
478 
479 #ifdef CONFIG_BLK_DEV_INITRD
480 	if (initrd_start < initrd_end) {
481 		initrd_is_mapped = mem_reserve(__pa(initrd_start),
482 					       __pa(initrd_end), 0);
483 		initrd_below_start_ok = 1;
484 	} else {
485 		initrd_start = 0;
486 	}
487 #endif
488 
489 	mem_reserve(__pa(&_stext),__pa(&_end), 1);
490 
491 	mem_reserve(__pa(&_WindowVectors_text_start),
492 		    __pa(&_WindowVectors_text_end), 0);
493 
494 	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
495 		    __pa(&_DebugInterruptVector_text_end), 0);
496 
497 	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
498 		    __pa(&_KernelExceptionVector_text_end), 0);
499 
500 	mem_reserve(__pa(&_UserExceptionVector_literal_start),
501 		    __pa(&_UserExceptionVector_text_end), 0);
502 
503 	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
504 		    __pa(&_DoubleExceptionVector_text_end), 0);
505 
506 #if XCHAL_EXCM_LEVEL >= 2
507 	mem_reserve(__pa(&_Level2InterruptVector_text_start),
508 		    __pa(&_Level2InterruptVector_text_end), 0);
509 #endif
510 #if XCHAL_EXCM_LEVEL >= 3
511 	mem_reserve(__pa(&_Level3InterruptVector_text_start),
512 		    __pa(&_Level3InterruptVector_text_end), 0);
513 #endif
514 #if XCHAL_EXCM_LEVEL >= 4
515 	mem_reserve(__pa(&_Level4InterruptVector_text_start),
516 		    __pa(&_Level4InterruptVector_text_end), 0);
517 #endif
518 #if XCHAL_EXCM_LEVEL >= 5
519 	mem_reserve(__pa(&_Level5InterruptVector_text_start),
520 		    __pa(&_Level5InterruptVector_text_end), 0);
521 #endif
522 #if XCHAL_EXCM_LEVEL >= 6
523 	mem_reserve(__pa(&_Level6InterruptVector_text_start),
524 		    __pa(&_Level6InterruptVector_text_end), 0);
525 #endif
526 
527 	bootmem_init();
528 
529 #ifdef CONFIG_OF
530 	copy_devtree();
531 	unflatten_device_tree();
532 #endif
533 
534 	platform_setup(cmdline_p);
535 
536 	paging_init();
537 	zones_init();
538 
539 #ifdef CONFIG_VT
540 # if defined(CONFIG_VGA_CONSOLE)
541 	conswitchp = &vga_con;
542 # elif defined(CONFIG_DUMMY_CONSOLE)
543 	conswitchp = &dummy_con;
544 # endif
545 #endif
546 
547 #ifdef CONFIG_PCI
548 	platform_pcibios_init();
549 #endif
550 }
551 
552 void machine_restart(char * cmd)
553 {
554 	platform_restart();
555 }
556 
557 void machine_halt(void)
558 {
559 	platform_halt();
560 	while (1);
561 }
562 
563 void machine_power_off(void)
564 {
565 	platform_power_off();
566 	while (1);
567 }
568 #ifdef CONFIG_PROC_FS
569 
570 /*
571  * Display some core information through /proc/cpuinfo.
572  */
573 
574 static int
575 c_show(struct seq_file *f, void *slot)
576 {
577 	/* high-level stuff */
578 	seq_printf(f,"processor\t: 0\n"
579 		     "vendor_id\t: Tensilica\n"
580 		     "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
581 		     "core ID\t\t: " XCHAL_CORE_ID "\n"
582 		     "build ID\t: 0x%x\n"
583 		     "byte order\t: %s\n"
584 		     "cpu MHz\t\t: %lu.%02lu\n"
585 		     "bogomips\t: %lu.%02lu\n",
586 		     XCHAL_BUILD_UNIQUE_ID,
587 		     XCHAL_HAVE_BE ?  "big" : "little",
588 		     CCOUNT_PER_JIFFY/(1000000/HZ),
589 		     (CCOUNT_PER_JIFFY/(10000/HZ)) % 100,
590 		     loops_per_jiffy/(500000/HZ),
591 		     (loops_per_jiffy/(5000/HZ)) % 100);
592 
593 	seq_printf(f,"flags\t\t: "
594 #if XCHAL_HAVE_NMI
595 		     "nmi "
596 #endif
597 #if XCHAL_HAVE_DEBUG
598 		     "debug "
599 # if XCHAL_HAVE_OCD
600 		     "ocd "
601 # endif
602 #endif
603 #if XCHAL_HAVE_DENSITY
604 	    	     "density "
605 #endif
606 #if XCHAL_HAVE_BOOLEANS
607 		     "boolean "
608 #endif
609 #if XCHAL_HAVE_LOOPS
610 		     "loop "
611 #endif
612 #if XCHAL_HAVE_NSA
613 		     "nsa "
614 #endif
615 #if XCHAL_HAVE_MINMAX
616 		     "minmax "
617 #endif
618 #if XCHAL_HAVE_SEXT
619 		     "sext "
620 #endif
621 #if XCHAL_HAVE_CLAMPS
622 		     "clamps "
623 #endif
624 #if XCHAL_HAVE_MAC16
625 		     "mac16 "
626 #endif
627 #if XCHAL_HAVE_MUL16
628 		     "mul16 "
629 #endif
630 #if XCHAL_HAVE_MUL32
631 		     "mul32 "
632 #endif
633 #if XCHAL_HAVE_MUL32_HIGH
634 		     "mul32h "
635 #endif
636 #if XCHAL_HAVE_FP
637 		     "fpu "
638 #endif
639 #if XCHAL_HAVE_S32C1I
640 		     "s32c1i "
641 #endif
642 		     "\n");
643 
644 	/* Registers. */
645 	seq_printf(f,"physical aregs\t: %d\n"
646 		     "misc regs\t: %d\n"
647 		     "ibreak\t\t: %d\n"
648 		     "dbreak\t\t: %d\n",
649 		     XCHAL_NUM_AREGS,
650 		     XCHAL_NUM_MISC_REGS,
651 		     XCHAL_NUM_IBREAK,
652 		     XCHAL_NUM_DBREAK);
653 
654 
655 	/* Interrupt. */
656 	seq_printf(f,"num ints\t: %d\n"
657 		     "ext ints\t: %d\n"
658 		     "int levels\t: %d\n"
659 		     "timers\t\t: %d\n"
660 		     "debug level\t: %d\n",
661 		     XCHAL_NUM_INTERRUPTS,
662 		     XCHAL_NUM_EXTINTERRUPTS,
663 		     XCHAL_NUM_INTLEVELS,
664 		     XCHAL_NUM_TIMERS,
665 		     XCHAL_DEBUGLEVEL);
666 
667 	/* Cache */
668 	seq_printf(f,"icache line size: %d\n"
669 		     "icache ways\t: %d\n"
670 		     "icache size\t: %d\n"
671 		     "icache flags\t: "
672 #if XCHAL_ICACHE_LINE_LOCKABLE
673 		     "lock "
674 #endif
675 		     "\n"
676 		     "dcache line size: %d\n"
677 		     "dcache ways\t: %d\n"
678 		     "dcache size\t: %d\n"
679 		     "dcache flags\t: "
680 #if XCHAL_DCACHE_IS_WRITEBACK
681 		     "writeback "
682 #endif
683 #if XCHAL_DCACHE_LINE_LOCKABLE
684 		     "lock "
685 #endif
686 		     "\n",
687 		     XCHAL_ICACHE_LINESIZE,
688 		     XCHAL_ICACHE_WAYS,
689 		     XCHAL_ICACHE_SIZE,
690 		     XCHAL_DCACHE_LINESIZE,
691 		     XCHAL_DCACHE_WAYS,
692 		     XCHAL_DCACHE_SIZE);
693 
694 	return 0;
695 }
696 
697 /*
698  * We show only CPU #0 info.
699  */
700 static void *
701 c_start(struct seq_file *f, loff_t *pos)
702 {
703 	return (void *) ((*pos == 0) ? (void *)1 : NULL);
704 }
705 
706 static void *
707 c_next(struct seq_file *f, void *v, loff_t *pos)
708 {
709 	return NULL;
710 }
711 
712 static void
713 c_stop(struct seq_file *f, void *v)
714 {
715 }
716 
717 const struct seq_operations cpuinfo_op =
718 {
719 	start:  c_start,
720 	next:   c_next,
721 	stop:   c_stop,
722 	show:   c_show
723 };
724 
725 #endif /* CONFIG_PROC_FS */
726