xref: /linux/arch/xtensa/kernel/setup.c (revision 00a6d7b6762c27d441e9ac8faff36384bc0fc180) 
1 /*
2  * arch/xtensa/kernel/setup.c
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1995  Linus Torvalds
9  * Copyright (C) 2001 - 2005  Tensilica Inc.
10  *
11  * Chris Zankel	<chris@zankel.net>
12  * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
13  * Kevin Chea
14  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
15  */
16 
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/mm.h>
20 #include <linux/proc_fs.h>
21 #include <linux/screen_info.h>
22 #include <linux/bootmem.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/clk-provider.h>
26 #include <linux/cpu.h>
27 #include <linux/of_fdt.h>
28 #include <linux/of_platform.h>
29 
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
32 #endif
33 
34 #ifdef CONFIG_RTC
35 # include <linux/timex.h>
36 #endif
37 
38 #ifdef CONFIG_PROC_FS
39 # include <linux/seq_file.h>
40 #endif
41 
42 #include <asm/bootparam.h>
43 #include <asm/mmu_context.h>
44 #include <asm/pgtable.h>
45 #include <asm/processor.h>
46 #include <asm/timex.h>
47 #include <asm/platform.h>
48 #include <asm/page.h>
49 #include <asm/setup.h>
50 #include <asm/param.h>
51 #include <asm/traps.h>
52 #include <asm/smp.h>
53 #include <asm/sysmem.h>
54 
55 #include <platform/hardware.h>
56 
57 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
58 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
59 #endif
60 
61 #ifdef CONFIG_BLK_DEV_FD
62 extern struct fd_ops no_fd_ops;
63 struct fd_ops *fd_ops;
64 #endif
65 
66 extern struct rtc_ops no_rtc_ops;
67 struct rtc_ops *rtc_ops;
68 
69 #ifdef CONFIG_BLK_DEV_INITRD
70 extern unsigned long initrd_start;
71 extern unsigned long initrd_end;
72 int initrd_is_mapped = 0;
73 extern int initrd_below_start_ok;
74 #endif
75 
76 #ifdef CONFIG_OF
77 extern u32 __dtb_start[];
78 void *dtb_start = __dtb_start;
79 #endif
80 
81 unsigned char aux_device_present;
82 extern unsigned long loops_per_jiffy;
83 
84 /* Command line specified as configuration option. */
85 
86 static char __initdata command_line[COMMAND_LINE_SIZE];
87 
88 #ifdef CONFIG_CMDLINE_BOOL
89 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
90 #endif
91 
92 /*
93  * Boot parameter parsing.
94  *
95  * The Xtensa port uses a list of variable-sized tags to pass data to
96  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
97  * to be recognised. The list is terminated with a zero-sized
98  * BP_TAG_LAST tag.
99  */
100 
101 typedef struct tagtable {
102 	u32 tag;
103 	int (*parse)(const bp_tag_t*);
104 } tagtable_t;
105 
106 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
107 	__attribute__((used, section(".taglist"))) = { tag, fn }
108 
109 /* parse current tag */
110 
111 static int __init parse_tag_mem(const bp_tag_t *tag)
112 {
113 	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
114 
115 	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
116 		return -1;
117 
118 	return add_sysmem_bank(mi->start, mi->end);
119 }
120 
121 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
122 
123 #ifdef CONFIG_BLK_DEV_INITRD
124 
125 static int __init parse_tag_initrd(const bp_tag_t* tag)
126 {
127 	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
128 
129 	initrd_start = (unsigned long)__va(mi->start);
130 	initrd_end = (unsigned long)__va(mi->end);
131 
132 	return 0;
133 }
134 
135 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
136 
137 #ifdef CONFIG_OF
138 
139 static int __init parse_tag_fdt(const bp_tag_t *tag)
140 {
141 	dtb_start = __va(tag->data[0]);
142 	return 0;
143 }
144 
145 __tagtable(BP_TAG_FDT, parse_tag_fdt);
146 
147 #endif /* CONFIG_OF */
148 
149 #endif /* CONFIG_BLK_DEV_INITRD */
150 
151 static int __init parse_tag_cmdline(const bp_tag_t* tag)
152 {
153 	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
154 	return 0;
155 }
156 
157 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
158 
159 static int __init parse_bootparam(const bp_tag_t* tag)
160 {
161 	extern tagtable_t __tagtable_begin, __tagtable_end;
162 	tagtable_t *t;
163 
164 	/* Boot parameters must start with a BP_TAG_FIRST tag. */
165 
166 	if (tag->id != BP_TAG_FIRST) {
167 		printk(KERN_WARNING "Invalid boot parameters!\n");
168 		return 0;
169 	}
170 
171 	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
172 
173 	/* Parse all tags. */
174 
175 	while (tag != NULL && tag->id != BP_TAG_LAST) {
176 	 	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
177 			if (tag->id == t->tag) {
178 				t->parse(tag);
179 				break;
180 			}
181 		}
182 		if (t == &__tagtable_end)
183 			printk(KERN_WARNING "Ignoring tag "
184 			       "0x%08x\n", tag->id);
185 		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
186 	}
187 
188 	return 0;
189 }
190 
191 #ifdef CONFIG_OF
192 bool __initdata dt_memory_scan = false;
193 
194 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
195 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
196 EXPORT_SYMBOL(xtensa_kio_paddr);
197 
198 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
199 		int depth, void *data)
200 {
201 	const __be32 *ranges;
202 	unsigned long len;
203 
204 	if (depth > 1)
205 		return 0;
206 
207 	if (!of_flat_dt_is_compatible(node, "simple-bus"))
208 		return 0;
209 
210 	ranges = of_get_flat_dt_prop(node, "ranges", &len);
211 	if (!ranges)
212 		return 1;
213 	if (len == 0)
214 		return 1;
215 
216 	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
217 	/* round down to nearest 256MB boundary */
218 	xtensa_kio_paddr &= 0xf0000000;
219 
220 	return 1;
221 }
222 #else
223 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
224 		int depth, void *data)
225 {
226 	return 1;
227 }
228 #endif
229 
230 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
231 {
232 	if (!dt_memory_scan)
233 		return;
234 
235 	size &= PAGE_MASK;
236 	add_sysmem_bank(base, base + size);
237 }
238 
239 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
240 {
241 	return __alloc_bootmem(size, align, 0);
242 }
243 
244 void __init early_init_devtree(void *params)
245 {
246 	if (sysmem.nr_banks == 0)
247 		dt_memory_scan = true;
248 
249 	early_init_dt_scan(params);
250 	of_scan_flat_dt(xtensa_dt_io_area, NULL);
251 
252 	if (!command_line[0])
253 		strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
254 }
255 
256 static int __init xtensa_device_probe(void)
257 {
258 	of_clk_init(NULL);
259 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
260 	return 0;
261 }
262 
263 device_initcall(xtensa_device_probe);
264 
265 #endif /* CONFIG_OF */
266 
267 /*
268  * Initialize architecture. (Early stage)
269  */
270 
271 void __init init_arch(bp_tag_t *bp_start)
272 {
273 	/* Parse boot parameters */
274 
275 	if (bp_start)
276 		parse_bootparam(bp_start);
277 
278 #ifdef CONFIG_OF
279 	early_init_devtree(dtb_start);
280 #endif
281 
282 	if (sysmem.nr_banks == 0) {
283 		add_sysmem_bank(PLATFORM_DEFAULT_MEM_START,
284 				PLATFORM_DEFAULT_MEM_START +
285 				PLATFORM_DEFAULT_MEM_SIZE);
286 	}
287 
288 #ifdef CONFIG_CMDLINE_BOOL
289 	if (!command_line[0])
290 		strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
291 #endif
292 
293 	/* Early hook for platforms */
294 
295 	platform_init(bp_start);
296 
297 	/* Initialize MMU. */
298 
299 	init_mmu();
300 }
301 
302 /*
303  * Initialize system. Setup memory and reserve regions.
304  */
305 
306 extern char _end;
307 extern char _stext;
308 extern char _WindowVectors_text_start;
309 extern char _WindowVectors_text_end;
310 extern char _DebugInterruptVector_literal_start;
311 extern char _DebugInterruptVector_text_end;
312 extern char _KernelExceptionVector_literal_start;
313 extern char _KernelExceptionVector_text_end;
314 extern char _UserExceptionVector_literal_start;
315 extern char _UserExceptionVector_text_end;
316 extern char _DoubleExceptionVector_literal_start;
317 extern char _DoubleExceptionVector_text_end;
318 #if XCHAL_EXCM_LEVEL >= 2
319 extern char _Level2InterruptVector_text_start;
320 extern char _Level2InterruptVector_text_end;
321 #endif
322 #if XCHAL_EXCM_LEVEL >= 3
323 extern char _Level3InterruptVector_text_start;
324 extern char _Level3InterruptVector_text_end;
325 #endif
326 #if XCHAL_EXCM_LEVEL >= 4
327 extern char _Level4InterruptVector_text_start;
328 extern char _Level4InterruptVector_text_end;
329 #endif
330 #if XCHAL_EXCM_LEVEL >= 5
331 extern char _Level5InterruptVector_text_start;
332 extern char _Level5InterruptVector_text_end;
333 #endif
334 #if XCHAL_EXCM_LEVEL >= 6
335 extern char _Level6InterruptVector_text_start;
336 extern char _Level6InterruptVector_text_end;
337 #endif
338 
339 
340 
341 #ifdef CONFIG_S32C1I_SELFTEST
342 #if XCHAL_HAVE_S32C1I
343 
344 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
345 
346 /*
347  * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
348  *
349  * If *v == cmp, set *v = set.  Return previous *v.
350  */
351 static inline int probed_compare_swap(int *v, int cmp, int set)
352 {
353 	int tmp;
354 
355 	__asm__ __volatile__(
356 			"	movi	%1, 1f\n"
357 			"	s32i	%1, %4, 0\n"
358 			"	wsr	%2, scompare1\n"
359 			"1:	s32c1i	%0, %3, 0\n"
360 			: "=a" (set), "=&a" (tmp)
361 			: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
362 			: "memory"
363 			);
364 	return set;
365 }
366 
367 /* Handle probed exception */
368 
369 static void __init do_probed_exception(struct pt_regs *regs,
370 		unsigned long exccause)
371 {
372 	if (regs->pc == rcw_probe_pc) {	/* exception on s32c1i ? */
373 		regs->pc += 3;		/* skip the s32c1i instruction */
374 		rcw_exc = exccause;
375 	} else {
376 		do_unhandled(regs, exccause);
377 	}
378 }
379 
380 /* Simple test of S32C1I (soc bringup assist) */
381 
382 static int __init check_s32c1i(void)
383 {
384 	int n, cause1, cause2;
385 	void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
386 
387 	rcw_probe_pc = 0;
388 	handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
389 			do_probed_exception);
390 	handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
391 			do_probed_exception);
392 	handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
393 			do_probed_exception);
394 
395 	/* First try an S32C1I that does not store: */
396 	rcw_exc = 0;
397 	rcw_word = 1;
398 	n = probed_compare_swap(&rcw_word, 0, 2);
399 	cause1 = rcw_exc;
400 
401 	/* took exception? */
402 	if (cause1 != 0) {
403 		/* unclean exception? */
404 		if (n != 2 || rcw_word != 1)
405 			panic("S32C1I exception error");
406 	} else if (rcw_word != 1 || n != 1) {
407 		panic("S32C1I compare error");
408 	}
409 
410 	/* Then an S32C1I that stores: */
411 	rcw_exc = 0;
412 	rcw_word = 0x1234567;
413 	n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
414 	cause2 = rcw_exc;
415 
416 	if (cause2 != 0) {
417 		/* unclean exception? */
418 		if (n != 0xabcde || rcw_word != 0x1234567)
419 			panic("S32C1I exception error (b)");
420 	} else if (rcw_word != 0xabcde || n != 0x1234567) {
421 		panic("S32C1I store error");
422 	}
423 
424 	/* Verify consistency of exceptions: */
425 	if (cause1 || cause2) {
426 		pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
427 		/* If emulation of S32C1I upon bus error gets implemented,
428 		   we can get rid of this panic for single core (not SMP) */
429 		panic("S32C1I exceptions not currently supported");
430 	}
431 	if (cause1 != cause2)
432 		panic("inconsistent S32C1I exceptions");
433 
434 	trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
435 	trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
436 	trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
437 	return 0;
438 }
439 
440 #else /* XCHAL_HAVE_S32C1I */
441 
442 /* This condition should not occur with a commercially deployed processor.
443    Display reminder for early engr test or demo chips / FPGA bitstreams */
444 static int __init check_s32c1i(void)
445 {
446 	pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
447 	return 0;
448 }
449 
450 #endif /* XCHAL_HAVE_S32C1I */
451 early_initcall(check_s32c1i);
452 #endif /* CONFIG_S32C1I_SELFTEST */
453 
454 
455 void __init setup_arch(char **cmdline_p)
456 {
457 	strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
458 	*cmdline_p = command_line;
459 
460 	/* Reserve some memory regions */
461 
462 #ifdef CONFIG_BLK_DEV_INITRD
463 	if (initrd_start < initrd_end) {
464 		initrd_is_mapped = mem_reserve(__pa(initrd_start),
465 					       __pa(initrd_end), 0) == 0;
466 		initrd_below_start_ok = 1;
467 	} else {
468 		initrd_start = 0;
469 	}
470 #endif
471 
472 	mem_reserve(__pa(&_stext),__pa(&_end), 1);
473 
474 	mem_reserve(__pa(&_WindowVectors_text_start),
475 		    __pa(&_WindowVectors_text_end), 0);
476 
477 	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
478 		    __pa(&_DebugInterruptVector_text_end), 0);
479 
480 	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
481 		    __pa(&_KernelExceptionVector_text_end), 0);
482 
483 	mem_reserve(__pa(&_UserExceptionVector_literal_start),
484 		    __pa(&_UserExceptionVector_text_end), 0);
485 
486 	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
487 		    __pa(&_DoubleExceptionVector_text_end), 0);
488 
489 #if XCHAL_EXCM_LEVEL >= 2
490 	mem_reserve(__pa(&_Level2InterruptVector_text_start),
491 		    __pa(&_Level2InterruptVector_text_end), 0);
492 #endif
493 #if XCHAL_EXCM_LEVEL >= 3
494 	mem_reserve(__pa(&_Level3InterruptVector_text_start),
495 		    __pa(&_Level3InterruptVector_text_end), 0);
496 #endif
497 #if XCHAL_EXCM_LEVEL >= 4
498 	mem_reserve(__pa(&_Level4InterruptVector_text_start),
499 		    __pa(&_Level4InterruptVector_text_end), 0);
500 #endif
501 #if XCHAL_EXCM_LEVEL >= 5
502 	mem_reserve(__pa(&_Level5InterruptVector_text_start),
503 		    __pa(&_Level5InterruptVector_text_end), 0);
504 #endif
505 #if XCHAL_EXCM_LEVEL >= 6
506 	mem_reserve(__pa(&_Level6InterruptVector_text_start),
507 		    __pa(&_Level6InterruptVector_text_end), 0);
508 #endif
509 
510 	parse_early_param();
511 	bootmem_init();
512 
513 	unflatten_and_copy_device_tree();
514 
515 	platform_setup(cmdline_p);
516 
517 #ifdef CONFIG_SMP
518 	smp_init_cpus();
519 #endif
520 
521 	paging_init();
522 	zones_init();
523 
524 #ifdef CONFIG_VT
525 # if defined(CONFIG_VGA_CONSOLE)
526 	conswitchp = &vga_con;
527 # elif defined(CONFIG_DUMMY_CONSOLE)
528 	conswitchp = &dummy_con;
529 # endif
530 #endif
531 
532 #ifdef CONFIG_PCI
533 	platform_pcibios_init();
534 #endif
535 }
536 
537 static DEFINE_PER_CPU(struct cpu, cpu_data);
538 
539 static int __init topology_init(void)
540 {
541 	int i;
542 
543 	for_each_possible_cpu(i) {
544 		struct cpu *cpu = &per_cpu(cpu_data, i);
545 		cpu->hotpluggable = !!i;
546 		register_cpu(cpu, i);
547 	}
548 
549 	return 0;
550 }
551 subsys_initcall(topology_init);
552 
553 void machine_restart(char * cmd)
554 {
555 	platform_restart();
556 }
557 
558 void machine_halt(void)
559 {
560 	platform_halt();
561 	while (1);
562 }
563 
564 void machine_power_off(void)
565 {
566 	platform_power_off();
567 	while (1);
568 }
569 #ifdef CONFIG_PROC_FS
570 
571 /*
572  * Display some core information through /proc/cpuinfo.
573  */
574 
575 static int
576 c_show(struct seq_file *f, void *slot)
577 {
578 	char buf[NR_CPUS * 5];
579 
580 	cpulist_scnprintf(buf, sizeof(buf), cpu_online_mask);
581 	/* high-level stuff */
582 	seq_printf(f, "CPU count\t: %u\n"
583 		      "CPU list\t: %s\n"
584 		      "vendor_id\t: Tensilica\n"
585 		      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
586 		      "core ID\t\t: " XCHAL_CORE_ID "\n"
587 		      "build ID\t: 0x%x\n"
588 		      "byte order\t: %s\n"
589 		      "cpu MHz\t\t: %lu.%02lu\n"
590 		      "bogomips\t: %lu.%02lu\n",
591 		      num_online_cpus(),
592 		      buf,
593 		      XCHAL_BUILD_UNIQUE_ID,
594 		      XCHAL_HAVE_BE ?  "big" : "little",
595 		      ccount_freq/1000000,
596 		      (ccount_freq/10000) % 100,
597 		      loops_per_jiffy/(500000/HZ),
598 		      (loops_per_jiffy/(5000/HZ)) % 100);
599 
600 	seq_printf(f,"flags\t\t: "
601 #if XCHAL_HAVE_NMI
602 		     "nmi "
603 #endif
604 #if XCHAL_HAVE_DEBUG
605 		     "debug "
606 # if XCHAL_HAVE_OCD
607 		     "ocd "
608 # endif
609 #endif
610 #if XCHAL_HAVE_DENSITY
611 	    	     "density "
612 #endif
613 #if XCHAL_HAVE_BOOLEANS
614 		     "boolean "
615 #endif
616 #if XCHAL_HAVE_LOOPS
617 		     "loop "
618 #endif
619 #if XCHAL_HAVE_NSA
620 		     "nsa "
621 #endif
622 #if XCHAL_HAVE_MINMAX
623 		     "minmax "
624 #endif
625 #if XCHAL_HAVE_SEXT
626 		     "sext "
627 #endif
628 #if XCHAL_HAVE_CLAMPS
629 		     "clamps "
630 #endif
631 #if XCHAL_HAVE_MAC16
632 		     "mac16 "
633 #endif
634 #if XCHAL_HAVE_MUL16
635 		     "mul16 "
636 #endif
637 #if XCHAL_HAVE_MUL32
638 		     "mul32 "
639 #endif
640 #if XCHAL_HAVE_MUL32_HIGH
641 		     "mul32h "
642 #endif
643 #if XCHAL_HAVE_FP
644 		     "fpu "
645 #endif
646 #if XCHAL_HAVE_S32C1I
647 		     "s32c1i "
648 #endif
649 		     "\n");
650 
651 	/* Registers. */
652 	seq_printf(f,"physical aregs\t: %d\n"
653 		     "misc regs\t: %d\n"
654 		     "ibreak\t\t: %d\n"
655 		     "dbreak\t\t: %d\n",
656 		     XCHAL_NUM_AREGS,
657 		     XCHAL_NUM_MISC_REGS,
658 		     XCHAL_NUM_IBREAK,
659 		     XCHAL_NUM_DBREAK);
660 
661 
662 	/* Interrupt. */
663 	seq_printf(f,"num ints\t: %d\n"
664 		     "ext ints\t: %d\n"
665 		     "int levels\t: %d\n"
666 		     "timers\t\t: %d\n"
667 		     "debug level\t: %d\n",
668 		     XCHAL_NUM_INTERRUPTS,
669 		     XCHAL_NUM_EXTINTERRUPTS,
670 		     XCHAL_NUM_INTLEVELS,
671 		     XCHAL_NUM_TIMERS,
672 		     XCHAL_DEBUGLEVEL);
673 
674 	/* Cache */
675 	seq_printf(f,"icache line size: %d\n"
676 		     "icache ways\t: %d\n"
677 		     "icache size\t: %d\n"
678 		     "icache flags\t: "
679 #if XCHAL_ICACHE_LINE_LOCKABLE
680 		     "lock "
681 #endif
682 		     "\n"
683 		     "dcache line size: %d\n"
684 		     "dcache ways\t: %d\n"
685 		     "dcache size\t: %d\n"
686 		     "dcache flags\t: "
687 #if XCHAL_DCACHE_IS_WRITEBACK
688 		     "writeback "
689 #endif
690 #if XCHAL_DCACHE_LINE_LOCKABLE
691 		     "lock "
692 #endif
693 		     "\n",
694 		     XCHAL_ICACHE_LINESIZE,
695 		     XCHAL_ICACHE_WAYS,
696 		     XCHAL_ICACHE_SIZE,
697 		     XCHAL_DCACHE_LINESIZE,
698 		     XCHAL_DCACHE_WAYS,
699 		     XCHAL_DCACHE_SIZE);
700 
701 	return 0;
702 }
703 
704 /*
705  * We show only CPU #0 info.
706  */
707 static void *
708 c_start(struct seq_file *f, loff_t *pos)
709 {
710 	return (*pos == 0) ? (void *)1 : NULL;
711 }
712 
713 static void *
714 c_next(struct seq_file *f, void *v, loff_t *pos)
715 {
716 	return NULL;
717 }
718 
719 static void
720 c_stop(struct seq_file *f, void *v)
721 {
722 }
723 
724 const struct seq_operations cpuinfo_op =
725 {
726 	.start	= c_start,
727 	.next	= c_next,
728 	.stop	= c_stop,
729 	.show	= c_show,
730 };
731 
732 #endif /* CONFIG_PROC_FS */
733