1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DMA coherent memory allocation. 4 * 5 * Copyright (C) 2002 - 2005 Tensilica Inc. 6 * Copyright (C) 2015 Cadence Design Systems Inc. 7 * 8 * Based on version for i386. 9 * 10 * Chris Zankel <chris@zankel.net> 11 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> 12 */ 13 14 #include <linux/dma-contiguous.h> 15 #include <linux/dma-noncoherent.h> 16 #include <linux/dma-direct.h> 17 #include <linux/gfp.h> 18 #include <linux/highmem.h> 19 #include <linux/mm.h> 20 #include <linux/types.h> 21 #include <asm/cacheflush.h> 22 #include <asm/io.h> 23 #include <asm/platform.h> 24 25 static void do_cache_op(phys_addr_t paddr, size_t size, 26 void (*fn)(unsigned long, unsigned long)) 27 { 28 unsigned long off = paddr & (PAGE_SIZE - 1); 29 unsigned long pfn = PFN_DOWN(paddr); 30 struct page *page = pfn_to_page(pfn); 31 32 if (!PageHighMem(page)) 33 fn((unsigned long)phys_to_virt(paddr), size); 34 else 35 while (size > 0) { 36 size_t sz = min_t(size_t, size, PAGE_SIZE - off); 37 void *vaddr = kmap_atomic(page); 38 39 fn((unsigned long)vaddr + off, sz); 40 kunmap_atomic(vaddr); 41 off = 0; 42 ++page; 43 size -= sz; 44 } 45 } 46 47 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, 48 enum dma_data_direction dir) 49 { 50 switch (dir) { 51 case DMA_BIDIRECTIONAL: 52 case DMA_FROM_DEVICE: 53 do_cache_op(paddr, size, __invalidate_dcache_range); 54 break; 55 56 case DMA_NONE: 57 BUG(); 58 break; 59 60 default: 61 break; 62 } 63 } 64 65 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, 66 enum dma_data_direction dir) 67 { 68 switch (dir) { 69 case DMA_BIDIRECTIONAL: 70 case DMA_TO_DEVICE: 71 if (XCHAL_DCACHE_IS_WRITEBACK) 72 do_cache_op(paddr, size, __flush_dcache_range); 73 break; 74 75 case DMA_NONE: 76 BUG(); 77 break; 78 79 default: 80 break; 81 } 82 } 83 84 void arch_dma_prep_coherent(struct page *page, size_t size) 85 { 86 __invalidate_dcache_range((unsigned long)page_address(page), size); 87 } 88 89 /* 90 * Memory caching is platform-dependent in noMMU xtensa configurations. 91 * The following two functions should be implemented in platform code 92 * in order to enable coherent DMA memory operations when CONFIG_MMU is not 93 * enabled. 94 */ 95 #ifdef CONFIG_MMU 96 void *uncached_kernel_address(void *p) 97 { 98 return p + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR; 99 } 100 101 void *cached_kernel_address(void *p) 102 { 103 return p + XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_BYPASS_VADDR; 104 } 105 #endif /* CONFIG_MMU */ 106