xref: /linux/arch/xtensa/kernel/head.S (revision 0d456bad36d42d16022be045c8a53ddbb59ee478) 
1/*
2 * arch/xtensa/kernel/head.S
3 *
4 * Xtensa Processor startup code.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License.  See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 *
12 * Chris Zankel <chris@zankel.net>
13 * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
14 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
15 * Kevin Chea
16 */
17
18#include <asm/processor.h>
19#include <asm/page.h>
20#include <asm/cacheasm.h>
21#include <asm/initialize_mmu.h>
22
23#include <linux/init.h>
24#include <linux/linkage.h>
25
26/*
27 * This module contains the entry code for kernel images. It performs the
28 * minimal setup needed to call the generic C routines.
29 *
30 * Prerequisites:
31 *
32 * - The kernel image has been loaded to the actual address where it was
33 *   compiled to.
34 * - a2 contains either 0 or a pointer to a list of boot parameters.
35 *   (see setup.c for more details)
36 *
37 */
38
39/*
40 *  _start
41 *
42 *  The bootloader passes a pointer to a list of boot parameters in a2.
43 */
44
45	/* The first bytes of the kernel image must be an instruction, so we
46	 * manually allocate and define the literal constant we need for a jx
47	 * instruction.
48	 */
49
50	__HEAD
51ENTRY(_start)
52
53	_j	2f
54	.align	4
551:	.word	_startup
562:	l32r	a0, 1b
57	jx	a0
58
59ENDPROC(_start)
60
61	.section .init.text, "ax"
62
63ENTRY(_startup)
64
65	/* Disable interrupts and exceptions. */
66
67	movi	a0, LOCKLEVEL
68	wsr	a0, ps
69
70	/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
71
72	wsr	a2, excsave1
73
74	/* Start with a fresh windowbase and windowstart.  */
75
76	movi	a1, 1
77	movi	a0, 0
78	wsr	a1, windowstart
79	wsr	a0, windowbase
80	rsync
81
82	/* Set a0 to 0 for the remaining initialization. */
83
84	movi	a0, 0
85
86	/* Clear debugging registers. */
87
88#if XCHAL_HAVE_DEBUG
89	wsr	a0, ibreakenable
90	wsr	a0, icount
91	movi	a1, 15
92	wsr	a0, icountlevel
93
94	.set	_index, 0
95	.rept	XCHAL_NUM_DBREAK - 1
96	wsr	a0, SREG_DBREAKC + _index
97	.set	_index, _index + 1
98	.endr
99#endif
100
101	/* Clear CCOUNT (not really necessary, but nice) */
102
103	wsr	a0, ccount	# not really necessary, but nice
104
105	/* Disable zero-loops. */
106
107#if XCHAL_HAVE_LOOPS
108	wsr	a0, lcount
109#endif
110
111	/* Disable all timers. */
112
113	.set	_index, 0
114	.rept	XCHAL_NUM_TIMERS - 1
115	wsr	a0, SREG_CCOMPARE + _index
116	.set	_index, _index + 1
117	.endr
118
119	/* Interrupt initialization. */
120
121	movi	a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE
122	wsr	a0, intenable
123	wsr	a2, intclear
124
125	/* Disable coprocessors. */
126
127#if XCHAL_CP_NUM > 0
128	wsr	a0, cpenable
129#endif
130
131	/* Set PS.INTLEVEL=1, PS.WOE=0, kernel stack, PS.EXCM=0
132	 *
133	 * Note: PS.EXCM must be cleared before using any loop
134	 *	 instructions; otherwise, they are silently disabled, and
135	 * 	 at most one iteration of the loop is executed.
136	 */
137
138	movi	a1, 1
139	wsr	a1, ps
140	rsync
141
142	/*  Initialize the caches.
143	 *  a2, a3 are just working registers (clobbered).
144	 */
145
146#if XCHAL_DCACHE_LINE_LOCKABLE
147	___unlock_dcache_all a2 a3
148#endif
149
150#if XCHAL_ICACHE_LINE_LOCKABLE
151	___unlock_icache_all a2 a3
152#endif
153
154	___invalidate_dcache_all a2 a3
155	___invalidate_icache_all a2 a3
156
157	isync
158
159	initialize_mmu
160
161	/* Unpack data sections
162	 *
163	 * The linker script used to build the Linux kernel image
164	 * creates a table located at __boot_reloc_table_start
165	 * that contans the information what data needs to be unpacked.
166	 *
167	 * Uses a2-a7.
168	 */
169
170	movi	a2, __boot_reloc_table_start
171	movi	a3, __boot_reloc_table_end
172
1731:	beq	a2, a3, 3f	# no more entries?
174	l32i	a4, a2, 0	# start destination (in RAM)
175	l32i	a5, a2, 4	# end desination (in RAM)
176	l32i	a6, a2, 8	# start source (in ROM)
177	addi	a2, a2, 12	# next entry
178	beq	a4, a5, 1b	# skip, empty entry
179	beq	a4, a6, 1b	# skip, source and dest. are the same
180
1812:	l32i	a7, a6, 0	# load word
182	addi	a6, a6, 4
183	s32i	a7, a4, 0	# store word
184	addi	a4, a4, 4
185	bltu	a4, a5, 2b
186	j	1b
187
1883:
189	/* All code and initialized data segments have been copied.
190	 * Now clear the BSS segment.
191	 */
192
193	movi	a2, __bss_start	# start of BSS
194	movi	a3, __bss_stop	# end of BSS
195
196	__loopt	a2, a3, a4, 2
197	s32i	a0, a2, 0
198	__endla	a2, a4, 4
199
200#if XCHAL_DCACHE_IS_WRITEBACK
201
202	/* After unpacking, flush the writeback cache to memory so the
203	 * instructions/data are available.
204	 */
205
206	___flush_dcache_all a2 a3
207#endif
208
209	/* Setup stack and enable window exceptions (keep irqs disabled) */
210
211	movi	a1, init_thread_union
212	addi	a1, a1, KERNEL_STACK_SIZE
213
214	movi	a2, 0x00040001		# WOE=1, INTLEVEL=1, UM=0
215	wsr	a2, ps			# (enable reg-windows; progmode stack)
216	rsync
217
218	/* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/
219
220	movi	a2, debug_exception
221	wsr	a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
222
223	/* Set up EXCSAVE[1] to point to the exc_table. */
224
225	movi	a6, exc_table
226	xsr	a6, excsave1
227
228	/* init_arch kick-starts the linux kernel */
229
230	movi	a4, init_arch
231	callx4	a4
232
233	movi	a4, start_kernel
234	callx4	a4
235
236should_never_return:
237	j	should_never_return
238
239ENDPROC(_startup)
240
241/*
242 * BSS section
243 */
244
245__PAGE_ALIGNED_BSS
246#ifdef CONFIG_MMU
247ENTRY(swapper_pg_dir)
248	.fill	PAGE_SIZE, 1, 0
249END(swapper_pg_dir)
250#endif
251ENTRY(empty_zero_page)
252	.fill	PAGE_SIZE, 1, 0
253END(empty_zero_page)
254