1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2001 - 2008 Tensilica Inc. 7 * Copyright (C) 2015 Cadence Design Systems Inc. 8 */ 9 10 #ifndef _XTENSA_PROCESSOR_H 11 #define _XTENSA_PROCESSOR_H 12 13 #include <variant/core.h> 14 15 #include <linux/compiler.h> 16 #include <asm/ptrace.h> 17 #include <asm/types.h> 18 #include <asm/regs.h> 19 20 /* Assertions. */ 21 22 #if (XCHAL_HAVE_WINDOWED != 1) 23 # error Linux requires the Xtensa Windowed Registers Option. 24 #endif 25 26 #define ARCH_SLAB_MINALIGN XCHAL_DATA_WIDTH 27 28 /* 29 * User space process size: 1 GB. 30 * Windowed call ABI requires caller and callee to be located within the same 31 * 1 GB region. The C compiler places trampoline code on the stack for sources 32 * that take the address of a nested C function (a feature used by glibc), so 33 * the 1 GB requirement applies to the stack as well. 34 */ 35 36 #ifdef CONFIG_MMU 37 #define TASK_SIZE __XTENSA_UL_CONST(0x40000000) 38 #else 39 #define TASK_SIZE __XTENSA_UL_CONST(0xffffffff) 40 #endif 41 42 #define STACK_TOP TASK_SIZE 43 #define STACK_TOP_MAX STACK_TOP 44 45 /* 46 * General exception cause assigned to fake NMI. Fake NMI needs to be handled 47 * differently from other interrupts, but it uses common kernel entry/exit 48 * code. 49 */ 50 51 #define EXCCAUSE_MAPPED_NMI 62 52 53 /* 54 * General exception cause assigned to debug exceptions. Debug exceptions go 55 * to their own vector, rather than the general exception vectors (user, 56 * kernel, double); and their specific causes are reported via DEBUGCAUSE 57 * rather than EXCCAUSE. However it is sometimes convenient to redirect debug 58 * exceptions to the general exception mechanism. To do this, an otherwise 59 * unused EXCCAUSE value was assigned to debug exceptions for this purpose. 60 */ 61 62 #define EXCCAUSE_MAPPED_DEBUG 63 63 64 /* 65 * We use DEPC also as a flag to distinguish between double and regular 66 * exceptions. For performance reasons, DEPC might contain the value of 67 * EXCCAUSE for regular exceptions, so we use this definition to mark a 68 * valid double exception address. 69 * (Note: We use it in bgeui, so it should be 64, 128, or 256) 70 */ 71 72 #define VALID_DOUBLE_EXCEPTION_ADDRESS 64 73 74 #define XTENSA_INT_LEVEL(intno) _XTENSA_INT_LEVEL(intno) 75 #define _XTENSA_INT_LEVEL(intno) XCHAL_INT##intno##_LEVEL 76 77 #define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level) 78 #define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK) 79 80 #define XTENSA_INTLEVEL_ANDBELOW_MASK(l) _XTENSA_INTLEVEL_ANDBELOW_MASK(l) 81 #define _XTENSA_INTLEVEL_ANDBELOW_MASK(l) (XCHAL_INTLEVEL##l##_ANDBELOW_MASK) 82 83 #define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT) 84 85 /* LOCKLEVEL defines the interrupt level that masks all 86 * general-purpose interrupts. 87 */ 88 #if defined(CONFIG_XTENSA_FAKE_NMI) && defined(XCHAL_PROFILING_INTERRUPT) 89 #define LOCKLEVEL (PROFILING_INTLEVEL - 1) 90 #else 91 #define LOCKLEVEL XCHAL_EXCM_LEVEL 92 #endif 93 94 #define TOPLEVEL XCHAL_EXCM_LEVEL 95 #define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL) 96 97 /* WSBITS and WBBITS are the width of the WINDOWSTART and WINDOWBASE 98 * registers 99 */ 100 #define WSBITS (XCHAL_NUM_AREGS / 4) /* width of WINDOWSTART in bits */ 101 #define WBBITS (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE in bits */ 102 103 #ifndef __ASSEMBLY__ 104 105 /* Build a valid return address for the specified call winsize. 106 * winsize must be 1 (call4), 2 (call8), or 3 (call12) 107 */ 108 #define MAKE_RA_FOR_CALL(ra,ws) (((ra) & 0x3fffffff) | (ws) << 30) 109 110 /* Convert return address to a valid pc 111 * Note: We assume that the stack pointer is in the same 1GB ranges as the ra 112 */ 113 #define MAKE_PC_FROM_RA(ra,sp) (((ra) & 0x3fffffff) | ((sp) & 0xc0000000)) 114 115 /* Spill slot location for the register reg in the spill area under the stack 116 * pointer sp. reg must be in the range [0..4). 117 */ 118 #define SPILL_SLOT(sp, reg) (*(((unsigned long *)(sp)) - 4 + (reg))) 119 120 /* Spill slot location for the register reg in the spill area under the stack 121 * pointer sp for the call8. reg must be in the range [4..8). 122 */ 123 #define SPILL_SLOT_CALL8(sp, reg) (*(((unsigned long *)(sp)) - 12 + (reg))) 124 125 /* Spill slot location for the register reg in the spill area under the stack 126 * pointer sp for the call12. reg must be in the range [4..12). 127 */ 128 #define SPILL_SLOT_CALL12(sp, reg) (*(((unsigned long *)(sp)) - 16 + (reg))) 129 130 typedef struct { 131 unsigned long seg; 132 } mm_segment_t; 133 134 struct thread_struct { 135 136 /* kernel's return address and stack pointer for context switching */ 137 unsigned long ra; /* kernel's a0: return address and window call size */ 138 unsigned long sp; /* kernel's a1: stack pointer */ 139 140 mm_segment_t current_ds; /* see uaccess.h for example uses */ 141 142 /* struct xtensa_cpuinfo info; */ 143 144 unsigned long bad_vaddr; /* last user fault */ 145 unsigned long bad_uaddr; /* last kernel fault accessing user space */ 146 unsigned long error_code; 147 #ifdef CONFIG_HAVE_HW_BREAKPOINT 148 struct perf_event *ptrace_bp[XCHAL_NUM_IBREAK]; 149 struct perf_event *ptrace_wp[XCHAL_NUM_DBREAK]; 150 #endif 151 /* Make structure 16 bytes aligned. */ 152 int align[0] __attribute__ ((aligned(16))); 153 }; 154 155 156 /* 157 * Default implementation of macro that returns current 158 * instruction pointer ("program counter"). 159 */ 160 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 161 162 163 /* This decides where the kernel will search for a free chunk of vm 164 * space during mmap's. 165 */ 166 #define TASK_UNMAPPED_BASE (TASK_SIZE / 2) 167 168 #define INIT_THREAD \ 169 { \ 170 ra: 0, \ 171 sp: sizeof(init_stack) + (long) &init_stack, \ 172 current_ds: {0}, \ 173 /*info: {0}, */ \ 174 bad_vaddr: 0, \ 175 bad_uaddr: 0, \ 176 error_code: 0, \ 177 } 178 179 180 /* 181 * Do necessary setup to start up a newly executed thread. 182 * Note: We set-up ps as if we did a call4 to the new pc. 183 * set_thread_state in signal.c depends on it. 184 */ 185 #define USER_PS_VALUE ((1 << PS_WOE_BIT) | \ 186 (1 << PS_CALLINC_SHIFT) | \ 187 (USER_RING << PS_RING_SHIFT) | \ 188 (1 << PS_UM_BIT) | \ 189 (1 << PS_EXCM_BIT)) 190 191 /* Clearing a0 terminates the backtrace. */ 192 #define start_thread(regs, new_pc, new_sp) \ 193 memset(regs, 0, sizeof(*regs)); \ 194 regs->pc = new_pc; \ 195 regs->ps = USER_PS_VALUE; \ 196 regs->areg[1] = new_sp; \ 197 regs->areg[0] = 0; \ 198 regs->wmask = 1; \ 199 regs->depc = 0; \ 200 regs->windowbase = 0; \ 201 regs->windowstart = 1; 202 203 /* Forward declaration */ 204 struct task_struct; 205 struct mm_struct; 206 207 /* Free all resources held by a thread. */ 208 #define release_thread(thread) do { } while(0) 209 210 extern unsigned long get_wchan(struct task_struct *p); 211 212 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) 213 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->areg[1]) 214 215 #define cpu_relax() barrier() 216 217 /* Special register access. */ 218 219 #define WSR(v,sr) __asm__ __volatile__ ("wsr %0,"__stringify(sr) :: "a"(v)); 220 #define RSR(v,sr) __asm__ __volatile__ ("rsr %0,"__stringify(sr) : "=a"(v)); 221 222 #define set_sr(x,sr) ({unsigned int v=(unsigned int)x; WSR(v,sr);}) 223 #define get_sr(sr) ({unsigned int v; RSR(v,sr); v; }) 224 225 #ifndef XCHAL_HAVE_EXTERN_REGS 226 #define XCHAL_HAVE_EXTERN_REGS 0 227 #endif 228 229 #if XCHAL_HAVE_EXTERN_REGS 230 231 static inline void set_er(unsigned long value, unsigned long addr) 232 { 233 asm volatile ("wer %0, %1" : : "a" (value), "a" (addr) : "memory"); 234 } 235 236 static inline unsigned long get_er(unsigned long addr) 237 { 238 register unsigned long value; 239 asm volatile ("rer %0, %1" : "=a" (value) : "a" (addr) : "memory"); 240 return value; 241 } 242 243 #endif /* XCHAL_HAVE_EXTERN_REGS */ 244 245 #endif /* __ASSEMBLY__ */ 246 #endif /* _XTENSA_PROCESSOR_H */ 247