1 /* 2 * include/asm-xtensa/pgtable.h 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Copyright (C) 2001 - 2013 Tensilica Inc. 9 */ 10 11 #ifndef _XTENSA_PGTABLE_H 12 #define _XTENSA_PGTABLE_H 13 14 #include <asm-generic/pgtable-nopmd.h> 15 #include <asm/page.h> 16 17 /* 18 * We only use two ring levels, user and kernel space. 19 */ 20 21 #ifdef CONFIG_MMU 22 #define USER_RING 1 /* user ring level */ 23 #else 24 #define USER_RING 0 25 #endif 26 #define KERNEL_RING 0 /* kernel ring level */ 27 28 /* 29 * The Xtensa architecture port of Linux has a two-level page table system, 30 * i.e. the logical three-level Linux page table layout is folded. 31 * Each task has the following memory page tables: 32 * 33 * PGD table (page directory), ie. 3rd-level page table: 34 * One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables 35 * (Architectures that don't have the PMD folded point to the PMD tables) 36 * 37 * The pointer to the PGD table for a given task can be retrieved from 38 * the task structure (struct task_struct*) t, e.g. current(): 39 * (t->mm ? t->mm : t->active_mm)->pgd 40 * 41 * PMD tables (page middle-directory), ie. 2nd-level page tables: 42 * Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1). 43 * 44 * PTE tables (page table entry), ie. 1st-level page tables: 45 * One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE 46 * invalid_pte_table for absent mappings. 47 * 48 * The individual pages are 4 kB big with special pages for the empty_zero_page. 49 */ 50 51 #define PGDIR_SHIFT 22 52 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 53 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 54 55 /* 56 * Entries per page directory level: we use two-level, so 57 * we don't really have any PMD directory physically. 58 */ 59 #define PTRS_PER_PTE 1024 60 #define PTRS_PER_PTE_SHIFT 10 61 #define PTRS_PER_PGD 1024 62 #define PGD_ORDER 0 63 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 64 #define FIRST_USER_ADDRESS 0UL 65 #define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) 66 67 /* 68 * Virtual memory area. We keep a distance to other memory regions to be 69 * on the safe side. We also use this area for cache aliasing. 70 */ 71 #define VMALLOC_START 0xC0000000 72 #define VMALLOC_END 0xC7FEFFFF 73 #define TLBTEMP_BASE_1 0xC7FF0000 74 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE) 75 #if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE 76 #define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE) 77 #else 78 #define TLBTEMP_SIZE ICACHE_WAY_SIZE 79 #endif 80 81 /* 82 * For the Xtensa architecture, the PTE layout is as follows: 83 * 84 * 31------12 11 10-9 8-6 5-4 3-2 1-0 85 * +-----------------------------------------+ 86 * | | Software | HARDWARE | 87 * | PPN | ADW | RI |Attribute| 88 * +-----------------------------------------+ 89 * pte_none | MBZ | 01 | 11 | 00 | 90 * +-----------------------------------------+ 91 * present | PPN | 0 | 00 | ADW | RI | CA | wx | 92 * +- - - - - - - - - - - - - - - - - - - - -+ 93 * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 11 | 11 | 94 * +-----------------------------------------+ 95 * swap | index | type | 01 | 11 | 00 | 96 * +-----------------------------------------+ 97 * 98 * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE) 99 * +-----------------------------------------+ 100 * present | PPN | 0 | 00 | ADW | RI | CA | w1 | 101 * +-----------------------------------------+ 102 * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 01 | 00 | 103 * +-----------------------------------------+ 104 * 105 * Legend: 106 * PPN Physical Page Number 107 * ADW software: accessed (young) / dirty / writable 108 * RI ring (0=privileged, 1=user, 2 and 3 are unused) 109 * CA cache attribute: 00 bypass, 01 writeback, 10 writethrough 110 * (11 is invalid and used to mark pages that are not present) 111 * w page is writable (hw) 112 * x page is executable (hw) 113 * index swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB) 114 * (note that the index is always non-zero) 115 * type swap type (5 bits -> 32 types) 116 * 117 * Notes: 118 * - (PROT_NONE) is a special case of 'present' but causes an exception for 119 * any access (read, write, and execute). 120 * - 'multihit-exception' has the highest priority of all MMU exceptions, 121 * so the ring must be set to 'RING_USER' even for 'non-present' pages. 122 * - on older hardware, the exectuable flag was not supported and 123 * used as a 'valid' flag, so it needs to be always set. 124 * - we need to keep track of certain flags in software (dirty and young) 125 * to do this, we use write exceptions and have a separate software w-flag. 126 * - attribute value 1101 (and 1111 on T1050 and earlier) is reserved 127 */ 128 129 #define _PAGE_ATTRIB_MASK 0xf 130 131 #define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */ 132 #define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */ 133 134 #define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */ 135 #define _PAGE_CA_WB (1<<2) /* write-back */ 136 #define _PAGE_CA_WT (2<<2) /* write-through */ 137 #define _PAGE_CA_MASK (3<<2) 138 #define _PAGE_CA_INVALID (3<<2) 139 140 /* We use invalid attribute values to distinguish special pte entries */ 141 #if XCHAL_HW_VERSION_MAJOR < 2000 142 #define _PAGE_HW_VALID 0x01 /* older HW needed this bit set */ 143 #define _PAGE_NONE 0x04 144 #else 145 #define _PAGE_HW_VALID 0x00 146 #define _PAGE_NONE 0x0f 147 #endif 148 149 #define _PAGE_USER (1<<4) /* user access (ring=1) */ 150 151 /* Software */ 152 #define _PAGE_WRITABLE_BIT 6 153 #define _PAGE_WRITABLE (1<<6) /* software: page writable */ 154 #define _PAGE_DIRTY (1<<7) /* software: page dirty */ 155 #define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */ 156 157 #ifdef CONFIG_MMU 158 159 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 160 #define _PAGE_PRESENT (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED) 161 162 #define PAGE_NONE __pgprot(_PAGE_NONE | _PAGE_USER) 163 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER) 164 #define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC) 165 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER) 166 #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC) 167 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE) 168 #define PAGE_SHARED_EXEC \ 169 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC) 170 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE) 171 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC) 172 173 #if (DCACHE_WAY_SIZE > PAGE_SIZE) 174 # define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS) 175 #else 176 # define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB) 177 #endif 178 179 #else /* no mmu */ 180 181 # define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 182 # define PAGE_NONE __pgprot(0) 183 # define PAGE_SHARED __pgprot(0) 184 # define PAGE_COPY __pgprot(0) 185 # define PAGE_READONLY __pgprot(0) 186 # define PAGE_KERNEL __pgprot(0) 187 188 #endif 189 190 /* 191 * On certain configurations of Xtensa MMUs (eg. the initial Linux config), 192 * the MMU can't do page protection for execute, and considers that the same as 193 * read. Also, write permissions may imply read permissions. 194 * What follows is the closest we can get by reasonable means.. 195 * See linux/mm/mmap.c for protection_map[] array that uses these definitions. 196 */ 197 #define __P000 PAGE_NONE /* private --- */ 198 #define __P001 PAGE_READONLY /* private --r */ 199 #define __P010 PAGE_COPY /* private -w- */ 200 #define __P011 PAGE_COPY /* private -wr */ 201 #define __P100 PAGE_READONLY_EXEC /* private x-- */ 202 #define __P101 PAGE_READONLY_EXEC /* private x-r */ 203 #define __P110 PAGE_COPY_EXEC /* private xw- */ 204 #define __P111 PAGE_COPY_EXEC /* private xwr */ 205 206 #define __S000 PAGE_NONE /* shared --- */ 207 #define __S001 PAGE_READONLY /* shared --r */ 208 #define __S010 PAGE_SHARED /* shared -w- */ 209 #define __S011 PAGE_SHARED /* shared -wr */ 210 #define __S100 PAGE_READONLY_EXEC /* shared x-- */ 211 #define __S101 PAGE_READONLY_EXEC /* shared x-r */ 212 #define __S110 PAGE_SHARED_EXEC /* shared xw- */ 213 #define __S111 PAGE_SHARED_EXEC /* shared xwr */ 214 215 #ifndef __ASSEMBLY__ 216 217 #define pte_ERROR(e) \ 218 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 219 #define pgd_ERROR(e) \ 220 printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 221 222 extern unsigned long empty_zero_page[1024]; 223 224 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 225 226 #ifdef CONFIG_MMU 227 extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)]; 228 extern void paging_init(void); 229 #else 230 # define swapper_pg_dir NULL 231 static inline void paging_init(void) { } 232 #endif 233 static inline void pgtable_cache_init(void) { } 234 235 /* 236 * The pmd contains the kernel virtual address of the pte page. 237 */ 238 #define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK)) 239 #define pmd_page(pmd) virt_to_page(pmd_val(pmd)) 240 241 /* 242 * pte status. 243 */ 244 # define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER)) 245 #if XCHAL_HW_VERSION_MAJOR < 2000 246 # define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) 247 #else 248 # define pte_present(pte) \ 249 (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) \ 250 || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE)) 251 #endif 252 #define pte_clear(mm,addr,ptep) \ 253 do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0) 254 255 #define pmd_none(pmd) (!pmd_val(pmd)) 256 #define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK) 257 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 258 #define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0) 259 260 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; } 261 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 262 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 263 static inline int pte_special(pte_t pte) { return 0; } 264 265 static inline pte_t pte_wrprotect(pte_t pte) 266 { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; } 267 static inline pte_t pte_mkclean(pte_t pte) 268 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; } 269 static inline pte_t pte_mkold(pte_t pte) 270 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 271 static inline pte_t pte_mkdirty(pte_t pte) 272 { pte_val(pte) |= _PAGE_DIRTY; return pte; } 273 static inline pte_t pte_mkyoung(pte_t pte) 274 { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 275 static inline pte_t pte_mkwrite(pte_t pte) 276 { pte_val(pte) |= _PAGE_WRITABLE; return pte; } 277 static inline pte_t pte_mkspecial(pte_t pte) 278 { return pte; } 279 280 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK)) 281 282 /* 283 * Conversion functions: convert a page and protection to a page entry, 284 * and a page entry and page directory to the page they refer to. 285 */ 286 287 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 288 #define pte_same(a,b) (pte_val(a) == pte_val(b)) 289 #define pte_page(x) pfn_to_page(pte_pfn(x)) 290 #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 291 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 292 293 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 294 { 295 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 296 } 297 298 /* 299 * Certain architectures need to do special things when pte's 300 * within a page table are directly modified. Thus, the following 301 * hook is made available. 302 */ 303 static inline void update_pte(pte_t *ptep, pte_t pteval) 304 { 305 *ptep = pteval; 306 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK 307 __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep)); 308 #endif 309 310 } 311 312 struct mm_struct; 313 314 static inline void 315 set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval) 316 { 317 update_pte(ptep, pteval); 318 } 319 320 static inline void set_pte(pte_t *ptep, pte_t pteval) 321 { 322 update_pte(ptep, pteval); 323 } 324 325 static inline void 326 set_pmd(pmd_t *pmdp, pmd_t pmdval) 327 { 328 *pmdp = pmdval; 329 } 330 331 struct vm_area_struct; 332 333 static inline int 334 ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, 335 pte_t *ptep) 336 { 337 pte_t pte = *ptep; 338 if (!pte_young(pte)) 339 return 0; 340 update_pte(ptep, pte_mkold(pte)); 341 return 1; 342 } 343 344 static inline pte_t 345 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 346 { 347 pte_t pte = *ptep; 348 pte_clear(mm, addr, ptep); 349 return pte; 350 } 351 352 static inline void 353 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 354 { 355 pte_t pte = *ptep; 356 update_pte(ptep, pte_wrprotect(pte)); 357 } 358 359 /* to find an entry in a kernel page-table-directory */ 360 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 361 362 /* to find an entry in a page-table-directory */ 363 #define pgd_offset(mm,address) ((mm)->pgd + pgd_index(address)) 364 365 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 366 367 /* Find an entry in the second-level page table.. */ 368 #define pmd_offset(dir,address) ((pmd_t*)(dir)) 369 370 /* Find an entry in the third-level page table.. */ 371 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 372 #define pte_offset_kernel(dir,addr) \ 373 ((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr)) 374 #define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr)) 375 #define pte_unmap(pte) do { } while (0) 376 377 378 /* 379 * Encode and decode a swap and file entry. 380 */ 381 #define SWP_TYPE_BITS 5 382 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) 383 384 #define __swp_type(entry) (((entry).val >> 6) & 0x1f) 385 #define __swp_offset(entry) ((entry).val >> 11) 386 #define __swp_entry(type,offs) \ 387 ((swp_entry_t){((type) << 6) | ((offs) << 11) | \ 388 _PAGE_CA_INVALID | _PAGE_USER}) 389 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 390 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 391 392 #endif /* !defined (__ASSEMBLY__) */ 393 394 395 #ifdef __ASSEMBLY__ 396 397 /* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long), 398 * _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long), 399 * _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long) 400 * _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long) 401 * 402 * Note: We require an additional temporary register which can be the same as 403 * the register that holds the address. 404 * 405 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr)) 406 * 407 */ 408 #define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT 409 #define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT 410 411 #define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \ 412 _PGD_INDEX(tmp, adr); \ 413 addx4 mm, tmp, mm 414 415 #define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \ 416 srli pmd, pmd, PAGE_SHIFT; \ 417 slli pmd, pmd, PAGE_SHIFT; \ 418 addx4 pmd, tmp, pmd 419 420 #else 421 422 #define kern_addr_valid(addr) (1) 423 424 extern void update_mmu_cache(struct vm_area_struct * vma, 425 unsigned long address, pte_t *ptep); 426 427 typedef pte_t *pte_addr_t; 428 429 #endif /* !defined (__ASSEMBLY__) */ 430 431 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 432 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 433 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 434 #define __HAVE_ARCH_PTEP_MKDIRTY 435 #define __HAVE_ARCH_PTE_SAME 436 /* We provide our own get_unmapped_area to cope with 437 * SHM area cache aliasing for userland. 438 */ 439 #define HAVE_ARCH_UNMAPPED_AREA 440 441 #include <asm-generic/pgtable.h> 442 443 #endif /* _XTENSA_PGTABLE_H */ 444