1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_HAS_SG_CHAIN 5 select ARCH_HAS_SYNC_DMA_FOR_CPU 6 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 7 select ARCH_NO_COHERENT_DMA_MMAP if !MMU 8 select ARCH_WANT_FRAME_POINTERS 9 select ARCH_WANT_IPC_PARSE_VERSION 10 select BUILDTIME_EXTABLE_SORT 11 select CLONE_BACKWARDS 12 select COMMON_CLK 13 select DMA_DIRECT_OPS 14 select GENERIC_ATOMIC64 15 select GENERIC_CLOCKEVENTS 16 select GENERIC_IRQ_SHOW 17 select GENERIC_PCI_IOMAP 18 select GENERIC_SCHED_CLOCK 19 select GENERIC_STRNCPY_FROM_USER if KASAN 20 select HAVE_ARCH_KASAN if MMU 21 select HAVE_DEBUG_KMEMLEAK 22 select HAVE_DMA_CONTIGUOUS 23 select HAVE_EXIT_THREAD 24 select HAVE_FUNCTION_TRACER 25 select HAVE_FUTEX_CMPXCHG if !MMU 26 select HAVE_HW_BREAKPOINT if PERF_EVENTS 27 select HAVE_IRQ_TIME_ACCOUNTING 28 select HAVE_OPROFILE 29 select HAVE_PCI 30 select HAVE_PERF_EVENTS 31 select HAVE_STACKPROTECTOR 32 select IRQ_DOMAIN 33 select MODULES_USE_ELF_RELA 34 select PERF_USE_VMALLOC 35 select VIRT_TO_BUS 36 help 37 Xtensa processors are 32-bit RISC machines designed by Tensilica 38 primarily for embedded systems. These processors are both 39 configurable and extensible. The Linux port to the Xtensa 40 architecture supports all processor configurations and extensions, 41 with reasonable minimum requirements. The Xtensa Linux project has 42 a home page at <http://www.linux-xtensa.org/>. 43 44config RWSEM_XCHGADD_ALGORITHM 45 def_bool y 46 47config GENERIC_HWEIGHT 48 def_bool y 49 50config ARCH_HAS_ILOG2_U32 51 def_bool n 52 53config ARCH_HAS_ILOG2_U64 54 def_bool n 55 56config NO_IOPORT_MAP 57 def_bool n 58 59config HZ 60 int 61 default 100 62 63config LOCKDEP_SUPPORT 64 def_bool y 65 66config STACKTRACE_SUPPORT 67 def_bool y 68 69config TRACE_IRQFLAGS_SUPPORT 70 def_bool y 71 72config MMU 73 def_bool n 74 75config HAVE_XTENSA_GPIO32 76 def_bool n 77 78config KASAN_SHADOW_OFFSET 79 hex 80 default 0x6e400000 81 82menu "Processor type and features" 83 84choice 85 prompt "Xtensa Processor Configuration" 86 default XTENSA_VARIANT_FSF 87 88config XTENSA_VARIANT_FSF 89 bool "fsf - default (not generic) configuration" 90 select MMU 91 92config XTENSA_VARIANT_DC232B 93 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 94 select MMU 95 select HAVE_XTENSA_GPIO32 96 help 97 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 98 99config XTENSA_VARIANT_DC233C 100 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 101 select MMU 102 select HAVE_XTENSA_GPIO32 103 help 104 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 105 106config XTENSA_VARIANT_CUSTOM 107 bool "Custom Xtensa processor configuration" 108 select HAVE_XTENSA_GPIO32 109 help 110 Select this variant to use a custom Xtensa processor configuration. 111 You will be prompted for a processor variant CORENAME. 112endchoice 113 114config XTENSA_VARIANT_CUSTOM_NAME 115 string "Xtensa Processor Custom Core Variant Name" 116 depends on XTENSA_VARIANT_CUSTOM 117 help 118 Provide the name of a custom Xtensa processor variant. 119 This CORENAME selects arch/xtensa/variant/CORENAME. 120 Dont forget you have to select MMU if you have one. 121 122config XTENSA_VARIANT_NAME 123 string 124 default "dc232b" if XTENSA_VARIANT_DC232B 125 default "dc233c" if XTENSA_VARIANT_DC233C 126 default "fsf" if XTENSA_VARIANT_FSF 127 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 128 129config XTENSA_VARIANT_MMU 130 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 131 depends on XTENSA_VARIANT_CUSTOM 132 default y 133 select MMU 134 help 135 Build a Conventional Kernel with full MMU support, 136 ie: it supports a TLB with auto-loading, page protection. 137 138config XTENSA_VARIANT_HAVE_PERF_EVENTS 139 bool "Core variant has Performance Monitor Module" 140 depends on XTENSA_VARIANT_CUSTOM 141 default n 142 help 143 Enable if core variant has Performance Monitor Module with 144 External Registers Interface. 145 146 If unsure, say N. 147 148config XTENSA_FAKE_NMI 149 bool "Treat PMM IRQ as NMI" 150 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 151 default n 152 help 153 If PMM IRQ is the only IRQ at EXCM level it is safe to 154 treat it as NMI, which improves accuracy of profiling. 155 156 If there are other interrupts at or above PMM IRQ priority level 157 but not above the EXCM level, PMM IRQ still may be treated as NMI, 158 but only if these IRQs are not used. There will be a build warning 159 saying that this is not safe, and a bugcheck if one of these IRQs 160 actually fire. 161 162 If unsure, say N. 163 164config XTENSA_UNALIGNED_USER 165 bool "Unaligned memory access in use space" 166 help 167 The Xtensa architecture currently does not handle unaligned 168 memory accesses in hardware but through an exception handler. 169 Per default, unaligned memory accesses are disabled in user space. 170 171 Say Y here to enable unaligned memory access in user space. 172 173config HAVE_SMP 174 bool "System Supports SMP (MX)" 175 depends on XTENSA_VARIANT_CUSTOM 176 select XTENSA_MX 177 help 178 This option is use to indicate that the system-on-a-chip (SOC) 179 supports Multiprocessing. Multiprocessor support implemented above 180 the CPU core definition and currently needs to be selected manually. 181 182 Multiprocessor support in implemented with external cache and 183 interrupt controllers. 184 185 The MX interrupt distributer adds Interprocessor Interrupts 186 and causes the IRQ numbers to be increased by 4 for devices 187 like the open cores ethernet driver and the serial interface. 188 189 You still have to select "Enable SMP" to enable SMP on this SOC. 190 191config SMP 192 bool "Enable Symmetric multi-processing support" 193 depends on HAVE_SMP 194 select GENERIC_SMP_IDLE_THREAD 195 help 196 Enabled SMP Software; allows more than one CPU/CORE 197 to be activated during startup. 198 199config NR_CPUS 200 depends on SMP 201 int "Maximum number of CPUs (2-32)" 202 range 2 32 203 default "4" 204 205config HOTPLUG_CPU 206 bool "Enable CPU hotplug support" 207 depends on SMP 208 help 209 Say Y here to allow turning CPUs off and on. CPUs can be 210 controlled through /sys/devices/system/cpu. 211 212 Say N if you want to disable CPU hotplug. 213 214config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 215 bool "Initialize Xtensa MMU inside the Linux kernel code" 216 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 217 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 218 help 219 Earlier version initialized the MMU in the exception vector 220 before jumping to _startup in head.S and had an advantage that 221 it was possible to place a software breakpoint at 'reset' and 222 then enter your normal kernel breakpoints once the MMU was mapped 223 to the kernel mappings (0XC0000000). 224 225 This unfortunately won't work for U-Boot and likely also wont 226 work for using KEXEC to have a hot kernel ready for doing a 227 KDUMP. 228 229 So now the MMU is initialized in head.S but it's necessary to 230 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 231 xt-gdb can't place a Software Breakpoint in the 0XD region prior 232 to mapping the MMU and after mapping even if the area of low memory 233 was mapped gdb wouldn't remove the breakpoint on hitting it as the 234 PC wouldn't match. Since Hardware Breakpoints are recommended for 235 Linux configurations it seems reasonable to just assume they exist 236 and leave this older mechanism for unfortunate souls that choose 237 not to follow Tensilica's recommendation. 238 239 Selecting this will cause U-Boot to set the KERNEL Load and Entry 240 address at 0x00003000 instead of the mapped std of 0xD0003000. 241 242 If in doubt, say Y. 243 244config MEMMAP_CACHEATTR 245 hex "Cache attributes for the memory address space" 246 depends on !MMU 247 default 0x22222222 248 help 249 These cache attributes are set up for noMMU systems. Each hex digit 250 specifies cache attributes for the corresponding 512MB memory 251 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 252 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 253 254 Cache attribute values are specific for the MMU type, so e.g. 255 for region protection MMUs: 2 is cache bypass, 4 is WB cached, 256 1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable, 257 bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass, 258 1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is 259 reserved). 260 261config KSEG_PADDR 262 hex "Physical address of the KSEG mapping" 263 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 264 default 0x00000000 265 help 266 This is the physical address where KSEG is mapped. Please refer to 267 the chosen KSEG layout help for the required address alignment. 268 Unpacked kernel image (including vectors) must be located completely 269 within KSEG. 270 Physical memory below this address is not available to linux. 271 272 If unsure, leave the default value here. 273 274config KERNEL_LOAD_ADDRESS 275 hex "Kernel load address" 276 default 0x60003000 if !MMU 277 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 278 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 279 help 280 This is the address where the kernel is loaded. 281 It is virtual address for MMUv2 configurations and physical address 282 for all other configurations. 283 284 If unsure, leave the default value here. 285 286config VECTORS_OFFSET 287 hex "Kernel vectors offset" 288 default 0x00003000 289 help 290 This is the offset of the kernel image from the relocatable vectors 291 base. 292 293 If unsure, leave the default value here. 294 295choice 296 prompt "KSEG layout" 297 depends on MMU 298 default XTENSA_KSEG_MMU_V2 299 300config XTENSA_KSEG_MMU_V2 301 bool "MMUv2: 128MB cached + 128MB uncached" 302 help 303 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 304 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 305 without cache. 306 KSEG_PADDR must be aligned to 128MB. 307 308config XTENSA_KSEG_256M 309 bool "256MB cached + 256MB uncached" 310 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 311 help 312 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 313 with cache and to 0xc0000000 without cache. 314 KSEG_PADDR must be aligned to 256MB. 315 316config XTENSA_KSEG_512M 317 bool "512MB cached + 512MB uncached" 318 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 319 help 320 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 321 with cache and to 0xc0000000 without cache. 322 KSEG_PADDR must be aligned to 256MB. 323 324endchoice 325 326config HIGHMEM 327 bool "High Memory Support" 328 depends on MMU 329 help 330 Linux can use the full amount of RAM in the system by 331 default. However, the default MMUv2 setup only maps the 332 lowermost 128 MB of memory linearly to the areas starting 333 at 0xd0000000 (cached) and 0xd8000000 (uncached). 334 When there are more than 128 MB memory in the system not 335 all of it can be "permanently mapped" by the kernel. 336 The physical memory that's not permanently mapped is called 337 "high memory". 338 339 If you are compiling a kernel which will never run on a 340 machine with more than 128 MB total physical RAM, answer 341 N here. 342 343 If unsure, say Y. 344 345config FAST_SYSCALL_XTENSA 346 bool "Enable fast atomic syscalls" 347 default n 348 help 349 fast_syscall_xtensa is a syscall that can make atomic operations 350 on UP kernel when processor has no s32c1i support. 351 352 This syscall is deprecated. It may have issues when called with 353 invalid arguments. It is provided only for backwards compatibility. 354 Only enable it if your userspace software requires it. 355 356 If unsure, say N. 357 358config FAST_SYSCALL_SPILL_REGISTERS 359 bool "Enable spill registers syscall" 360 default n 361 help 362 fast_syscall_spill_registers is a syscall that spills all active 363 register windows of a calling userspace task onto its stack. 364 365 This syscall is deprecated. It may have issues when called with 366 invalid arguments. It is provided only for backwards compatibility. 367 Only enable it if your userspace software requires it. 368 369 If unsure, say N. 370 371endmenu 372 373config XTENSA_CALIBRATE_CCOUNT 374 def_bool n 375 help 376 On some platforms (XT2000, for example), the CPU clock rate can 377 vary. The frequency can be determined, however, by measuring 378 against a well known, fixed frequency, such as an UART oscillator. 379 380config SERIAL_CONSOLE 381 def_bool n 382 383menu "Platform options" 384 385choice 386 prompt "Xtensa System Type" 387 default XTENSA_PLATFORM_ISS 388 389config XTENSA_PLATFORM_ISS 390 bool "ISS" 391 select XTENSA_CALIBRATE_CCOUNT 392 select SERIAL_CONSOLE 393 help 394 ISS is an acronym for Tensilica's Instruction Set Simulator. 395 396config XTENSA_PLATFORM_XT2000 397 bool "XT2000" 398 select HAVE_IDE 399 help 400 XT2000 is the name of Tensilica's feature-rich emulation platform. 401 This hardware is capable of running a full Linux distribution. 402 403config XTENSA_PLATFORM_XTFPGA 404 bool "XTFPGA" 405 select ETHOC if ETHERNET 406 select PLATFORM_WANT_DEFAULT_MEM if !MMU 407 select SERIAL_CONSOLE 408 select XTENSA_CALIBRATE_CCOUNT 409 help 410 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 411 This hardware is capable of running a full Linux distribution. 412 413endchoice 414 415config PLATFORM_NR_IRQS 416 int 417 default 3 if XTENSA_PLATFORM_XT2000 418 default 0 419 420config XTENSA_CPU_CLOCK 421 int "CPU clock rate [MHz]" 422 depends on !XTENSA_CALIBRATE_CCOUNT 423 default 16 424 425config GENERIC_CALIBRATE_DELAY 426 bool "Auto calibration of the BogoMIPS value" 427 help 428 The BogoMIPS value can easily be derived from the CPU frequency. 429 430config CMDLINE_BOOL 431 bool "Default bootloader kernel arguments" 432 433config CMDLINE 434 string "Initial kernel command string" 435 depends on CMDLINE_BOOL 436 default "console=ttyS0,38400 root=/dev/ram" 437 help 438 On some architectures (EBSA110 and CATS), there is currently no way 439 for the boot loader to pass arguments to the kernel. For these 440 architectures, you should supply some command-line options at build 441 time by entering them here. As a minimum, you should specify the 442 memory size and the root device (e.g., mem=64M root=/dev/nfs). 443 444config USE_OF 445 bool "Flattened Device Tree support" 446 select OF 447 select OF_EARLY_FLATTREE 448 select OF_RESERVED_MEM 449 help 450 Include support for flattened device tree machine descriptions. 451 452config BUILTIN_DTB 453 string "DTB to build into the kernel image" 454 depends on OF 455 456config PARSE_BOOTPARAM 457 bool "Parse bootparam block" 458 default y 459 help 460 Parse parameters passed to the kernel from the bootloader. It may 461 be disabled if the kernel is known to run without the bootloader. 462 463 If unsure, say Y. 464 465config BLK_DEV_SIMDISK 466 tristate "Host file-based simulated block device support" 467 default n 468 depends on XTENSA_PLATFORM_ISS && BLOCK 469 help 470 Create block devices that map to files in the host file system. 471 Device binding to host file may be changed at runtime via proc 472 interface provided the device is not in use. 473 474config BLK_DEV_SIMDISK_COUNT 475 int "Number of host file-based simulated block devices" 476 range 1 10 477 depends on BLK_DEV_SIMDISK 478 default 2 479 help 480 This is the default minimal number of created block devices. 481 Kernel/module parameter 'simdisk_count' may be used to change this 482 value at runtime. More file names (but no more than 10) may be 483 specified as parameters, simdisk_count grows accordingly. 484 485config SIMDISK0_FILENAME 486 string "Host filename for the first simulated device" 487 depends on BLK_DEV_SIMDISK = y 488 default "" 489 help 490 Attach a first simdisk to a host file. Conventionally, this file 491 contains a root file system. 492 493config SIMDISK1_FILENAME 494 string "Host filename for the second simulated device" 495 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 496 default "" 497 help 498 Another simulated disk in a host file for a buildroot-independent 499 storage. 500 501config FORCE_MAX_ZONEORDER 502 int "Maximum zone order" 503 default "11" 504 help 505 The kernel memory allocator divides physically contiguous memory 506 blocks into "zones", where each zone is a power of two number of 507 pages. This option selects the largest power of two that the kernel 508 keeps in the memory allocator. If you need to allocate very large 509 blocks of physically contiguous memory, then you may need to 510 increase this value. 511 512 This config option is actually maximum order plus one. For example, 513 a value of 11 means that the largest free memory block is 2^10 pages. 514 515source "drivers/pcmcia/Kconfig" 516 517config PLATFORM_WANT_DEFAULT_MEM 518 def_bool n 519 520config DEFAULT_MEM_START 521 hex 522 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 523 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 524 default 0x00000000 525 help 526 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 527 in noMMU configurations. 528 529 If unsure, leave the default value here. 530 531config XTFPGA_LCD 532 bool "Enable XTFPGA LCD driver" 533 depends on XTENSA_PLATFORM_XTFPGA 534 default n 535 help 536 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 537 progress messages there during bootup/shutdown. It may be useful 538 during board bringup. 539 540 If unsure, say N. 541 542config XTFPGA_LCD_BASE_ADDR 543 hex "XTFPGA LCD base address" 544 depends on XTFPGA_LCD 545 default "0x0d0c0000" 546 help 547 Base address of the LCD controller inside KIO region. 548 Different boards from XTFPGA family have LCD controller at different 549 addresses. Please consult prototyping user guide for your board for 550 the correct address. Wrong address here may lead to hardware lockup. 551 552config XTFPGA_LCD_8BIT_ACCESS 553 bool "Use 8-bit access to XTFPGA LCD" 554 depends on XTFPGA_LCD 555 default n 556 help 557 LCD may be connected with 4- or 8-bit interface, 8-bit access may 558 only be used with 8-bit interface. Please consult prototyping user 559 guide for your board for the correct interface width. 560 561endmenu 562 563menu "Power management options" 564 565source "kernel/power/Kconfig" 566 567endmenu 568