1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_BINFMT_FLAT if !MMU 6 select ARCH_HAS_DMA_PREP_COHERENT if MMU 7 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 9 select ARCH_HAS_DMA_SET_UNCACHED if MMU 10 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN 11 select ARCH_HAS_STRNLEN_USER 12 select ARCH_USE_MEMTEST 13 select ARCH_USE_QUEUED_RWLOCKS 14 select ARCH_USE_QUEUED_SPINLOCKS 15 select ARCH_WANT_FRAME_POINTERS 16 select ARCH_WANT_IPC_PARSE_VERSION 17 select BUILDTIME_TABLE_SORT 18 select CLONE_BACKWARDS 19 select COMMON_CLK 20 select DMA_REMAP if MMU 21 select GENERIC_ATOMIC64 22 select GENERIC_IRQ_SHOW 23 select GENERIC_LIB_CMPDI2 24 select GENERIC_LIB_MULDI3 25 select GENERIC_LIB_UCMPDI2 26 select GENERIC_PCI_IOMAP 27 select GENERIC_SCHED_CLOCK 28 select HAVE_ARCH_AUDITSYSCALL 29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 30 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 31 select HAVE_ARCH_SECCOMP_FILTER 32 select HAVE_ARCH_TRACEHOOK 33 select HAVE_DEBUG_KMEMLEAK 34 select HAVE_DMA_CONTIGUOUS 35 select HAVE_EXIT_THREAD 36 select HAVE_FUNCTION_TRACER 37 select HAVE_HW_BREAKPOINT if PERF_EVENTS 38 select HAVE_IRQ_TIME_ACCOUNTING 39 select HAVE_PCI 40 select HAVE_PERF_EVENTS 41 select HAVE_STACKPROTECTOR 42 select HAVE_SYSCALL_TRACEPOINTS 43 select IRQ_DOMAIN 44 select MODULES_USE_ELF_RELA 45 select PERF_USE_VMALLOC 46 select SET_FS 47 select TRACE_IRQFLAGS_SUPPORT 48 select VIRT_TO_BUS 49 help 50 Xtensa processors are 32-bit RISC machines designed by Tensilica 51 primarily for embedded systems. These processors are both 52 configurable and extensible. The Linux port to the Xtensa 53 architecture supports all processor configurations and extensions, 54 with reasonable minimum requirements. The Xtensa Linux project has 55 a home page at <http://www.linux-xtensa.org/>. 56 57config GENERIC_HWEIGHT 58 def_bool y 59 60config ARCH_HAS_ILOG2_U32 61 def_bool n 62 63config ARCH_HAS_ILOG2_U64 64 def_bool n 65 66config NO_IOPORT_MAP 67 def_bool n 68 69config HZ 70 int 71 default 100 72 73config LOCKDEP_SUPPORT 74 def_bool y 75 76config STACKTRACE_SUPPORT 77 def_bool y 78 79config MMU 80 def_bool n 81 82config HAVE_XTENSA_GPIO32 83 def_bool n 84 85config KASAN_SHADOW_OFFSET 86 hex 87 default 0x6e400000 88 89config CPU_BIG_ENDIAN 90 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1) 91 92config CPU_LITTLE_ENDIAN 93 def_bool !CPU_BIG_ENDIAN 94 95config CC_HAVE_CALL0_ABI 96 def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1) 97 98menu "Processor type and features" 99 100choice 101 prompt "Xtensa Processor Configuration" 102 default XTENSA_VARIANT_FSF 103 104config XTENSA_VARIANT_FSF 105 bool "fsf - default (not generic) configuration" 106 select MMU 107 108config XTENSA_VARIANT_DC232B 109 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 110 select MMU 111 select HAVE_XTENSA_GPIO32 112 help 113 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 114 115config XTENSA_VARIANT_DC233C 116 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 117 select MMU 118 select HAVE_XTENSA_GPIO32 119 help 120 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 121 122config XTENSA_VARIANT_CUSTOM 123 bool "Custom Xtensa processor configuration" 124 select HAVE_XTENSA_GPIO32 125 help 126 Select this variant to use a custom Xtensa processor configuration. 127 You will be prompted for a processor variant CORENAME. 128endchoice 129 130config XTENSA_VARIANT_CUSTOM_NAME 131 string "Xtensa Processor Custom Core Variant Name" 132 depends on XTENSA_VARIANT_CUSTOM 133 help 134 Provide the name of a custom Xtensa processor variant. 135 This CORENAME selects arch/xtensa/variant/CORENAME. 136 Don't forget you have to select MMU if you have one. 137 138config XTENSA_VARIANT_NAME 139 string 140 default "dc232b" if XTENSA_VARIANT_DC232B 141 default "dc233c" if XTENSA_VARIANT_DC233C 142 default "fsf" if XTENSA_VARIANT_FSF 143 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 144 145config XTENSA_VARIANT_MMU 146 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 147 depends on XTENSA_VARIANT_CUSTOM 148 default y 149 select MMU 150 help 151 Build a Conventional Kernel with full MMU support, 152 ie: it supports a TLB with auto-loading, page protection. 153 154config XTENSA_VARIANT_HAVE_PERF_EVENTS 155 bool "Core variant has Performance Monitor Module" 156 depends on XTENSA_VARIANT_CUSTOM 157 default n 158 help 159 Enable if core variant has Performance Monitor Module with 160 External Registers Interface. 161 162 If unsure, say N. 163 164config XTENSA_FAKE_NMI 165 bool "Treat PMM IRQ as NMI" 166 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 167 default n 168 help 169 If PMM IRQ is the only IRQ at EXCM level it is safe to 170 treat it as NMI, which improves accuracy of profiling. 171 172 If there are other interrupts at or above PMM IRQ priority level 173 but not above the EXCM level, PMM IRQ still may be treated as NMI, 174 but only if these IRQs are not used. There will be a build warning 175 saying that this is not safe, and a bugcheck if one of these IRQs 176 actually fire. 177 178 If unsure, say N. 179 180config XTENSA_UNALIGNED_USER 181 bool "Unaligned memory access in user space" 182 help 183 The Xtensa architecture currently does not handle unaligned 184 memory accesses in hardware but through an exception handler. 185 Per default, unaligned memory accesses are disabled in user space. 186 187 Say Y here to enable unaligned memory access in user space. 188 189config HAVE_SMP 190 bool "System Supports SMP (MX)" 191 depends on XTENSA_VARIANT_CUSTOM 192 select XTENSA_MX 193 help 194 This option is used to indicate that the system-on-a-chip (SOC) 195 supports Multiprocessing. Multiprocessor support implemented above 196 the CPU core definition and currently needs to be selected manually. 197 198 Multiprocessor support is implemented with external cache and 199 interrupt controllers. 200 201 The MX interrupt distributer adds Interprocessor Interrupts 202 and causes the IRQ numbers to be increased by 4 for devices 203 like the open cores ethernet driver and the serial interface. 204 205 You still have to select "Enable SMP" to enable SMP on this SOC. 206 207config SMP 208 bool "Enable Symmetric multi-processing support" 209 depends on HAVE_SMP 210 select GENERIC_SMP_IDLE_THREAD 211 help 212 Enabled SMP Software; allows more than one CPU/CORE 213 to be activated during startup. 214 215config NR_CPUS 216 depends on SMP 217 int "Maximum number of CPUs (2-32)" 218 range 2 32 219 default "4" 220 221config HOTPLUG_CPU 222 bool "Enable CPU hotplug support" 223 depends on SMP 224 help 225 Say Y here to allow turning CPUs off and on. CPUs can be 226 controlled through /sys/devices/system/cpu. 227 228 Say N if you want to disable CPU hotplug. 229 230config SECONDARY_RESET_VECTOR 231 bool "Secondary cores use alternative reset vector" 232 default y 233 depends on HAVE_SMP 234 help 235 Secondary cores may be configured to use alternative reset vector, 236 or all cores may use primary reset vector. 237 Say Y here to supply handler for the alternative reset location. 238 239config FAST_SYSCALL_XTENSA 240 bool "Enable fast atomic syscalls" 241 default n 242 help 243 fast_syscall_xtensa is a syscall that can make atomic operations 244 on UP kernel when processor has no s32c1i support. 245 246 This syscall is deprecated. It may have issues when called with 247 invalid arguments. It is provided only for backwards compatibility. 248 Only enable it if your userspace software requires it. 249 250 If unsure, say N. 251 252config FAST_SYSCALL_SPILL_REGISTERS 253 bool "Enable spill registers syscall" 254 default n 255 help 256 fast_syscall_spill_registers is a syscall that spills all active 257 register windows of a calling userspace task onto its stack. 258 259 This syscall is deprecated. It may have issues when called with 260 invalid arguments. It is provided only for backwards compatibility. 261 Only enable it if your userspace software requires it. 262 263 If unsure, say N. 264 265choice 266 prompt "Kernel ABI" 267 default KERNEL_ABI_DEFAULT 268 help 269 Select ABI for the kernel code. This ABI is independent of the 270 supported userspace ABI and any combination of the 271 kernel/userspace ABI is possible and should work. 272 273 In case both kernel and userspace support only call0 ABI 274 all register windows support code will be omitted from the 275 build. 276 277 If unsure, choose the default ABI. 278 279config KERNEL_ABI_DEFAULT 280 bool "Default ABI" 281 help 282 Select this option to compile kernel code with the default ABI 283 selected for the toolchain. 284 Normally cores with windowed registers option use windowed ABI and 285 cores without it use call0 ABI. 286 287config KERNEL_ABI_CALL0 288 bool "Call0 ABI" if CC_HAVE_CALL0_ABI 289 help 290 Select this option to compile kernel code with call0 ABI even with 291 toolchain that defaults to windowed ABI. 292 When this option is not selected the default toolchain ABI will 293 be used for the kernel code. 294 295endchoice 296 297config USER_ABI_CALL0 298 bool 299 300choice 301 prompt "Userspace ABI" 302 default USER_ABI_DEFAULT 303 help 304 Select supported userspace ABI. 305 306 If unsure, choose the default ABI. 307 308config USER_ABI_DEFAULT 309 bool "Default ABI only" 310 help 311 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 312 call0 ABI binaries may be run on such kernel, but signal delivery 313 will not work correctly for them. 314 315config USER_ABI_CALL0_ONLY 316 bool "Call0 ABI only" 317 select USER_ABI_CALL0 318 help 319 Select this option to support only call0 ABI in userspace. 320 Windowed ABI binaries will crash with a segfault caused by 321 an illegal instruction exception on the first 'entry' opcode. 322 323 Choose this option if you're planning to run only user code 324 built with call0 ABI. 325 326config USER_ABI_CALL0_PROBE 327 bool "Support both windowed and call0 ABI by probing" 328 select USER_ABI_CALL0 329 help 330 Select this option to support both windowed and call0 userspace 331 ABIs. When enabled all processes are started with PS.WOE disabled 332 and a fast user exception handler for an illegal instruction is 333 used to turn on PS.WOE bit on the first 'entry' opcode executed by 334 the userspace. 335 336 This option should be enabled for the kernel that must support 337 both call0 and windowed ABIs in userspace at the same time. 338 339 Note that Xtensa ISA does not guarantee that entry opcode will 340 raise an illegal instruction exception on cores with XEA2 when 341 PS.WOE is disabled, check whether the target core supports it. 342 343endchoice 344 345endmenu 346 347config XTENSA_CALIBRATE_CCOUNT 348 def_bool n 349 help 350 On some platforms (XT2000, for example), the CPU clock rate can 351 vary. The frequency can be determined, however, by measuring 352 against a well known, fixed frequency, such as an UART oscillator. 353 354config SERIAL_CONSOLE 355 def_bool n 356 357config PLATFORM_HAVE_XIP 358 def_bool n 359 360menu "Platform options" 361 362choice 363 prompt "Xtensa System Type" 364 default XTENSA_PLATFORM_ISS 365 366config XTENSA_PLATFORM_ISS 367 bool "ISS" 368 select XTENSA_CALIBRATE_CCOUNT 369 select SERIAL_CONSOLE 370 help 371 ISS is an acronym for Tensilica's Instruction Set Simulator. 372 373config XTENSA_PLATFORM_XT2000 374 bool "XT2000" 375 help 376 XT2000 is the name of Tensilica's feature-rich emulation platform. 377 This hardware is capable of running a full Linux distribution. 378 379config XTENSA_PLATFORM_XTFPGA 380 bool "XTFPGA" 381 select ETHOC if ETHERNET 382 select PLATFORM_WANT_DEFAULT_MEM if !MMU 383 select SERIAL_CONSOLE 384 select XTENSA_CALIBRATE_CCOUNT 385 select PLATFORM_HAVE_XIP 386 help 387 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 388 This hardware is capable of running a full Linux distribution. 389 390endchoice 391 392config PLATFORM_NR_IRQS 393 int 394 default 3 if XTENSA_PLATFORM_XT2000 395 default 0 396 397config XTENSA_CPU_CLOCK 398 int "CPU clock rate [MHz]" 399 depends on !XTENSA_CALIBRATE_CCOUNT 400 default 16 401 402config GENERIC_CALIBRATE_DELAY 403 bool "Auto calibration of the BogoMIPS value" 404 help 405 The BogoMIPS value can easily be derived from the CPU frequency. 406 407config CMDLINE_BOOL 408 bool "Default bootloader kernel arguments" 409 410config CMDLINE 411 string "Initial kernel command string" 412 depends on CMDLINE_BOOL 413 default "console=ttyS0,38400 root=/dev/ram" 414 help 415 On some architectures (EBSA110 and CATS), there is currently no way 416 for the boot loader to pass arguments to the kernel. For these 417 architectures, you should supply some command-line options at build 418 time by entering them here. As a minimum, you should specify the 419 memory size and the root device (e.g., mem=64M root=/dev/nfs). 420 421config USE_OF 422 bool "Flattened Device Tree support" 423 select OF 424 select OF_EARLY_FLATTREE 425 help 426 Include support for flattened device tree machine descriptions. 427 428config BUILTIN_DTB_SOURCE 429 string "DTB to build into the kernel image" 430 depends on OF 431 432config PARSE_BOOTPARAM 433 bool "Parse bootparam block" 434 default y 435 help 436 Parse parameters passed to the kernel from the bootloader. It may 437 be disabled if the kernel is known to run without the bootloader. 438 439 If unsure, say Y. 440 441choice 442 prompt "Semihosting interface" 443 default XTENSA_SIMCALL_ISS 444 depends on XTENSA_PLATFORM_ISS 445 help 446 Choose semihosting interface that will be used for serial port, 447 block device and networking. 448 449config XTENSA_SIMCALL_ISS 450 bool "simcall" 451 help 452 Use simcall instruction. simcall is only available on simulators, 453 it does nothing on hardware. 454 455config XTENSA_SIMCALL_GDBIO 456 bool "GDBIO" 457 help 458 Use break instruction. It is available on real hardware when GDB 459 is attached to it via JTAG. 460 461endchoice 462 463config BLK_DEV_SIMDISK 464 tristate "Host file-based simulated block device support" 465 default n 466 depends on XTENSA_PLATFORM_ISS && BLOCK 467 help 468 Create block devices that map to files in the host file system. 469 Device binding to host file may be changed at runtime via proc 470 interface provided the device is not in use. 471 472config BLK_DEV_SIMDISK_COUNT 473 int "Number of host file-based simulated block devices" 474 range 1 10 475 depends on BLK_DEV_SIMDISK 476 default 2 477 help 478 This is the default minimal number of created block devices. 479 Kernel/module parameter 'simdisk_count' may be used to change this 480 value at runtime. More file names (but no more than 10) may be 481 specified as parameters, simdisk_count grows accordingly. 482 483config SIMDISK0_FILENAME 484 string "Host filename for the first simulated device" 485 depends on BLK_DEV_SIMDISK = y 486 default "" 487 help 488 Attach a first simdisk to a host file. Conventionally, this file 489 contains a root file system. 490 491config SIMDISK1_FILENAME 492 string "Host filename for the second simulated device" 493 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 494 default "" 495 help 496 Another simulated disk in a host file for a buildroot-independent 497 storage. 498 499config XTFPGA_LCD 500 bool "Enable XTFPGA LCD driver" 501 depends on XTENSA_PLATFORM_XTFPGA 502 default n 503 help 504 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 505 progress messages there during bootup/shutdown. It may be useful 506 during board bringup. 507 508 If unsure, say N. 509 510config XTFPGA_LCD_BASE_ADDR 511 hex "XTFPGA LCD base address" 512 depends on XTFPGA_LCD 513 default "0x0d0c0000" 514 help 515 Base address of the LCD controller inside KIO region. 516 Different boards from XTFPGA family have LCD controller at different 517 addresses. Please consult prototyping user guide for your board for 518 the correct address. Wrong address here may lead to hardware lockup. 519 520config XTFPGA_LCD_8BIT_ACCESS 521 bool "Use 8-bit access to XTFPGA LCD" 522 depends on XTFPGA_LCD 523 default n 524 help 525 LCD may be connected with 4- or 8-bit interface, 8-bit access may 526 only be used with 8-bit interface. Please consult prototyping user 527 guide for your board for the correct interface width. 528 529comment "Kernel memory layout" 530 531config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 532 bool "Initialize Xtensa MMU inside the Linux kernel code" 533 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 534 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 535 help 536 Earlier version initialized the MMU in the exception vector 537 before jumping to _startup in head.S and had an advantage that 538 it was possible to place a software breakpoint at 'reset' and 539 then enter your normal kernel breakpoints once the MMU was mapped 540 to the kernel mappings (0XC0000000). 541 542 This unfortunately won't work for U-Boot and likely also won't 543 work for using KEXEC to have a hot kernel ready for doing a 544 KDUMP. 545 546 So now the MMU is initialized in head.S but it's necessary to 547 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 548 xt-gdb can't place a Software Breakpoint in the 0XD region prior 549 to mapping the MMU and after mapping even if the area of low memory 550 was mapped gdb wouldn't remove the breakpoint on hitting it as the 551 PC wouldn't match. Since Hardware Breakpoints are recommended for 552 Linux configurations it seems reasonable to just assume they exist 553 and leave this older mechanism for unfortunate souls that choose 554 not to follow Tensilica's recommendation. 555 556 Selecting this will cause U-Boot to set the KERNEL Load and Entry 557 address at 0x00003000 instead of the mapped std of 0xD0003000. 558 559 If in doubt, say Y. 560 561config XIP_KERNEL 562 bool "Kernel Execute-In-Place from ROM" 563 depends on PLATFORM_HAVE_XIP 564 help 565 Execute-In-Place allows the kernel to run from non-volatile storage 566 directly addressable by the CPU, such as NOR flash. This saves RAM 567 space since the text section of the kernel is not loaded from flash 568 to RAM. Read-write sections, such as the data section and stack, 569 are still copied to RAM. The XIP kernel is not compressed since 570 it has to run directly from flash, so it will take more space to 571 store it. The flash address used to link the kernel object files, 572 and for storing it, is configuration dependent. Therefore, if you 573 say Y here, you must know the proper physical address where to 574 store the kernel image depending on your own flash memory usage. 575 576 Also note that the make target becomes "make xipImage" rather than 577 "make Image" or "make uImage". The final kernel binary to put in 578 ROM memory will be arch/xtensa/boot/xipImage. 579 580 If unsure, say N. 581 582config MEMMAP_CACHEATTR 583 hex "Cache attributes for the memory address space" 584 depends on !MMU 585 default 0x22222222 586 help 587 These cache attributes are set up for noMMU systems. Each hex digit 588 specifies cache attributes for the corresponding 512MB memory 589 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 590 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 591 592 Cache attribute values are specific for the MMU type. 593 For region protection MMUs: 594 1: WT cached, 595 2: cache bypass, 596 4: WB cached, 597 f: illegal. 598 For full MMU: 599 bit 0: executable, 600 bit 1: writable, 601 bits 2..3: 602 0: cache bypass, 603 1: WB cache, 604 2: WT cache, 605 3: special (c and e are illegal, f is reserved). 606 For MPU: 607 0: illegal, 608 1: WB cache, 609 2: WB, no-write-allocate cache, 610 3: WT cache, 611 4: cache bypass. 612 613config KSEG_PADDR 614 hex "Physical address of the KSEG mapping" 615 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 616 default 0x00000000 617 help 618 This is the physical address where KSEG is mapped. Please refer to 619 the chosen KSEG layout help for the required address alignment. 620 Unpacked kernel image (including vectors) must be located completely 621 within KSEG. 622 Physical memory below this address is not available to linux. 623 624 If unsure, leave the default value here. 625 626config KERNEL_VIRTUAL_ADDRESS 627 hex "Kernel virtual address" 628 depends on MMU && XIP_KERNEL 629 default 0xd0003000 630 help 631 This is the virtual address where the XIP kernel is mapped. 632 XIP kernel may be mapped into KSEG or KIO region, virtual address 633 provided here must match kernel load address provided in 634 KERNEL_LOAD_ADDRESS. 635 636config KERNEL_LOAD_ADDRESS 637 hex "Kernel load address" 638 default 0x60003000 if !MMU 639 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 640 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 641 help 642 This is the address where the kernel is loaded. 643 It is virtual address for MMUv2 configurations and physical address 644 for all other configurations. 645 646 If unsure, leave the default value here. 647 648choice 649 prompt "Relocatable vectors location" 650 default XTENSA_VECTORS_IN_TEXT 651 help 652 Choose whether relocatable vectors are merged into the kernel .text 653 or placed separately at runtime. This option does not affect 654 configurations without VECBASE register where vectors are always 655 placed at their hardware-defined locations. 656 657config XTENSA_VECTORS_IN_TEXT 658 bool "Merge relocatable vectors into kernel text" 659 depends on !MTD_XIP 660 help 661 This option puts relocatable vectors into the kernel .text section 662 with proper alignment. 663 This is a safe choice for most configurations. 664 665config XTENSA_VECTORS_SEPARATE 666 bool "Put relocatable vectors at fixed address" 667 help 668 This option puts relocatable vectors at specific virtual address. 669 Vectors are merged with the .init data in the kernel image and 670 are copied into their designated location during kernel startup. 671 Use it to put vectors into IRAM or out of FLASH on kernels with 672 XIP-aware MTD support. 673 674endchoice 675 676config VECTORS_ADDR 677 hex "Kernel vectors virtual address" 678 default 0x00000000 679 depends on XTENSA_VECTORS_SEPARATE 680 help 681 This is the virtual address of the (relocatable) vectors base. 682 It must be within KSEG if MMU is used. 683 684config XIP_DATA_ADDR 685 hex "XIP kernel data virtual address" 686 depends on XIP_KERNEL 687 default 0x00000000 688 help 689 This is the virtual address where XIP kernel data is copied. 690 It must be within KSEG if MMU is used. 691 692config PLATFORM_WANT_DEFAULT_MEM 693 def_bool n 694 695config DEFAULT_MEM_START 696 hex 697 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 698 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 699 default 0x00000000 700 help 701 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 702 in noMMU configurations. 703 704 If unsure, leave the default value here. 705 706choice 707 prompt "KSEG layout" 708 depends on MMU 709 default XTENSA_KSEG_MMU_V2 710 711config XTENSA_KSEG_MMU_V2 712 bool "MMUv2: 128MB cached + 128MB uncached" 713 help 714 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 715 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 716 without cache. 717 KSEG_PADDR must be aligned to 128MB. 718 719config XTENSA_KSEG_256M 720 bool "256MB cached + 256MB uncached" 721 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 722 help 723 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 724 with cache and to 0xc0000000 without cache. 725 KSEG_PADDR must be aligned to 256MB. 726 727config XTENSA_KSEG_512M 728 bool "512MB cached + 512MB uncached" 729 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 730 help 731 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 732 with cache and to 0xc0000000 without cache. 733 KSEG_PADDR must be aligned to 256MB. 734 735endchoice 736 737config HIGHMEM 738 bool "High Memory Support" 739 depends on MMU 740 select KMAP_LOCAL 741 help 742 Linux can use the full amount of RAM in the system by 743 default. However, the default MMUv2 setup only maps the 744 lowermost 128 MB of memory linearly to the areas starting 745 at 0xd0000000 (cached) and 0xd8000000 (uncached). 746 When there are more than 128 MB memory in the system not 747 all of it can be "permanently mapped" by the kernel. 748 The physical memory that's not permanently mapped is called 749 "high memory". 750 751 If you are compiling a kernel which will never run on a 752 machine with more than 128 MB total physical RAM, answer 753 N here. 754 755 If unsure, say Y. 756 757config FORCE_MAX_ZONEORDER 758 int "Maximum zone order" 759 default "11" 760 help 761 The kernel memory allocator divides physically contiguous memory 762 blocks into "zones", where each zone is a power of two number of 763 pages. This option selects the largest power of two that the kernel 764 keeps in the memory allocator. If you need to allocate very large 765 blocks of physically contiguous memory, then you may need to 766 increase this value. 767 768 This config option is actually maximum order plus one. For example, 769 a value of 11 means that the largest free memory block is 2^10 pages. 770 771endmenu 772 773menu "Power management options" 774 775source "kernel/power/Kconfig" 776 777endmenu 778