1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_BINFMT_FLAT if !MMU 6 select ARCH_HAS_DMA_PREP_COHERENT if MMU 7 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 9 select ARCH_HAS_DMA_SET_UNCACHED if MMU 10 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN 11 select ARCH_HAS_STRNLEN_USER 12 select ARCH_USE_MEMTEST 13 select ARCH_USE_QUEUED_RWLOCKS 14 select ARCH_USE_QUEUED_SPINLOCKS 15 select ARCH_WANT_FRAME_POINTERS 16 select ARCH_WANT_IPC_PARSE_VERSION 17 select BUILDTIME_TABLE_SORT 18 select CLONE_BACKWARDS 19 select COMMON_CLK 20 select DMA_REMAP if MMU 21 select GENERIC_ATOMIC64 22 select GENERIC_IRQ_SHOW 23 select GENERIC_PCI_IOMAP 24 select GENERIC_SCHED_CLOCK 25 select HAVE_ARCH_AUDITSYSCALL 26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 27 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 28 select HAVE_ARCH_SECCOMP_FILTER 29 select HAVE_ARCH_TRACEHOOK 30 select HAVE_DEBUG_KMEMLEAK 31 select HAVE_DMA_CONTIGUOUS 32 select HAVE_EXIT_THREAD 33 select HAVE_FUNCTION_TRACER 34 select HAVE_FUTEX_CMPXCHG if !MMU && FUTEX 35 select HAVE_HW_BREAKPOINT if PERF_EVENTS 36 select HAVE_IRQ_TIME_ACCOUNTING 37 select HAVE_PCI 38 select HAVE_PERF_EVENTS 39 select HAVE_STACKPROTECTOR 40 select HAVE_SYSCALL_TRACEPOINTS 41 select IRQ_DOMAIN 42 select MODULES_USE_ELF_RELA 43 select PERF_USE_VMALLOC 44 select SET_FS 45 select TRACE_IRQFLAGS_SUPPORT 46 select VIRT_TO_BUS 47 help 48 Xtensa processors are 32-bit RISC machines designed by Tensilica 49 primarily for embedded systems. These processors are both 50 configurable and extensible. The Linux port to the Xtensa 51 architecture supports all processor configurations and extensions, 52 with reasonable minimum requirements. The Xtensa Linux project has 53 a home page at <http://www.linux-xtensa.org/>. 54 55config GENERIC_HWEIGHT 56 def_bool y 57 58config ARCH_HAS_ILOG2_U32 59 def_bool n 60 61config ARCH_HAS_ILOG2_U64 62 def_bool n 63 64config NO_IOPORT_MAP 65 def_bool n 66 67config HZ 68 int 69 default 100 70 71config LOCKDEP_SUPPORT 72 def_bool y 73 74config STACKTRACE_SUPPORT 75 def_bool y 76 77config MMU 78 def_bool n 79 80config HAVE_XTENSA_GPIO32 81 def_bool n 82 83config KASAN_SHADOW_OFFSET 84 hex 85 default 0x6e400000 86 87config CPU_BIG_ENDIAN 88 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1) 89 90config CPU_LITTLE_ENDIAN 91 def_bool !CPU_BIG_ENDIAN 92 93menu "Processor type and features" 94 95choice 96 prompt "Xtensa Processor Configuration" 97 default XTENSA_VARIANT_FSF 98 99config XTENSA_VARIANT_FSF 100 bool "fsf - default (not generic) configuration" 101 select MMU 102 103config XTENSA_VARIANT_DC232B 104 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 105 select MMU 106 select HAVE_XTENSA_GPIO32 107 help 108 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 109 110config XTENSA_VARIANT_DC233C 111 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 112 select MMU 113 select HAVE_XTENSA_GPIO32 114 help 115 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 116 117config XTENSA_VARIANT_CUSTOM 118 bool "Custom Xtensa processor configuration" 119 select HAVE_XTENSA_GPIO32 120 help 121 Select this variant to use a custom Xtensa processor configuration. 122 You will be prompted for a processor variant CORENAME. 123endchoice 124 125config XTENSA_VARIANT_CUSTOM_NAME 126 string "Xtensa Processor Custom Core Variant Name" 127 depends on XTENSA_VARIANT_CUSTOM 128 help 129 Provide the name of a custom Xtensa processor variant. 130 This CORENAME selects arch/xtensa/variant/CORENAME. 131 Don't forget you have to select MMU if you have one. 132 133config XTENSA_VARIANT_NAME 134 string 135 default "dc232b" if XTENSA_VARIANT_DC232B 136 default "dc233c" if XTENSA_VARIANT_DC233C 137 default "fsf" if XTENSA_VARIANT_FSF 138 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 139 140config XTENSA_VARIANT_MMU 141 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 142 depends on XTENSA_VARIANT_CUSTOM 143 default y 144 select MMU 145 help 146 Build a Conventional Kernel with full MMU support, 147 ie: it supports a TLB with auto-loading, page protection. 148 149config XTENSA_VARIANT_HAVE_PERF_EVENTS 150 bool "Core variant has Performance Monitor Module" 151 depends on XTENSA_VARIANT_CUSTOM 152 default n 153 help 154 Enable if core variant has Performance Monitor Module with 155 External Registers Interface. 156 157 If unsure, say N. 158 159config XTENSA_FAKE_NMI 160 bool "Treat PMM IRQ as NMI" 161 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 162 default n 163 help 164 If PMM IRQ is the only IRQ at EXCM level it is safe to 165 treat it as NMI, which improves accuracy of profiling. 166 167 If there are other interrupts at or above PMM IRQ priority level 168 but not above the EXCM level, PMM IRQ still may be treated as NMI, 169 but only if these IRQs are not used. There will be a build warning 170 saying that this is not safe, and a bugcheck if one of these IRQs 171 actually fire. 172 173 If unsure, say N. 174 175config XTENSA_UNALIGNED_USER 176 bool "Unaligned memory access in user space" 177 help 178 The Xtensa architecture currently does not handle unaligned 179 memory accesses in hardware but through an exception handler. 180 Per default, unaligned memory accesses are disabled in user space. 181 182 Say Y here to enable unaligned memory access in user space. 183 184config HAVE_SMP 185 bool "System Supports SMP (MX)" 186 depends on XTENSA_VARIANT_CUSTOM 187 select XTENSA_MX 188 help 189 This option is used to indicate that the system-on-a-chip (SOC) 190 supports Multiprocessing. Multiprocessor support implemented above 191 the CPU core definition and currently needs to be selected manually. 192 193 Multiprocessor support is implemented with external cache and 194 interrupt controllers. 195 196 The MX interrupt distributer adds Interprocessor Interrupts 197 and causes the IRQ numbers to be increased by 4 for devices 198 like the open cores ethernet driver and the serial interface. 199 200 You still have to select "Enable SMP" to enable SMP on this SOC. 201 202config SMP 203 bool "Enable Symmetric multi-processing support" 204 depends on HAVE_SMP 205 select GENERIC_SMP_IDLE_THREAD 206 help 207 Enabled SMP Software; allows more than one CPU/CORE 208 to be activated during startup. 209 210config NR_CPUS 211 depends on SMP 212 int "Maximum number of CPUs (2-32)" 213 range 2 32 214 default "4" 215 216config HOTPLUG_CPU 217 bool "Enable CPU hotplug support" 218 depends on SMP 219 help 220 Say Y here to allow turning CPUs off and on. CPUs can be 221 controlled through /sys/devices/system/cpu. 222 223 Say N if you want to disable CPU hotplug. 224 225config FAST_SYSCALL_XTENSA 226 bool "Enable fast atomic syscalls" 227 default n 228 help 229 fast_syscall_xtensa is a syscall that can make atomic operations 230 on UP kernel when processor has no s32c1i support. 231 232 This syscall is deprecated. It may have issues when called with 233 invalid arguments. It is provided only for backwards compatibility. 234 Only enable it if your userspace software requires it. 235 236 If unsure, say N. 237 238config FAST_SYSCALL_SPILL_REGISTERS 239 bool "Enable spill registers syscall" 240 default n 241 help 242 fast_syscall_spill_registers is a syscall that spills all active 243 register windows of a calling userspace task onto its stack. 244 245 This syscall is deprecated. It may have issues when called with 246 invalid arguments. It is provided only for backwards compatibility. 247 Only enable it if your userspace software requires it. 248 249 If unsure, say N. 250 251config USER_ABI_CALL0 252 bool 253 254choice 255 prompt "Userspace ABI" 256 default USER_ABI_DEFAULT 257 help 258 Select supported userspace ABI. 259 260 If unsure, choose the default ABI. 261 262config USER_ABI_DEFAULT 263 bool "Default ABI only" 264 help 265 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 266 call0 ABI binaries may be run on such kernel, but signal delivery 267 will not work correctly for them. 268 269config USER_ABI_CALL0_ONLY 270 bool "Call0 ABI only" 271 select USER_ABI_CALL0 272 help 273 Select this option to support only call0 ABI in userspace. 274 Windowed ABI binaries will crash with a segfault caused by 275 an illegal instruction exception on the first 'entry' opcode. 276 277 Choose this option if you're planning to run only user code 278 built with call0 ABI. 279 280config USER_ABI_CALL0_PROBE 281 bool "Support both windowed and call0 ABI by probing" 282 select USER_ABI_CALL0 283 help 284 Select this option to support both windowed and call0 userspace 285 ABIs. When enabled all processes are started with PS.WOE disabled 286 and a fast user exception handler for an illegal instruction is 287 used to turn on PS.WOE bit on the first 'entry' opcode executed by 288 the userspace. 289 290 This option should be enabled for the kernel that must support 291 both call0 and windowed ABIs in userspace at the same time. 292 293 Note that Xtensa ISA does not guarantee that entry opcode will 294 raise an illegal instruction exception on cores with XEA2 when 295 PS.WOE is disabled, check whether the target core supports it. 296 297endchoice 298 299endmenu 300 301config XTENSA_CALIBRATE_CCOUNT 302 def_bool n 303 help 304 On some platforms (XT2000, for example), the CPU clock rate can 305 vary. The frequency can be determined, however, by measuring 306 against a well known, fixed frequency, such as an UART oscillator. 307 308config SERIAL_CONSOLE 309 def_bool n 310 311config PLATFORM_HAVE_XIP 312 def_bool n 313 314menu "Platform options" 315 316choice 317 prompt "Xtensa System Type" 318 default XTENSA_PLATFORM_ISS 319 320config XTENSA_PLATFORM_ISS 321 bool "ISS" 322 select XTENSA_CALIBRATE_CCOUNT 323 select SERIAL_CONSOLE 324 help 325 ISS is an acronym for Tensilica's Instruction Set Simulator. 326 327config XTENSA_PLATFORM_XT2000 328 bool "XT2000" 329 help 330 XT2000 is the name of Tensilica's feature-rich emulation platform. 331 This hardware is capable of running a full Linux distribution. 332 333config XTENSA_PLATFORM_XTFPGA 334 bool "XTFPGA" 335 select ETHOC if ETHERNET 336 select PLATFORM_WANT_DEFAULT_MEM if !MMU 337 select SERIAL_CONSOLE 338 select XTENSA_CALIBRATE_CCOUNT 339 select PLATFORM_HAVE_XIP 340 help 341 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 342 This hardware is capable of running a full Linux distribution. 343 344endchoice 345 346config PLATFORM_NR_IRQS 347 int 348 default 3 if XTENSA_PLATFORM_XT2000 349 default 0 350 351config XTENSA_CPU_CLOCK 352 int "CPU clock rate [MHz]" 353 depends on !XTENSA_CALIBRATE_CCOUNT 354 default 16 355 356config GENERIC_CALIBRATE_DELAY 357 bool "Auto calibration of the BogoMIPS value" 358 help 359 The BogoMIPS value can easily be derived from the CPU frequency. 360 361config CMDLINE_BOOL 362 bool "Default bootloader kernel arguments" 363 364config CMDLINE 365 string "Initial kernel command string" 366 depends on CMDLINE_BOOL 367 default "console=ttyS0,38400 root=/dev/ram" 368 help 369 On some architectures (EBSA110 and CATS), there is currently no way 370 for the boot loader to pass arguments to the kernel. For these 371 architectures, you should supply some command-line options at build 372 time by entering them here. As a minimum, you should specify the 373 memory size and the root device (e.g., mem=64M root=/dev/nfs). 374 375config USE_OF 376 bool "Flattened Device Tree support" 377 select OF 378 select OF_EARLY_FLATTREE 379 help 380 Include support for flattened device tree machine descriptions. 381 382config BUILTIN_DTB_SOURCE 383 string "DTB to build into the kernel image" 384 depends on OF 385 386config PARSE_BOOTPARAM 387 bool "Parse bootparam block" 388 default y 389 help 390 Parse parameters passed to the kernel from the bootloader. It may 391 be disabled if the kernel is known to run without the bootloader. 392 393 If unsure, say Y. 394 395choice 396 prompt "Semihosting interface" 397 default XTENSA_SIMCALL_ISS 398 depends on XTENSA_PLATFORM_ISS 399 help 400 Choose semihosting interface that will be used for serial port, 401 block device and networking. 402 403config XTENSA_SIMCALL_ISS 404 bool "simcall" 405 help 406 Use simcall instruction. simcall is only available on simulators, 407 it does nothing on hardware. 408 409config XTENSA_SIMCALL_GDBIO 410 bool "GDBIO" 411 help 412 Use break instruction. It is available on real hardware when GDB 413 is attached to it via JTAG. 414 415endchoice 416 417config BLK_DEV_SIMDISK 418 tristate "Host file-based simulated block device support" 419 default n 420 depends on XTENSA_PLATFORM_ISS && BLOCK 421 help 422 Create block devices that map to files in the host file system. 423 Device binding to host file may be changed at runtime via proc 424 interface provided the device is not in use. 425 426config BLK_DEV_SIMDISK_COUNT 427 int "Number of host file-based simulated block devices" 428 range 1 10 429 depends on BLK_DEV_SIMDISK 430 default 2 431 help 432 This is the default minimal number of created block devices. 433 Kernel/module parameter 'simdisk_count' may be used to change this 434 value at runtime. More file names (but no more than 10) may be 435 specified as parameters, simdisk_count grows accordingly. 436 437config SIMDISK0_FILENAME 438 string "Host filename for the first simulated device" 439 depends on BLK_DEV_SIMDISK = y 440 default "" 441 help 442 Attach a first simdisk to a host file. Conventionally, this file 443 contains a root file system. 444 445config SIMDISK1_FILENAME 446 string "Host filename for the second simulated device" 447 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 448 default "" 449 help 450 Another simulated disk in a host file for a buildroot-independent 451 storage. 452 453config XTFPGA_LCD 454 bool "Enable XTFPGA LCD driver" 455 depends on XTENSA_PLATFORM_XTFPGA 456 default n 457 help 458 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 459 progress messages there during bootup/shutdown. It may be useful 460 during board bringup. 461 462 If unsure, say N. 463 464config XTFPGA_LCD_BASE_ADDR 465 hex "XTFPGA LCD base address" 466 depends on XTFPGA_LCD 467 default "0x0d0c0000" 468 help 469 Base address of the LCD controller inside KIO region. 470 Different boards from XTFPGA family have LCD controller at different 471 addresses. Please consult prototyping user guide for your board for 472 the correct address. Wrong address here may lead to hardware lockup. 473 474config XTFPGA_LCD_8BIT_ACCESS 475 bool "Use 8-bit access to XTFPGA LCD" 476 depends on XTFPGA_LCD 477 default n 478 help 479 LCD may be connected with 4- or 8-bit interface, 8-bit access may 480 only be used with 8-bit interface. Please consult prototyping user 481 guide for your board for the correct interface width. 482 483comment "Kernel memory layout" 484 485config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 486 bool "Initialize Xtensa MMU inside the Linux kernel code" 487 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 488 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 489 help 490 Earlier version initialized the MMU in the exception vector 491 before jumping to _startup in head.S and had an advantage that 492 it was possible to place a software breakpoint at 'reset' and 493 then enter your normal kernel breakpoints once the MMU was mapped 494 to the kernel mappings (0XC0000000). 495 496 This unfortunately won't work for U-Boot and likely also won't 497 work for using KEXEC to have a hot kernel ready for doing a 498 KDUMP. 499 500 So now the MMU is initialized in head.S but it's necessary to 501 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 502 xt-gdb can't place a Software Breakpoint in the 0XD region prior 503 to mapping the MMU and after mapping even if the area of low memory 504 was mapped gdb wouldn't remove the breakpoint on hitting it as the 505 PC wouldn't match. Since Hardware Breakpoints are recommended for 506 Linux configurations it seems reasonable to just assume they exist 507 and leave this older mechanism for unfortunate souls that choose 508 not to follow Tensilica's recommendation. 509 510 Selecting this will cause U-Boot to set the KERNEL Load and Entry 511 address at 0x00003000 instead of the mapped std of 0xD0003000. 512 513 If in doubt, say Y. 514 515config XIP_KERNEL 516 bool "Kernel Execute-In-Place from ROM" 517 depends on PLATFORM_HAVE_XIP 518 help 519 Execute-In-Place allows the kernel to run from non-volatile storage 520 directly addressable by the CPU, such as NOR flash. This saves RAM 521 space since the text section of the kernel is not loaded from flash 522 to RAM. Read-write sections, such as the data section and stack, 523 are still copied to RAM. The XIP kernel is not compressed since 524 it has to run directly from flash, so it will take more space to 525 store it. The flash address used to link the kernel object files, 526 and for storing it, is configuration dependent. Therefore, if you 527 say Y here, you must know the proper physical address where to 528 store the kernel image depending on your own flash memory usage. 529 530 Also note that the make target becomes "make xipImage" rather than 531 "make Image" or "make uImage". The final kernel binary to put in 532 ROM memory will be arch/xtensa/boot/xipImage. 533 534 If unsure, say N. 535 536config MEMMAP_CACHEATTR 537 hex "Cache attributes for the memory address space" 538 depends on !MMU 539 default 0x22222222 540 help 541 These cache attributes are set up for noMMU systems. Each hex digit 542 specifies cache attributes for the corresponding 512MB memory 543 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 544 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 545 546 Cache attribute values are specific for the MMU type. 547 For region protection MMUs: 548 1: WT cached, 549 2: cache bypass, 550 4: WB cached, 551 f: illegal. 552 For full MMU: 553 bit 0: executable, 554 bit 1: writable, 555 bits 2..3: 556 0: cache bypass, 557 1: WB cache, 558 2: WT cache, 559 3: special (c and e are illegal, f is reserved). 560 For MPU: 561 0: illegal, 562 1: WB cache, 563 2: WB, no-write-allocate cache, 564 3: WT cache, 565 4: cache bypass. 566 567config KSEG_PADDR 568 hex "Physical address of the KSEG mapping" 569 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 570 default 0x00000000 571 help 572 This is the physical address where KSEG is mapped. Please refer to 573 the chosen KSEG layout help for the required address alignment. 574 Unpacked kernel image (including vectors) must be located completely 575 within KSEG. 576 Physical memory below this address is not available to linux. 577 578 If unsure, leave the default value here. 579 580config KERNEL_VIRTUAL_ADDRESS 581 hex "Kernel virtual address" 582 depends on MMU && XIP_KERNEL 583 default 0xd0003000 584 help 585 This is the virtual address where the XIP kernel is mapped. 586 XIP kernel may be mapped into KSEG or KIO region, virtual address 587 provided here must match kernel load address provided in 588 KERNEL_LOAD_ADDRESS. 589 590config KERNEL_LOAD_ADDRESS 591 hex "Kernel load address" 592 default 0x60003000 if !MMU 593 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 594 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 595 help 596 This is the address where the kernel is loaded. 597 It is virtual address for MMUv2 configurations and physical address 598 for all other configurations. 599 600 If unsure, leave the default value here. 601 602choice 603 prompt "Relocatable vectors location" 604 default XTENSA_VECTORS_IN_TEXT 605 help 606 Choose whether relocatable vectors are merged into the kernel .text 607 or placed separately at runtime. This option does not affect 608 configurations without VECBASE register where vectors are always 609 placed at their hardware-defined locations. 610 611config XTENSA_VECTORS_IN_TEXT 612 bool "Merge relocatable vectors into kernel text" 613 depends on !MTD_XIP 614 help 615 This option puts relocatable vectors into the kernel .text section 616 with proper alignment. 617 This is a safe choice for most configurations. 618 619config XTENSA_VECTORS_SEPARATE 620 bool "Put relocatable vectors at fixed address" 621 help 622 This option puts relocatable vectors at specific virtual address. 623 Vectors are merged with the .init data in the kernel image and 624 are copied into their designated location during kernel startup. 625 Use it to put vectors into IRAM or out of FLASH on kernels with 626 XIP-aware MTD support. 627 628endchoice 629 630config VECTORS_ADDR 631 hex "Kernel vectors virtual address" 632 default 0x00000000 633 depends on XTENSA_VECTORS_SEPARATE 634 help 635 This is the virtual address of the (relocatable) vectors base. 636 It must be within KSEG if MMU is used. 637 638config XIP_DATA_ADDR 639 hex "XIP kernel data virtual address" 640 depends on XIP_KERNEL 641 default 0x00000000 642 help 643 This is the virtual address where XIP kernel data is copied. 644 It must be within KSEG if MMU is used. 645 646config PLATFORM_WANT_DEFAULT_MEM 647 def_bool n 648 649config DEFAULT_MEM_START 650 hex 651 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 652 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 653 default 0x00000000 654 help 655 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 656 in noMMU configurations. 657 658 If unsure, leave the default value here. 659 660choice 661 prompt "KSEG layout" 662 depends on MMU 663 default XTENSA_KSEG_MMU_V2 664 665config XTENSA_KSEG_MMU_V2 666 bool "MMUv2: 128MB cached + 128MB uncached" 667 help 668 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 669 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 670 without cache. 671 KSEG_PADDR must be aligned to 128MB. 672 673config XTENSA_KSEG_256M 674 bool "256MB cached + 256MB uncached" 675 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 676 help 677 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 678 with cache and to 0xc0000000 without cache. 679 KSEG_PADDR must be aligned to 256MB. 680 681config XTENSA_KSEG_512M 682 bool "512MB cached + 512MB uncached" 683 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 684 help 685 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 686 with cache and to 0xc0000000 without cache. 687 KSEG_PADDR must be aligned to 256MB. 688 689endchoice 690 691config HIGHMEM 692 bool "High Memory Support" 693 depends on MMU 694 select KMAP_LOCAL 695 help 696 Linux can use the full amount of RAM in the system by 697 default. However, the default MMUv2 setup only maps the 698 lowermost 128 MB of memory linearly to the areas starting 699 at 0xd0000000 (cached) and 0xd8000000 (uncached). 700 When there are more than 128 MB memory in the system not 701 all of it can be "permanently mapped" by the kernel. 702 The physical memory that's not permanently mapped is called 703 "high memory". 704 705 If you are compiling a kernel which will never run on a 706 machine with more than 128 MB total physical RAM, answer 707 N here. 708 709 If unsure, say Y. 710 711config FORCE_MAX_ZONEORDER 712 int "Maximum zone order" 713 default "11" 714 help 715 The kernel memory allocator divides physically contiguous memory 716 blocks into "zones", where each zone is a power of two number of 717 pages. This option selects the largest power of two that the kernel 718 keeps in the memory allocator. If you need to allocate very large 719 blocks of physically contiguous memory, then you may need to 720 increase this value. 721 722 This config option is actually maximum order plus one. For example, 723 a value of 11 means that the largest free memory block is 2^10 pages. 724 725endmenu 726 727menu "Power management options" 728 729source "kernel/power/Kconfig" 730 731endmenu 732