1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_BINFMT_FLAT if !MMU 6 select ARCH_HAS_DMA_PREP_COHERENT if MMU 7 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 9 select ARCH_HAS_DMA_SET_UNCACHED if MMU 10 select ARCH_USE_MEMTEST 11 select ARCH_USE_QUEUED_RWLOCKS 12 select ARCH_USE_QUEUED_SPINLOCKS 13 select ARCH_WANT_FRAME_POINTERS 14 select ARCH_WANT_IPC_PARSE_VERSION 15 select BUILDTIME_TABLE_SORT 16 select CLONE_BACKWARDS 17 select COMMON_CLK 18 select DMA_REMAP if MMU 19 select GENERIC_ATOMIC64 20 select GENERIC_IRQ_SHOW 21 select GENERIC_PCI_IOMAP 22 select GENERIC_SCHED_CLOCK 23 select GENERIC_STRNCPY_FROM_USER if KASAN 24 select HAVE_ARCH_AUDITSYSCALL 25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 26 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 27 select HAVE_ARCH_SECCOMP_FILTER 28 select HAVE_ARCH_TRACEHOOK 29 select HAVE_DEBUG_KMEMLEAK 30 select HAVE_DMA_CONTIGUOUS 31 select HAVE_EXIT_THREAD 32 select HAVE_FUNCTION_TRACER 33 select HAVE_FUTEX_CMPXCHG if !MMU 34 select HAVE_HW_BREAKPOINT if PERF_EVENTS 35 select HAVE_IRQ_TIME_ACCOUNTING 36 select HAVE_PCI 37 select HAVE_PERF_EVENTS 38 select HAVE_STACKPROTECTOR 39 select HAVE_SYSCALL_TRACEPOINTS 40 select IRQ_DOMAIN 41 select MODULES_USE_ELF_RELA 42 select PERF_USE_VMALLOC 43 select SET_FS 44 select VIRT_TO_BUS 45 help 46 Xtensa processors are 32-bit RISC machines designed by Tensilica 47 primarily for embedded systems. These processors are both 48 configurable and extensible. The Linux port to the Xtensa 49 architecture supports all processor configurations and extensions, 50 with reasonable minimum requirements. The Xtensa Linux project has 51 a home page at <http://www.linux-xtensa.org/>. 52 53config GENERIC_HWEIGHT 54 def_bool y 55 56config ARCH_HAS_ILOG2_U32 57 def_bool n 58 59config ARCH_HAS_ILOG2_U64 60 def_bool n 61 62config NO_IOPORT_MAP 63 def_bool n 64 65config HZ 66 int 67 default 100 68 69config LOCKDEP_SUPPORT 70 def_bool y 71 72config STACKTRACE_SUPPORT 73 def_bool y 74 75config TRACE_IRQFLAGS_SUPPORT 76 def_bool y 77 78config MMU 79 def_bool n 80 81config HAVE_XTENSA_GPIO32 82 def_bool n 83 84config KASAN_SHADOW_OFFSET 85 hex 86 default 0x6e400000 87 88config CPU_BIG_ENDIAN 89 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1) 90 91config CPU_LITTLE_ENDIAN 92 def_bool !CPU_BIG_ENDIAN 93 94menu "Processor type and features" 95 96choice 97 prompt "Xtensa Processor Configuration" 98 default XTENSA_VARIANT_FSF 99 100config XTENSA_VARIANT_FSF 101 bool "fsf - default (not generic) configuration" 102 select MMU 103 104config XTENSA_VARIANT_DC232B 105 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 106 select MMU 107 select HAVE_XTENSA_GPIO32 108 help 109 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 110 111config XTENSA_VARIANT_DC233C 112 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 113 select MMU 114 select HAVE_XTENSA_GPIO32 115 help 116 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 117 118config XTENSA_VARIANT_CUSTOM 119 bool "Custom Xtensa processor configuration" 120 select HAVE_XTENSA_GPIO32 121 help 122 Select this variant to use a custom Xtensa processor configuration. 123 You will be prompted for a processor variant CORENAME. 124endchoice 125 126config XTENSA_VARIANT_CUSTOM_NAME 127 string "Xtensa Processor Custom Core Variant Name" 128 depends on XTENSA_VARIANT_CUSTOM 129 help 130 Provide the name of a custom Xtensa processor variant. 131 This CORENAME selects arch/xtensa/variant/CORENAME. 132 Don't forget you have to select MMU if you have one. 133 134config XTENSA_VARIANT_NAME 135 string 136 default "dc232b" if XTENSA_VARIANT_DC232B 137 default "dc233c" if XTENSA_VARIANT_DC233C 138 default "fsf" if XTENSA_VARIANT_FSF 139 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 140 141config XTENSA_VARIANT_MMU 142 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 143 depends on XTENSA_VARIANT_CUSTOM 144 default y 145 select MMU 146 help 147 Build a Conventional Kernel with full MMU support, 148 ie: it supports a TLB with auto-loading, page protection. 149 150config XTENSA_VARIANT_HAVE_PERF_EVENTS 151 bool "Core variant has Performance Monitor Module" 152 depends on XTENSA_VARIANT_CUSTOM 153 default n 154 help 155 Enable if core variant has Performance Monitor Module with 156 External Registers Interface. 157 158 If unsure, say N. 159 160config XTENSA_FAKE_NMI 161 bool "Treat PMM IRQ as NMI" 162 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 163 default n 164 help 165 If PMM IRQ is the only IRQ at EXCM level it is safe to 166 treat it as NMI, which improves accuracy of profiling. 167 168 If there are other interrupts at or above PMM IRQ priority level 169 but not above the EXCM level, PMM IRQ still may be treated as NMI, 170 but only if these IRQs are not used. There will be a build warning 171 saying that this is not safe, and a bugcheck if one of these IRQs 172 actually fire. 173 174 If unsure, say N. 175 176config XTENSA_UNALIGNED_USER 177 bool "Unaligned memory access in user space" 178 help 179 The Xtensa architecture currently does not handle unaligned 180 memory accesses in hardware but through an exception handler. 181 Per default, unaligned memory accesses are disabled in user space. 182 183 Say Y here to enable unaligned memory access in user space. 184 185config HAVE_SMP 186 bool "System Supports SMP (MX)" 187 depends on XTENSA_VARIANT_CUSTOM 188 select XTENSA_MX 189 help 190 This option is used to indicate that the system-on-a-chip (SOC) 191 supports Multiprocessing. Multiprocessor support implemented above 192 the CPU core definition and currently needs to be selected manually. 193 194 Multiprocessor support is implemented with external cache and 195 interrupt controllers. 196 197 The MX interrupt distributer adds Interprocessor Interrupts 198 and causes the IRQ numbers to be increased by 4 for devices 199 like the open cores ethernet driver and the serial interface. 200 201 You still have to select "Enable SMP" to enable SMP on this SOC. 202 203config SMP 204 bool "Enable Symmetric multi-processing support" 205 depends on HAVE_SMP 206 select GENERIC_SMP_IDLE_THREAD 207 help 208 Enabled SMP Software; allows more than one CPU/CORE 209 to be activated during startup. 210 211config NR_CPUS 212 depends on SMP 213 int "Maximum number of CPUs (2-32)" 214 range 2 32 215 default "4" 216 217config HOTPLUG_CPU 218 bool "Enable CPU hotplug support" 219 depends on SMP 220 help 221 Say Y here to allow turning CPUs off and on. CPUs can be 222 controlled through /sys/devices/system/cpu. 223 224 Say N if you want to disable CPU hotplug. 225 226config FAST_SYSCALL_XTENSA 227 bool "Enable fast atomic syscalls" 228 default n 229 help 230 fast_syscall_xtensa is a syscall that can make atomic operations 231 on UP kernel when processor has no s32c1i support. 232 233 This syscall is deprecated. It may have issues when called with 234 invalid arguments. It is provided only for backwards compatibility. 235 Only enable it if your userspace software requires it. 236 237 If unsure, say N. 238 239config FAST_SYSCALL_SPILL_REGISTERS 240 bool "Enable spill registers syscall" 241 default n 242 help 243 fast_syscall_spill_registers is a syscall that spills all active 244 register windows of a calling userspace task onto its stack. 245 246 This syscall is deprecated. It may have issues when called with 247 invalid arguments. It is provided only for backwards compatibility. 248 Only enable it if your userspace software requires it. 249 250 If unsure, say N. 251 252config USER_ABI_CALL0 253 bool 254 255choice 256 prompt "Userspace ABI" 257 default USER_ABI_DEFAULT 258 help 259 Select supported userspace ABI. 260 261 If unsure, choose the default ABI. 262 263config USER_ABI_DEFAULT 264 bool "Default ABI only" 265 help 266 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 267 call0 ABI binaries may be run on such kernel, but signal delivery 268 will not work correctly for them. 269 270config USER_ABI_CALL0_ONLY 271 bool "Call0 ABI only" 272 select USER_ABI_CALL0 273 help 274 Select this option to support only call0 ABI in userspace. 275 Windowed ABI binaries will crash with a segfault caused by 276 an illegal instruction exception on the first 'entry' opcode. 277 278 Choose this option if you're planning to run only user code 279 built with call0 ABI. 280 281config USER_ABI_CALL0_PROBE 282 bool "Support both windowed and call0 ABI by probing" 283 select USER_ABI_CALL0 284 help 285 Select this option to support both windowed and call0 userspace 286 ABIs. When enabled all processes are started with PS.WOE disabled 287 and a fast user exception handler for an illegal instruction is 288 used to turn on PS.WOE bit on the first 'entry' opcode executed by 289 the userspace. 290 291 This option should be enabled for the kernel that must support 292 both call0 and windowed ABIs in userspace at the same time. 293 294 Note that Xtensa ISA does not guarantee that entry opcode will 295 raise an illegal instruction exception on cores with XEA2 when 296 PS.WOE is disabled, check whether the target core supports it. 297 298endchoice 299 300endmenu 301 302config XTENSA_CALIBRATE_CCOUNT 303 def_bool n 304 help 305 On some platforms (XT2000, for example), the CPU clock rate can 306 vary. The frequency can be determined, however, by measuring 307 against a well known, fixed frequency, such as an UART oscillator. 308 309config SERIAL_CONSOLE 310 def_bool n 311 312config PLATFORM_HAVE_XIP 313 def_bool n 314 315menu "Platform options" 316 317choice 318 prompt "Xtensa System Type" 319 default XTENSA_PLATFORM_ISS 320 321config XTENSA_PLATFORM_ISS 322 bool "ISS" 323 select XTENSA_CALIBRATE_CCOUNT 324 select SERIAL_CONSOLE 325 help 326 ISS is an acronym for Tensilica's Instruction Set Simulator. 327 328config XTENSA_PLATFORM_XT2000 329 bool "XT2000" 330 select HAVE_IDE 331 help 332 XT2000 is the name of Tensilica's feature-rich emulation platform. 333 This hardware is capable of running a full Linux distribution. 334 335config XTENSA_PLATFORM_XTFPGA 336 bool "XTFPGA" 337 select ETHOC if ETHERNET 338 select PLATFORM_WANT_DEFAULT_MEM if !MMU 339 select SERIAL_CONSOLE 340 select XTENSA_CALIBRATE_CCOUNT 341 select PLATFORM_HAVE_XIP 342 help 343 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 344 This hardware is capable of running a full Linux distribution. 345 346endchoice 347 348config PLATFORM_NR_IRQS 349 int 350 default 3 if XTENSA_PLATFORM_XT2000 351 default 0 352 353config XTENSA_CPU_CLOCK 354 int "CPU clock rate [MHz]" 355 depends on !XTENSA_CALIBRATE_CCOUNT 356 default 16 357 358config GENERIC_CALIBRATE_DELAY 359 bool "Auto calibration of the BogoMIPS value" 360 help 361 The BogoMIPS value can easily be derived from the CPU frequency. 362 363config CMDLINE_BOOL 364 bool "Default bootloader kernel arguments" 365 366config CMDLINE 367 string "Initial kernel command string" 368 depends on CMDLINE_BOOL 369 default "console=ttyS0,38400 root=/dev/ram" 370 help 371 On some architectures (EBSA110 and CATS), there is currently no way 372 for the boot loader to pass arguments to the kernel. For these 373 architectures, you should supply some command-line options at build 374 time by entering them here. As a minimum, you should specify the 375 memory size and the root device (e.g., mem=64M root=/dev/nfs). 376 377config USE_OF 378 bool "Flattened Device Tree support" 379 select OF 380 select OF_EARLY_FLATTREE 381 help 382 Include support for flattened device tree machine descriptions. 383 384config BUILTIN_DTB_SOURCE 385 string "DTB to build into the kernel image" 386 depends on OF 387 388config PARSE_BOOTPARAM 389 bool "Parse bootparam block" 390 default y 391 help 392 Parse parameters passed to the kernel from the bootloader. It may 393 be disabled if the kernel is known to run without the bootloader. 394 395 If unsure, say Y. 396 397choice 398 prompt "Semihosting interface" 399 default XTENSA_SIMCALL_ISS 400 depends on XTENSA_PLATFORM_ISS 401 help 402 Choose semihosting interface that will be used for serial port, 403 block device and networking. 404 405config XTENSA_SIMCALL_ISS 406 bool "simcall" 407 help 408 Use simcall instruction. simcall is only available on simulators, 409 it does nothing on hardware. 410 411config XTENSA_SIMCALL_GDBIO 412 bool "GDBIO" 413 help 414 Use break instruction. It is available on real hardware when GDB 415 is attached to it via JTAG. 416 417endchoice 418 419config BLK_DEV_SIMDISK 420 tristate "Host file-based simulated block device support" 421 default n 422 depends on XTENSA_PLATFORM_ISS && BLOCK 423 help 424 Create block devices that map to files in the host file system. 425 Device binding to host file may be changed at runtime via proc 426 interface provided the device is not in use. 427 428config BLK_DEV_SIMDISK_COUNT 429 int "Number of host file-based simulated block devices" 430 range 1 10 431 depends on BLK_DEV_SIMDISK 432 default 2 433 help 434 This is the default minimal number of created block devices. 435 Kernel/module parameter 'simdisk_count' may be used to change this 436 value at runtime. More file names (but no more than 10) may be 437 specified as parameters, simdisk_count grows accordingly. 438 439config SIMDISK0_FILENAME 440 string "Host filename for the first simulated device" 441 depends on BLK_DEV_SIMDISK = y 442 default "" 443 help 444 Attach a first simdisk to a host file. Conventionally, this file 445 contains a root file system. 446 447config SIMDISK1_FILENAME 448 string "Host filename for the second simulated device" 449 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 450 default "" 451 help 452 Another simulated disk in a host file for a buildroot-independent 453 storage. 454 455config XTFPGA_LCD 456 bool "Enable XTFPGA LCD driver" 457 depends on XTENSA_PLATFORM_XTFPGA 458 default n 459 help 460 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 461 progress messages there during bootup/shutdown. It may be useful 462 during board bringup. 463 464 If unsure, say N. 465 466config XTFPGA_LCD_BASE_ADDR 467 hex "XTFPGA LCD base address" 468 depends on XTFPGA_LCD 469 default "0x0d0c0000" 470 help 471 Base address of the LCD controller inside KIO region. 472 Different boards from XTFPGA family have LCD controller at different 473 addresses. Please consult prototyping user guide for your board for 474 the correct address. Wrong address here may lead to hardware lockup. 475 476config XTFPGA_LCD_8BIT_ACCESS 477 bool "Use 8-bit access to XTFPGA LCD" 478 depends on XTFPGA_LCD 479 default n 480 help 481 LCD may be connected with 4- or 8-bit interface, 8-bit access may 482 only be used with 8-bit interface. Please consult prototyping user 483 guide for your board for the correct interface width. 484 485comment "Kernel memory layout" 486 487config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 488 bool "Initialize Xtensa MMU inside the Linux kernel code" 489 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 490 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 491 help 492 Earlier version initialized the MMU in the exception vector 493 before jumping to _startup in head.S and had an advantage that 494 it was possible to place a software breakpoint at 'reset' and 495 then enter your normal kernel breakpoints once the MMU was mapped 496 to the kernel mappings (0XC0000000). 497 498 This unfortunately won't work for U-Boot and likely also won't 499 work for using KEXEC to have a hot kernel ready for doing a 500 KDUMP. 501 502 So now the MMU is initialized in head.S but it's necessary to 503 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 504 xt-gdb can't place a Software Breakpoint in the 0XD region prior 505 to mapping the MMU and after mapping even if the area of low memory 506 was mapped gdb wouldn't remove the breakpoint on hitting it as the 507 PC wouldn't match. Since Hardware Breakpoints are recommended for 508 Linux configurations it seems reasonable to just assume they exist 509 and leave this older mechanism for unfortunate souls that choose 510 not to follow Tensilica's recommendation. 511 512 Selecting this will cause U-Boot to set the KERNEL Load and Entry 513 address at 0x00003000 instead of the mapped std of 0xD0003000. 514 515 If in doubt, say Y. 516 517config XIP_KERNEL 518 bool "Kernel Execute-In-Place from ROM" 519 depends on PLATFORM_HAVE_XIP 520 help 521 Execute-In-Place allows the kernel to run from non-volatile storage 522 directly addressable by the CPU, such as NOR flash. This saves RAM 523 space since the text section of the kernel is not loaded from flash 524 to RAM. Read-write sections, such as the data section and stack, 525 are still copied to RAM. The XIP kernel is not compressed since 526 it has to run directly from flash, so it will take more space to 527 store it. The flash address used to link the kernel object files, 528 and for storing it, is configuration dependent. Therefore, if you 529 say Y here, you must know the proper physical address where to 530 store the kernel image depending on your own flash memory usage. 531 532 Also note that the make target becomes "make xipImage" rather than 533 "make Image" or "make uImage". The final kernel binary to put in 534 ROM memory will be arch/xtensa/boot/xipImage. 535 536 If unsure, say N. 537 538config MEMMAP_CACHEATTR 539 hex "Cache attributes for the memory address space" 540 depends on !MMU 541 default 0x22222222 542 help 543 These cache attributes are set up for noMMU systems. Each hex digit 544 specifies cache attributes for the corresponding 512MB memory 545 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 546 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 547 548 Cache attribute values are specific for the MMU type. 549 For region protection MMUs: 550 1: WT cached, 551 2: cache bypass, 552 4: WB cached, 553 f: illegal. 554 For full MMU: 555 bit 0: executable, 556 bit 1: writable, 557 bits 2..3: 558 0: cache bypass, 559 1: WB cache, 560 2: WT cache, 561 3: special (c and e are illegal, f is reserved). 562 For MPU: 563 0: illegal, 564 1: WB cache, 565 2: WB, no-write-allocate cache, 566 3: WT cache, 567 4: cache bypass. 568 569config KSEG_PADDR 570 hex "Physical address of the KSEG mapping" 571 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 572 default 0x00000000 573 help 574 This is the physical address where KSEG is mapped. Please refer to 575 the chosen KSEG layout help for the required address alignment. 576 Unpacked kernel image (including vectors) must be located completely 577 within KSEG. 578 Physical memory below this address is not available to linux. 579 580 If unsure, leave the default value here. 581 582config KERNEL_VIRTUAL_ADDRESS 583 hex "Kernel virtual address" 584 depends on MMU && XIP_KERNEL 585 default 0xd0003000 586 help 587 This is the virtual address where the XIP kernel is mapped. 588 XIP kernel may be mapped into KSEG or KIO region, virtual address 589 provided here must match kernel load address provided in 590 KERNEL_LOAD_ADDRESS. 591 592config KERNEL_LOAD_ADDRESS 593 hex "Kernel load address" 594 default 0x60003000 if !MMU 595 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 596 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 597 help 598 This is the address where the kernel is loaded. 599 It is virtual address for MMUv2 configurations and physical address 600 for all other configurations. 601 602 If unsure, leave the default value here. 603 604choice 605 prompt "Relocatable vectors location" 606 default XTENSA_VECTORS_IN_TEXT 607 help 608 Choose whether relocatable vectors are merged into the kernel .text 609 or placed separately at runtime. This option does not affect 610 configurations without VECBASE register where vectors are always 611 placed at their hardware-defined locations. 612 613config XTENSA_VECTORS_IN_TEXT 614 bool "Merge relocatable vectors into kernel text" 615 depends on !MTD_XIP 616 help 617 This option puts relocatable vectors into the kernel .text section 618 with proper alignment. 619 This is a safe choice for most configurations. 620 621config XTENSA_VECTORS_SEPARATE 622 bool "Put relocatable vectors at fixed address" 623 help 624 This option puts relocatable vectors at specific virtual address. 625 Vectors are merged with the .init data in the kernel image and 626 are copied into their designated location during kernel startup. 627 Use it to put vectors into IRAM or out of FLASH on kernels with 628 XIP-aware MTD support. 629 630endchoice 631 632config VECTORS_ADDR 633 hex "Kernel vectors virtual address" 634 default 0x00000000 635 depends on XTENSA_VECTORS_SEPARATE 636 help 637 This is the virtual address of the (relocatable) vectors base. 638 It must be within KSEG if MMU is used. 639 640config XIP_DATA_ADDR 641 hex "XIP kernel data virtual address" 642 depends on XIP_KERNEL 643 default 0x00000000 644 help 645 This is the virtual address where XIP kernel data is copied. 646 It must be within KSEG if MMU is used. 647 648config PLATFORM_WANT_DEFAULT_MEM 649 def_bool n 650 651config DEFAULT_MEM_START 652 hex 653 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 654 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 655 default 0x00000000 656 help 657 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 658 in noMMU configurations. 659 660 If unsure, leave the default value here. 661 662choice 663 prompt "KSEG layout" 664 depends on MMU 665 default XTENSA_KSEG_MMU_V2 666 667config XTENSA_KSEG_MMU_V2 668 bool "MMUv2: 128MB cached + 128MB uncached" 669 help 670 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 671 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 672 without cache. 673 KSEG_PADDR must be aligned to 128MB. 674 675config XTENSA_KSEG_256M 676 bool "256MB cached + 256MB uncached" 677 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 678 help 679 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 680 with cache and to 0xc0000000 without cache. 681 KSEG_PADDR must be aligned to 256MB. 682 683config XTENSA_KSEG_512M 684 bool "512MB cached + 512MB uncached" 685 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 686 help 687 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 688 with cache and to 0xc0000000 without cache. 689 KSEG_PADDR must be aligned to 256MB. 690 691endchoice 692 693config HIGHMEM 694 bool "High Memory Support" 695 depends on MMU 696 select KMAP_LOCAL 697 help 698 Linux can use the full amount of RAM in the system by 699 default. However, the default MMUv2 setup only maps the 700 lowermost 128 MB of memory linearly to the areas starting 701 at 0xd0000000 (cached) and 0xd8000000 (uncached). 702 When there are more than 128 MB memory in the system not 703 all of it can be "permanently mapped" by the kernel. 704 The physical memory that's not permanently mapped is called 705 "high memory". 706 707 If you are compiling a kernel which will never run on a 708 machine with more than 128 MB total physical RAM, answer 709 N here. 710 711 If unsure, say Y. 712 713config FORCE_MAX_ZONEORDER 714 int "Maximum zone order" 715 default "11" 716 help 717 The kernel memory allocator divides physically contiguous memory 718 blocks into "zones", where each zone is a power of two number of 719 pages. This option selects the largest power of two that the kernel 720 keeps in the memory allocator. If you need to allocate very large 721 blocks of physically contiguous memory, then you may need to 722 increase this value. 723 724 This config option is actually maximum order plus one. For example, 725 a value of 11 means that the largest free memory block is 2^10 pages. 726 727endmenu 728 729menu "Power management options" 730 731source "kernel/power/Kconfig" 732 733endmenu 734