1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_BINFMT_FLAT if !MMU 6 select ARCH_HAS_SYNC_DMA_FOR_CPU 7 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 8 select ARCH_USE_QUEUED_RWLOCKS 9 select ARCH_USE_QUEUED_SPINLOCKS 10 select ARCH_WANT_FRAME_POINTERS 11 select ARCH_WANT_IPC_PARSE_VERSION 12 select BUILDTIME_EXTABLE_SORT 13 select CLONE_BACKWARDS 14 select COMMON_CLK 15 select DMA_REMAP if MMU 16 select GENERIC_ATOMIC64 17 select GENERIC_CLOCKEVENTS 18 select GENERIC_IRQ_SHOW 19 select GENERIC_PCI_IOMAP 20 select GENERIC_SCHED_CLOCK 21 select GENERIC_STRNCPY_FROM_USER if KASAN 22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 23 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 24 select HAVE_ARCH_TRACEHOOK 25 select HAVE_DEBUG_KMEMLEAK 26 select HAVE_DMA_CONTIGUOUS 27 select HAVE_EXIT_THREAD 28 select HAVE_FUNCTION_TRACER 29 select HAVE_FUTEX_CMPXCHG if !MMU 30 select HAVE_HW_BREAKPOINT if PERF_EVENTS 31 select HAVE_IRQ_TIME_ACCOUNTING 32 select HAVE_OPROFILE 33 select HAVE_PCI 34 select HAVE_PERF_EVENTS 35 select HAVE_STACKPROTECTOR 36 select HAVE_SYSCALL_TRACEPOINTS 37 select IRQ_DOMAIN 38 select MODULES_USE_ELF_RELA 39 select PERF_USE_VMALLOC 40 select VIRT_TO_BUS 41 help 42 Xtensa processors are 32-bit RISC machines designed by Tensilica 43 primarily for embedded systems. These processors are both 44 configurable and extensible. The Linux port to the Xtensa 45 architecture supports all processor configurations and extensions, 46 with reasonable minimum requirements. The Xtensa Linux project has 47 a home page at <http://www.linux-xtensa.org/>. 48 49config GENERIC_HWEIGHT 50 def_bool y 51 52config ARCH_HAS_ILOG2_U32 53 def_bool n 54 55config ARCH_HAS_ILOG2_U64 56 def_bool n 57 58config NO_IOPORT_MAP 59 def_bool n 60 61config HZ 62 int 63 default 100 64 65config LOCKDEP_SUPPORT 66 def_bool y 67 68config STACKTRACE_SUPPORT 69 def_bool y 70 71config TRACE_IRQFLAGS_SUPPORT 72 def_bool y 73 74config MMU 75 def_bool n 76 77config HAVE_XTENSA_GPIO32 78 def_bool n 79 80config KASAN_SHADOW_OFFSET 81 hex 82 default 0x6e400000 83 84menu "Processor type and features" 85 86choice 87 prompt "Xtensa Processor Configuration" 88 default XTENSA_VARIANT_FSF 89 90config XTENSA_VARIANT_FSF 91 bool "fsf - default (not generic) configuration" 92 select MMU 93 94config XTENSA_VARIANT_DC232B 95 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 96 select MMU 97 select HAVE_XTENSA_GPIO32 98 help 99 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 100 101config XTENSA_VARIANT_DC233C 102 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 103 select MMU 104 select HAVE_XTENSA_GPIO32 105 help 106 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 107 108config XTENSA_VARIANT_CUSTOM 109 bool "Custom Xtensa processor configuration" 110 select HAVE_XTENSA_GPIO32 111 help 112 Select this variant to use a custom Xtensa processor configuration. 113 You will be prompted for a processor variant CORENAME. 114endchoice 115 116config XTENSA_VARIANT_CUSTOM_NAME 117 string "Xtensa Processor Custom Core Variant Name" 118 depends on XTENSA_VARIANT_CUSTOM 119 help 120 Provide the name of a custom Xtensa processor variant. 121 This CORENAME selects arch/xtensa/variant/CORENAME. 122 Dont forget you have to select MMU if you have one. 123 124config XTENSA_VARIANT_NAME 125 string 126 default "dc232b" if XTENSA_VARIANT_DC232B 127 default "dc233c" if XTENSA_VARIANT_DC233C 128 default "fsf" if XTENSA_VARIANT_FSF 129 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 130 131config XTENSA_VARIANT_MMU 132 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 133 depends on XTENSA_VARIANT_CUSTOM 134 default y 135 select MMU 136 help 137 Build a Conventional Kernel with full MMU support, 138 ie: it supports a TLB with auto-loading, page protection. 139 140config XTENSA_VARIANT_HAVE_PERF_EVENTS 141 bool "Core variant has Performance Monitor Module" 142 depends on XTENSA_VARIANT_CUSTOM 143 default n 144 help 145 Enable if core variant has Performance Monitor Module with 146 External Registers Interface. 147 148 If unsure, say N. 149 150config XTENSA_FAKE_NMI 151 bool "Treat PMM IRQ as NMI" 152 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 153 default n 154 help 155 If PMM IRQ is the only IRQ at EXCM level it is safe to 156 treat it as NMI, which improves accuracy of profiling. 157 158 If there are other interrupts at or above PMM IRQ priority level 159 but not above the EXCM level, PMM IRQ still may be treated as NMI, 160 but only if these IRQs are not used. There will be a build warning 161 saying that this is not safe, and a bugcheck if one of these IRQs 162 actually fire. 163 164 If unsure, say N. 165 166config XTENSA_UNALIGNED_USER 167 bool "Unaligned memory access in user space" 168 help 169 The Xtensa architecture currently does not handle unaligned 170 memory accesses in hardware but through an exception handler. 171 Per default, unaligned memory accesses are disabled in user space. 172 173 Say Y here to enable unaligned memory access in user space. 174 175config HAVE_SMP 176 bool "System Supports SMP (MX)" 177 depends on XTENSA_VARIANT_CUSTOM 178 select XTENSA_MX 179 help 180 This option is use to indicate that the system-on-a-chip (SOC) 181 supports Multiprocessing. Multiprocessor support implemented above 182 the CPU core definition and currently needs to be selected manually. 183 184 Multiprocessor support in implemented with external cache and 185 interrupt controllers. 186 187 The MX interrupt distributer adds Interprocessor Interrupts 188 and causes the IRQ numbers to be increased by 4 for devices 189 like the open cores ethernet driver and the serial interface. 190 191 You still have to select "Enable SMP" to enable SMP on this SOC. 192 193config SMP 194 bool "Enable Symmetric multi-processing support" 195 depends on HAVE_SMP 196 select GENERIC_SMP_IDLE_THREAD 197 help 198 Enabled SMP Software; allows more than one CPU/CORE 199 to be activated during startup. 200 201config NR_CPUS 202 depends on SMP 203 int "Maximum number of CPUs (2-32)" 204 range 2 32 205 default "4" 206 207config HOTPLUG_CPU 208 bool "Enable CPU hotplug support" 209 depends on SMP 210 help 211 Say Y here to allow turning CPUs off and on. CPUs can be 212 controlled through /sys/devices/system/cpu. 213 214 Say N if you want to disable CPU hotplug. 215 216config FAST_SYSCALL_XTENSA 217 bool "Enable fast atomic syscalls" 218 default n 219 help 220 fast_syscall_xtensa is a syscall that can make atomic operations 221 on UP kernel when processor has no s32c1i support. 222 223 This syscall is deprecated. It may have issues when called with 224 invalid arguments. It is provided only for backwards compatibility. 225 Only enable it if your userspace software requires it. 226 227 If unsure, say N. 228 229config FAST_SYSCALL_SPILL_REGISTERS 230 bool "Enable spill registers syscall" 231 default n 232 help 233 fast_syscall_spill_registers is a syscall that spills all active 234 register windows of a calling userspace task onto its stack. 235 236 This syscall is deprecated. It may have issues when called with 237 invalid arguments. It is provided only for backwards compatibility. 238 Only enable it if your userspace software requires it. 239 240 If unsure, say N. 241 242config USER_ABI_CALL0 243 bool 244 245choice 246 prompt "Userspace ABI" 247 default USER_ABI_DEFAULT 248 help 249 Select supported userspace ABI. 250 251 If unsure, choose the default ABI. 252 253config USER_ABI_DEFAULT 254 bool "Default ABI only" 255 help 256 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 257 call0 ABI binaries may be run on such kernel, but signal delivery 258 will not work correctly for them. 259 260config USER_ABI_CALL0_ONLY 261 bool "Call0 ABI only" 262 select USER_ABI_CALL0 263 help 264 Select this option to support only call0 ABI in userspace. 265 Windowed ABI binaries will crash with a segfault caused by 266 an illegal instruction exception on the first 'entry' opcode. 267 268 Choose this option if you're planning to run only user code 269 built with call0 ABI. 270 271config USER_ABI_CALL0_PROBE 272 bool "Support both windowed and call0 ABI by probing" 273 select USER_ABI_CALL0 274 help 275 Select this option to support both windowed and call0 userspace 276 ABIs. When enabled all processes are started with PS.WOE disabled 277 and a fast user exception handler for an illegal instruction is 278 used to turn on PS.WOE bit on the first 'entry' opcode executed by 279 the userspace. 280 281 This option should be enabled for the kernel that must support 282 both call0 and windowed ABIs in userspace at the same time. 283 284 Note that Xtensa ISA does not guarantee that entry opcode will 285 raise an illegal instruction exception on cores with XEA2 when 286 PS.WOE is disabled, check whether the target core supports it. 287 288endchoice 289 290endmenu 291 292config XTENSA_CALIBRATE_CCOUNT 293 def_bool n 294 help 295 On some platforms (XT2000, for example), the CPU clock rate can 296 vary. The frequency can be determined, however, by measuring 297 against a well known, fixed frequency, such as an UART oscillator. 298 299config SERIAL_CONSOLE 300 def_bool n 301 302config PLATFORM_HAVE_XIP 303 def_bool n 304 305menu "Platform options" 306 307choice 308 prompt "Xtensa System Type" 309 default XTENSA_PLATFORM_ISS 310 311config XTENSA_PLATFORM_ISS 312 bool "ISS" 313 select XTENSA_CALIBRATE_CCOUNT 314 select SERIAL_CONSOLE 315 help 316 ISS is an acronym for Tensilica's Instruction Set Simulator. 317 318config XTENSA_PLATFORM_XT2000 319 bool "XT2000" 320 select HAVE_IDE 321 help 322 XT2000 is the name of Tensilica's feature-rich emulation platform. 323 This hardware is capable of running a full Linux distribution. 324 325config XTENSA_PLATFORM_XTFPGA 326 bool "XTFPGA" 327 select ETHOC if ETHERNET 328 select PLATFORM_WANT_DEFAULT_MEM if !MMU 329 select SERIAL_CONSOLE 330 select XTENSA_CALIBRATE_CCOUNT 331 select PLATFORM_HAVE_XIP 332 help 333 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 334 This hardware is capable of running a full Linux distribution. 335 336endchoice 337 338config PLATFORM_NR_IRQS 339 int 340 default 3 if XTENSA_PLATFORM_XT2000 341 default 0 342 343config XTENSA_CPU_CLOCK 344 int "CPU clock rate [MHz]" 345 depends on !XTENSA_CALIBRATE_CCOUNT 346 default 16 347 348config GENERIC_CALIBRATE_DELAY 349 bool "Auto calibration of the BogoMIPS value" 350 help 351 The BogoMIPS value can easily be derived from the CPU frequency. 352 353config CMDLINE_BOOL 354 bool "Default bootloader kernel arguments" 355 356config CMDLINE 357 string "Initial kernel command string" 358 depends on CMDLINE_BOOL 359 default "console=ttyS0,38400 root=/dev/ram" 360 help 361 On some architectures (EBSA110 and CATS), there is currently no way 362 for the boot loader to pass arguments to the kernel. For these 363 architectures, you should supply some command-line options at build 364 time by entering them here. As a minimum, you should specify the 365 memory size and the root device (e.g., mem=64M root=/dev/nfs). 366 367config USE_OF 368 bool "Flattened Device Tree support" 369 select OF 370 select OF_EARLY_FLATTREE 371 help 372 Include support for flattened device tree machine descriptions. 373 374config BUILTIN_DTB_SOURCE 375 string "DTB to build into the kernel image" 376 depends on OF 377 378config PARSE_BOOTPARAM 379 bool "Parse bootparam block" 380 default y 381 help 382 Parse parameters passed to the kernel from the bootloader. It may 383 be disabled if the kernel is known to run without the bootloader. 384 385 If unsure, say Y. 386 387config BLK_DEV_SIMDISK 388 tristate "Host file-based simulated block device support" 389 default n 390 depends on XTENSA_PLATFORM_ISS && BLOCK 391 help 392 Create block devices that map to files in the host file system. 393 Device binding to host file may be changed at runtime via proc 394 interface provided the device is not in use. 395 396config BLK_DEV_SIMDISK_COUNT 397 int "Number of host file-based simulated block devices" 398 range 1 10 399 depends on BLK_DEV_SIMDISK 400 default 2 401 help 402 This is the default minimal number of created block devices. 403 Kernel/module parameter 'simdisk_count' may be used to change this 404 value at runtime. More file names (but no more than 10) may be 405 specified as parameters, simdisk_count grows accordingly. 406 407config SIMDISK0_FILENAME 408 string "Host filename for the first simulated device" 409 depends on BLK_DEV_SIMDISK = y 410 default "" 411 help 412 Attach a first simdisk to a host file. Conventionally, this file 413 contains a root file system. 414 415config SIMDISK1_FILENAME 416 string "Host filename for the second simulated device" 417 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 418 default "" 419 help 420 Another simulated disk in a host file for a buildroot-independent 421 storage. 422 423config XTFPGA_LCD 424 bool "Enable XTFPGA LCD driver" 425 depends on XTENSA_PLATFORM_XTFPGA 426 default n 427 help 428 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 429 progress messages there during bootup/shutdown. It may be useful 430 during board bringup. 431 432 If unsure, say N. 433 434config XTFPGA_LCD_BASE_ADDR 435 hex "XTFPGA LCD base address" 436 depends on XTFPGA_LCD 437 default "0x0d0c0000" 438 help 439 Base address of the LCD controller inside KIO region. 440 Different boards from XTFPGA family have LCD controller at different 441 addresses. Please consult prototyping user guide for your board for 442 the correct address. Wrong address here may lead to hardware lockup. 443 444config XTFPGA_LCD_8BIT_ACCESS 445 bool "Use 8-bit access to XTFPGA LCD" 446 depends on XTFPGA_LCD 447 default n 448 help 449 LCD may be connected with 4- or 8-bit interface, 8-bit access may 450 only be used with 8-bit interface. Please consult prototyping user 451 guide for your board for the correct interface width. 452 453comment "Kernel memory layout" 454 455config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 456 bool "Initialize Xtensa MMU inside the Linux kernel code" 457 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 458 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 459 help 460 Earlier version initialized the MMU in the exception vector 461 before jumping to _startup in head.S and had an advantage that 462 it was possible to place a software breakpoint at 'reset' and 463 then enter your normal kernel breakpoints once the MMU was mapped 464 to the kernel mappings (0XC0000000). 465 466 This unfortunately won't work for U-Boot and likely also wont 467 work for using KEXEC to have a hot kernel ready for doing a 468 KDUMP. 469 470 So now the MMU is initialized in head.S but it's necessary to 471 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 472 xt-gdb can't place a Software Breakpoint in the 0XD region prior 473 to mapping the MMU and after mapping even if the area of low memory 474 was mapped gdb wouldn't remove the breakpoint on hitting it as the 475 PC wouldn't match. Since Hardware Breakpoints are recommended for 476 Linux configurations it seems reasonable to just assume they exist 477 and leave this older mechanism for unfortunate souls that choose 478 not to follow Tensilica's recommendation. 479 480 Selecting this will cause U-Boot to set the KERNEL Load and Entry 481 address at 0x00003000 instead of the mapped std of 0xD0003000. 482 483 If in doubt, say Y. 484 485config XIP_KERNEL 486 bool "Kernel Execute-In-Place from ROM" 487 depends on PLATFORM_HAVE_XIP 488 help 489 Execute-In-Place allows the kernel to run from non-volatile storage 490 directly addressable by the CPU, such as NOR flash. This saves RAM 491 space since the text section of the kernel is not loaded from flash 492 to RAM. Read-write sections, such as the data section and stack, 493 are still copied to RAM. The XIP kernel is not compressed since 494 it has to run directly from flash, so it will take more space to 495 store it. The flash address used to link the kernel object files, 496 and for storing it, is configuration dependent. Therefore, if you 497 say Y here, you must know the proper physical address where to 498 store the kernel image depending on your own flash memory usage. 499 500 Also note that the make target becomes "make xipImage" rather than 501 "make Image" or "make uImage". The final kernel binary to put in 502 ROM memory will be arch/xtensa/boot/xipImage. 503 504 If unsure, say N. 505 506config MEMMAP_CACHEATTR 507 hex "Cache attributes for the memory address space" 508 depends on !MMU 509 default 0x22222222 510 help 511 These cache attributes are set up for noMMU systems. Each hex digit 512 specifies cache attributes for the corresponding 512MB memory 513 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 514 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 515 516 Cache attribute values are specific for the MMU type. 517 For region protection MMUs: 518 1: WT cached, 519 2: cache bypass, 520 4: WB cached, 521 f: illegal. 522 For ful MMU: 523 bit 0: executable, 524 bit 1: writable, 525 bits 2..3: 526 0: cache bypass, 527 1: WB cache, 528 2: WT cache, 529 3: special (c and e are illegal, f is reserved). 530 For MPU: 531 0: illegal, 532 1: WB cache, 533 2: WB, no-write-allocate cache, 534 3: WT cache, 535 4: cache bypass. 536 537config KSEG_PADDR 538 hex "Physical address of the KSEG mapping" 539 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 540 default 0x00000000 541 help 542 This is the physical address where KSEG is mapped. Please refer to 543 the chosen KSEG layout help for the required address alignment. 544 Unpacked kernel image (including vectors) must be located completely 545 within KSEG. 546 Physical memory below this address is not available to linux. 547 548 If unsure, leave the default value here. 549 550config KERNEL_VIRTUAL_ADDRESS 551 hex "Kernel virtual address" 552 depends on MMU && XIP_KERNEL 553 default 0xd0003000 554 help 555 This is the virtual address where the XIP kernel is mapped. 556 XIP kernel may be mapped into KSEG or KIO region, virtual address 557 provided here must match kernel load address provided in 558 KERNEL_LOAD_ADDRESS. 559 560config KERNEL_LOAD_ADDRESS 561 hex "Kernel load address" 562 default 0x60003000 if !MMU 563 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 564 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 565 help 566 This is the address where the kernel is loaded. 567 It is virtual address for MMUv2 configurations and physical address 568 for all other configurations. 569 570 If unsure, leave the default value here. 571 572config VECTORS_OFFSET 573 hex "Kernel vectors offset" 574 default 0x00003000 575 depends on !XIP_KERNEL 576 help 577 This is the offset of the kernel image from the relocatable vectors 578 base. 579 580 If unsure, leave the default value here. 581 582config XIP_DATA_ADDR 583 hex "XIP kernel data virtual address" 584 depends on XIP_KERNEL 585 default 0x00000000 586 help 587 This is the virtual address where XIP kernel data is copied. 588 It must be within KSEG if MMU is used. 589 590config PLATFORM_WANT_DEFAULT_MEM 591 def_bool n 592 593config DEFAULT_MEM_START 594 hex 595 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 596 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 597 default 0x00000000 598 help 599 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 600 in noMMU configurations. 601 602 If unsure, leave the default value here. 603 604choice 605 prompt "KSEG layout" 606 depends on MMU 607 default XTENSA_KSEG_MMU_V2 608 609config XTENSA_KSEG_MMU_V2 610 bool "MMUv2: 128MB cached + 128MB uncached" 611 help 612 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 613 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 614 without cache. 615 KSEG_PADDR must be aligned to 128MB. 616 617config XTENSA_KSEG_256M 618 bool "256MB cached + 256MB uncached" 619 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 620 help 621 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 622 with cache and to 0xc0000000 without cache. 623 KSEG_PADDR must be aligned to 256MB. 624 625config XTENSA_KSEG_512M 626 bool "512MB cached + 512MB uncached" 627 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 628 help 629 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 630 with cache and to 0xc0000000 without cache. 631 KSEG_PADDR must be aligned to 256MB. 632 633endchoice 634 635config HIGHMEM 636 bool "High Memory Support" 637 depends on MMU 638 help 639 Linux can use the full amount of RAM in the system by 640 default. However, the default MMUv2 setup only maps the 641 lowermost 128 MB of memory linearly to the areas starting 642 at 0xd0000000 (cached) and 0xd8000000 (uncached). 643 When there are more than 128 MB memory in the system not 644 all of it can be "permanently mapped" by the kernel. 645 The physical memory that's not permanently mapped is called 646 "high memory". 647 648 If you are compiling a kernel which will never run on a 649 machine with more than 128 MB total physical RAM, answer 650 N here. 651 652 If unsure, say Y. 653 654config FORCE_MAX_ZONEORDER 655 int "Maximum zone order" 656 default "11" 657 help 658 The kernel memory allocator divides physically contiguous memory 659 blocks into "zones", where each zone is a power of two number of 660 pages. This option selects the largest power of two that the kernel 661 keeps in the memory allocator. If you need to allocate very large 662 blocks of physically contiguous memory, then you may need to 663 increase this value. 664 665 This config option is actually maximum order plus one. For example, 666 a value of 11 means that the largest free memory block is 2^10 pages. 667 668endmenu 669 670menu "Power management options" 671 672source "kernel/power/Kconfig" 673 674endmenu 675