1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_BINFMT_FLAT if !MMU 6 select ARCH_HAS_DMA_PREP_COHERENT if MMU 7 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 9 select ARCH_HAS_DMA_SET_UNCACHED if MMU 10 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN 11 select ARCH_HAS_STRNLEN_USER 12 select ARCH_USE_MEMTEST 13 select ARCH_USE_QUEUED_RWLOCKS 14 select ARCH_USE_QUEUED_SPINLOCKS 15 select ARCH_WANT_FRAME_POINTERS 16 select ARCH_WANT_IPC_PARSE_VERSION 17 select BUILDTIME_TABLE_SORT 18 select CLONE_BACKWARDS 19 select COMMON_CLK 20 select DMA_REMAP if MMU 21 select GENERIC_ATOMIC64 22 select GENERIC_IRQ_SHOW 23 select GENERIC_PCI_IOMAP 24 select GENERIC_SCHED_CLOCK 25 select HAVE_ARCH_AUDITSYSCALL 26 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 27 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 28 select HAVE_ARCH_SECCOMP_FILTER 29 select HAVE_ARCH_TRACEHOOK 30 select HAVE_DEBUG_KMEMLEAK 31 select HAVE_DMA_CONTIGUOUS 32 select HAVE_EXIT_THREAD 33 select HAVE_FUNCTION_TRACER 34 select HAVE_HW_BREAKPOINT if PERF_EVENTS 35 select HAVE_IRQ_TIME_ACCOUNTING 36 select HAVE_PCI 37 select HAVE_PERF_EVENTS 38 select HAVE_STACKPROTECTOR 39 select HAVE_SYSCALL_TRACEPOINTS 40 select IRQ_DOMAIN 41 select MODULES_USE_ELF_RELA 42 select PERF_USE_VMALLOC 43 select SET_FS 44 select TRACE_IRQFLAGS_SUPPORT 45 select VIRT_TO_BUS 46 help 47 Xtensa processors are 32-bit RISC machines designed by Tensilica 48 primarily for embedded systems. These processors are both 49 configurable and extensible. The Linux port to the Xtensa 50 architecture supports all processor configurations and extensions, 51 with reasonable minimum requirements. The Xtensa Linux project has 52 a home page at <http://www.linux-xtensa.org/>. 53 54config GENERIC_HWEIGHT 55 def_bool y 56 57config ARCH_HAS_ILOG2_U32 58 def_bool n 59 60config ARCH_HAS_ILOG2_U64 61 def_bool n 62 63config NO_IOPORT_MAP 64 def_bool n 65 66config HZ 67 int 68 default 100 69 70config LOCKDEP_SUPPORT 71 def_bool y 72 73config STACKTRACE_SUPPORT 74 def_bool y 75 76config MMU 77 def_bool n 78 79config HAVE_XTENSA_GPIO32 80 def_bool n 81 82config KASAN_SHADOW_OFFSET 83 hex 84 default 0x6e400000 85 86config CPU_BIG_ENDIAN 87 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1) 88 89config CPU_LITTLE_ENDIAN 90 def_bool !CPU_BIG_ENDIAN 91 92menu "Processor type and features" 93 94choice 95 prompt "Xtensa Processor Configuration" 96 default XTENSA_VARIANT_FSF 97 98config XTENSA_VARIANT_FSF 99 bool "fsf - default (not generic) configuration" 100 select MMU 101 102config XTENSA_VARIANT_DC232B 103 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 104 select MMU 105 select HAVE_XTENSA_GPIO32 106 help 107 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 108 109config XTENSA_VARIANT_DC233C 110 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 111 select MMU 112 select HAVE_XTENSA_GPIO32 113 help 114 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 115 116config XTENSA_VARIANT_CUSTOM 117 bool "Custom Xtensa processor configuration" 118 select HAVE_XTENSA_GPIO32 119 help 120 Select this variant to use a custom Xtensa processor configuration. 121 You will be prompted for a processor variant CORENAME. 122endchoice 123 124config XTENSA_VARIANT_CUSTOM_NAME 125 string "Xtensa Processor Custom Core Variant Name" 126 depends on XTENSA_VARIANT_CUSTOM 127 help 128 Provide the name of a custom Xtensa processor variant. 129 This CORENAME selects arch/xtensa/variant/CORENAME. 130 Don't forget you have to select MMU if you have one. 131 132config XTENSA_VARIANT_NAME 133 string 134 default "dc232b" if XTENSA_VARIANT_DC232B 135 default "dc233c" if XTENSA_VARIANT_DC233C 136 default "fsf" if XTENSA_VARIANT_FSF 137 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 138 139config XTENSA_VARIANT_MMU 140 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 141 depends on XTENSA_VARIANT_CUSTOM 142 default y 143 select MMU 144 help 145 Build a Conventional Kernel with full MMU support, 146 ie: it supports a TLB with auto-loading, page protection. 147 148config XTENSA_VARIANT_HAVE_PERF_EVENTS 149 bool "Core variant has Performance Monitor Module" 150 depends on XTENSA_VARIANT_CUSTOM 151 default n 152 help 153 Enable if core variant has Performance Monitor Module with 154 External Registers Interface. 155 156 If unsure, say N. 157 158config XTENSA_FAKE_NMI 159 bool "Treat PMM IRQ as NMI" 160 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 161 default n 162 help 163 If PMM IRQ is the only IRQ at EXCM level it is safe to 164 treat it as NMI, which improves accuracy of profiling. 165 166 If there are other interrupts at or above PMM IRQ priority level 167 but not above the EXCM level, PMM IRQ still may be treated as NMI, 168 but only if these IRQs are not used. There will be a build warning 169 saying that this is not safe, and a bugcheck if one of these IRQs 170 actually fire. 171 172 If unsure, say N. 173 174config XTENSA_UNALIGNED_USER 175 bool "Unaligned memory access in user space" 176 help 177 The Xtensa architecture currently does not handle unaligned 178 memory accesses in hardware but through an exception handler. 179 Per default, unaligned memory accesses are disabled in user space. 180 181 Say Y here to enable unaligned memory access in user space. 182 183config HAVE_SMP 184 bool "System Supports SMP (MX)" 185 depends on XTENSA_VARIANT_CUSTOM 186 select XTENSA_MX 187 help 188 This option is used to indicate that the system-on-a-chip (SOC) 189 supports Multiprocessing. Multiprocessor support implemented above 190 the CPU core definition and currently needs to be selected manually. 191 192 Multiprocessor support is implemented with external cache and 193 interrupt controllers. 194 195 The MX interrupt distributer adds Interprocessor Interrupts 196 and causes the IRQ numbers to be increased by 4 for devices 197 like the open cores ethernet driver and the serial interface. 198 199 You still have to select "Enable SMP" to enable SMP on this SOC. 200 201config SMP 202 bool "Enable Symmetric multi-processing support" 203 depends on HAVE_SMP 204 select GENERIC_SMP_IDLE_THREAD 205 help 206 Enabled SMP Software; allows more than one CPU/CORE 207 to be activated during startup. 208 209config NR_CPUS 210 depends on SMP 211 int "Maximum number of CPUs (2-32)" 212 range 2 32 213 default "4" 214 215config HOTPLUG_CPU 216 bool "Enable CPU hotplug support" 217 depends on SMP 218 help 219 Say Y here to allow turning CPUs off and on. CPUs can be 220 controlled through /sys/devices/system/cpu. 221 222 Say N if you want to disable CPU hotplug. 223 224config FAST_SYSCALL_XTENSA 225 bool "Enable fast atomic syscalls" 226 default n 227 help 228 fast_syscall_xtensa is a syscall that can make atomic operations 229 on UP kernel when processor has no s32c1i support. 230 231 This syscall is deprecated. It may have issues when called with 232 invalid arguments. It is provided only for backwards compatibility. 233 Only enable it if your userspace software requires it. 234 235 If unsure, say N. 236 237config FAST_SYSCALL_SPILL_REGISTERS 238 bool "Enable spill registers syscall" 239 default n 240 help 241 fast_syscall_spill_registers is a syscall that spills all active 242 register windows of a calling userspace task onto its stack. 243 244 This syscall is deprecated. It may have issues when called with 245 invalid arguments. It is provided only for backwards compatibility. 246 Only enable it if your userspace software requires it. 247 248 If unsure, say N. 249 250config USER_ABI_CALL0 251 bool 252 253choice 254 prompt "Userspace ABI" 255 default USER_ABI_DEFAULT 256 help 257 Select supported userspace ABI. 258 259 If unsure, choose the default ABI. 260 261config USER_ABI_DEFAULT 262 bool "Default ABI only" 263 help 264 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 265 call0 ABI binaries may be run on such kernel, but signal delivery 266 will not work correctly for them. 267 268config USER_ABI_CALL0_ONLY 269 bool "Call0 ABI only" 270 select USER_ABI_CALL0 271 help 272 Select this option to support only call0 ABI in userspace. 273 Windowed ABI binaries will crash with a segfault caused by 274 an illegal instruction exception on the first 'entry' opcode. 275 276 Choose this option if you're planning to run only user code 277 built with call0 ABI. 278 279config USER_ABI_CALL0_PROBE 280 bool "Support both windowed and call0 ABI by probing" 281 select USER_ABI_CALL0 282 help 283 Select this option to support both windowed and call0 userspace 284 ABIs. When enabled all processes are started with PS.WOE disabled 285 and a fast user exception handler for an illegal instruction is 286 used to turn on PS.WOE bit on the first 'entry' opcode executed by 287 the userspace. 288 289 This option should be enabled for the kernel that must support 290 both call0 and windowed ABIs in userspace at the same time. 291 292 Note that Xtensa ISA does not guarantee that entry opcode will 293 raise an illegal instruction exception on cores with XEA2 when 294 PS.WOE is disabled, check whether the target core supports it. 295 296endchoice 297 298endmenu 299 300config XTENSA_CALIBRATE_CCOUNT 301 def_bool n 302 help 303 On some platforms (XT2000, for example), the CPU clock rate can 304 vary. The frequency can be determined, however, by measuring 305 against a well known, fixed frequency, such as an UART oscillator. 306 307config SERIAL_CONSOLE 308 def_bool n 309 310config PLATFORM_HAVE_XIP 311 def_bool n 312 313menu "Platform options" 314 315choice 316 prompt "Xtensa System Type" 317 default XTENSA_PLATFORM_ISS 318 319config XTENSA_PLATFORM_ISS 320 bool "ISS" 321 select XTENSA_CALIBRATE_CCOUNT 322 select SERIAL_CONSOLE 323 help 324 ISS is an acronym for Tensilica's Instruction Set Simulator. 325 326config XTENSA_PLATFORM_XT2000 327 bool "XT2000" 328 help 329 XT2000 is the name of Tensilica's feature-rich emulation platform. 330 This hardware is capable of running a full Linux distribution. 331 332config XTENSA_PLATFORM_XTFPGA 333 bool "XTFPGA" 334 select ETHOC if ETHERNET 335 select PLATFORM_WANT_DEFAULT_MEM if !MMU 336 select SERIAL_CONSOLE 337 select XTENSA_CALIBRATE_CCOUNT 338 select PLATFORM_HAVE_XIP 339 help 340 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 341 This hardware is capable of running a full Linux distribution. 342 343endchoice 344 345config PLATFORM_NR_IRQS 346 int 347 default 3 if XTENSA_PLATFORM_XT2000 348 default 0 349 350config XTENSA_CPU_CLOCK 351 int "CPU clock rate [MHz]" 352 depends on !XTENSA_CALIBRATE_CCOUNT 353 default 16 354 355config GENERIC_CALIBRATE_DELAY 356 bool "Auto calibration of the BogoMIPS value" 357 help 358 The BogoMIPS value can easily be derived from the CPU frequency. 359 360config CMDLINE_BOOL 361 bool "Default bootloader kernel arguments" 362 363config CMDLINE 364 string "Initial kernel command string" 365 depends on CMDLINE_BOOL 366 default "console=ttyS0,38400 root=/dev/ram" 367 help 368 On some architectures (EBSA110 and CATS), there is currently no way 369 for the boot loader to pass arguments to the kernel. For these 370 architectures, you should supply some command-line options at build 371 time by entering them here. As a minimum, you should specify the 372 memory size and the root device (e.g., mem=64M root=/dev/nfs). 373 374config USE_OF 375 bool "Flattened Device Tree support" 376 select OF 377 select OF_EARLY_FLATTREE 378 help 379 Include support for flattened device tree machine descriptions. 380 381config BUILTIN_DTB_SOURCE 382 string "DTB to build into the kernel image" 383 depends on OF 384 385config PARSE_BOOTPARAM 386 bool "Parse bootparam block" 387 default y 388 help 389 Parse parameters passed to the kernel from the bootloader. It may 390 be disabled if the kernel is known to run without the bootloader. 391 392 If unsure, say Y. 393 394choice 395 prompt "Semihosting interface" 396 default XTENSA_SIMCALL_ISS 397 depends on XTENSA_PLATFORM_ISS 398 help 399 Choose semihosting interface that will be used for serial port, 400 block device and networking. 401 402config XTENSA_SIMCALL_ISS 403 bool "simcall" 404 help 405 Use simcall instruction. simcall is only available on simulators, 406 it does nothing on hardware. 407 408config XTENSA_SIMCALL_GDBIO 409 bool "GDBIO" 410 help 411 Use break instruction. It is available on real hardware when GDB 412 is attached to it via JTAG. 413 414endchoice 415 416config BLK_DEV_SIMDISK 417 tristate "Host file-based simulated block device support" 418 default n 419 depends on XTENSA_PLATFORM_ISS && BLOCK 420 help 421 Create block devices that map to files in the host file system. 422 Device binding to host file may be changed at runtime via proc 423 interface provided the device is not in use. 424 425config BLK_DEV_SIMDISK_COUNT 426 int "Number of host file-based simulated block devices" 427 range 1 10 428 depends on BLK_DEV_SIMDISK 429 default 2 430 help 431 This is the default minimal number of created block devices. 432 Kernel/module parameter 'simdisk_count' may be used to change this 433 value at runtime. More file names (but no more than 10) may be 434 specified as parameters, simdisk_count grows accordingly. 435 436config SIMDISK0_FILENAME 437 string "Host filename for the first simulated device" 438 depends on BLK_DEV_SIMDISK = y 439 default "" 440 help 441 Attach a first simdisk to a host file. Conventionally, this file 442 contains a root file system. 443 444config SIMDISK1_FILENAME 445 string "Host filename for the second simulated device" 446 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 447 default "" 448 help 449 Another simulated disk in a host file for a buildroot-independent 450 storage. 451 452config XTFPGA_LCD 453 bool "Enable XTFPGA LCD driver" 454 depends on XTENSA_PLATFORM_XTFPGA 455 default n 456 help 457 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 458 progress messages there during bootup/shutdown. It may be useful 459 during board bringup. 460 461 If unsure, say N. 462 463config XTFPGA_LCD_BASE_ADDR 464 hex "XTFPGA LCD base address" 465 depends on XTFPGA_LCD 466 default "0x0d0c0000" 467 help 468 Base address of the LCD controller inside KIO region. 469 Different boards from XTFPGA family have LCD controller at different 470 addresses. Please consult prototyping user guide for your board for 471 the correct address. Wrong address here may lead to hardware lockup. 472 473config XTFPGA_LCD_8BIT_ACCESS 474 bool "Use 8-bit access to XTFPGA LCD" 475 depends on XTFPGA_LCD 476 default n 477 help 478 LCD may be connected with 4- or 8-bit interface, 8-bit access may 479 only be used with 8-bit interface. Please consult prototyping user 480 guide for your board for the correct interface width. 481 482comment "Kernel memory layout" 483 484config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 485 bool "Initialize Xtensa MMU inside the Linux kernel code" 486 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 487 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 488 help 489 Earlier version initialized the MMU in the exception vector 490 before jumping to _startup in head.S and had an advantage that 491 it was possible to place a software breakpoint at 'reset' and 492 then enter your normal kernel breakpoints once the MMU was mapped 493 to the kernel mappings (0XC0000000). 494 495 This unfortunately won't work for U-Boot and likely also won't 496 work for using KEXEC to have a hot kernel ready for doing a 497 KDUMP. 498 499 So now the MMU is initialized in head.S but it's necessary to 500 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 501 xt-gdb can't place a Software Breakpoint in the 0XD region prior 502 to mapping the MMU and after mapping even if the area of low memory 503 was mapped gdb wouldn't remove the breakpoint on hitting it as the 504 PC wouldn't match. Since Hardware Breakpoints are recommended for 505 Linux configurations it seems reasonable to just assume they exist 506 and leave this older mechanism for unfortunate souls that choose 507 not to follow Tensilica's recommendation. 508 509 Selecting this will cause U-Boot to set the KERNEL Load and Entry 510 address at 0x00003000 instead of the mapped std of 0xD0003000. 511 512 If in doubt, say Y. 513 514config XIP_KERNEL 515 bool "Kernel Execute-In-Place from ROM" 516 depends on PLATFORM_HAVE_XIP 517 help 518 Execute-In-Place allows the kernel to run from non-volatile storage 519 directly addressable by the CPU, such as NOR flash. This saves RAM 520 space since the text section of the kernel is not loaded from flash 521 to RAM. Read-write sections, such as the data section and stack, 522 are still copied to RAM. The XIP kernel is not compressed since 523 it has to run directly from flash, so it will take more space to 524 store it. The flash address used to link the kernel object files, 525 and for storing it, is configuration dependent. Therefore, if you 526 say Y here, you must know the proper physical address where to 527 store the kernel image depending on your own flash memory usage. 528 529 Also note that the make target becomes "make xipImage" rather than 530 "make Image" or "make uImage". The final kernel binary to put in 531 ROM memory will be arch/xtensa/boot/xipImage. 532 533 If unsure, say N. 534 535config MEMMAP_CACHEATTR 536 hex "Cache attributes for the memory address space" 537 depends on !MMU 538 default 0x22222222 539 help 540 These cache attributes are set up for noMMU systems. Each hex digit 541 specifies cache attributes for the corresponding 512MB memory 542 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 543 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 544 545 Cache attribute values are specific for the MMU type. 546 For region protection MMUs: 547 1: WT cached, 548 2: cache bypass, 549 4: WB cached, 550 f: illegal. 551 For full MMU: 552 bit 0: executable, 553 bit 1: writable, 554 bits 2..3: 555 0: cache bypass, 556 1: WB cache, 557 2: WT cache, 558 3: special (c and e are illegal, f is reserved). 559 For MPU: 560 0: illegal, 561 1: WB cache, 562 2: WB, no-write-allocate cache, 563 3: WT cache, 564 4: cache bypass. 565 566config KSEG_PADDR 567 hex "Physical address of the KSEG mapping" 568 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 569 default 0x00000000 570 help 571 This is the physical address where KSEG is mapped. Please refer to 572 the chosen KSEG layout help for the required address alignment. 573 Unpacked kernel image (including vectors) must be located completely 574 within KSEG. 575 Physical memory below this address is not available to linux. 576 577 If unsure, leave the default value here. 578 579config KERNEL_VIRTUAL_ADDRESS 580 hex "Kernel virtual address" 581 depends on MMU && XIP_KERNEL 582 default 0xd0003000 583 help 584 This is the virtual address where the XIP kernel is mapped. 585 XIP kernel may be mapped into KSEG or KIO region, virtual address 586 provided here must match kernel load address provided in 587 KERNEL_LOAD_ADDRESS. 588 589config KERNEL_LOAD_ADDRESS 590 hex "Kernel load address" 591 default 0x60003000 if !MMU 592 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 593 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 594 help 595 This is the address where the kernel is loaded. 596 It is virtual address for MMUv2 configurations and physical address 597 for all other configurations. 598 599 If unsure, leave the default value here. 600 601choice 602 prompt "Relocatable vectors location" 603 default XTENSA_VECTORS_IN_TEXT 604 help 605 Choose whether relocatable vectors are merged into the kernel .text 606 or placed separately at runtime. This option does not affect 607 configurations without VECBASE register where vectors are always 608 placed at their hardware-defined locations. 609 610config XTENSA_VECTORS_IN_TEXT 611 bool "Merge relocatable vectors into kernel text" 612 depends on !MTD_XIP 613 help 614 This option puts relocatable vectors into the kernel .text section 615 with proper alignment. 616 This is a safe choice for most configurations. 617 618config XTENSA_VECTORS_SEPARATE 619 bool "Put relocatable vectors at fixed address" 620 help 621 This option puts relocatable vectors at specific virtual address. 622 Vectors are merged with the .init data in the kernel image and 623 are copied into their designated location during kernel startup. 624 Use it to put vectors into IRAM or out of FLASH on kernels with 625 XIP-aware MTD support. 626 627endchoice 628 629config VECTORS_ADDR 630 hex "Kernel vectors virtual address" 631 default 0x00000000 632 depends on XTENSA_VECTORS_SEPARATE 633 help 634 This is the virtual address of the (relocatable) vectors base. 635 It must be within KSEG if MMU is used. 636 637config XIP_DATA_ADDR 638 hex "XIP kernel data virtual address" 639 depends on XIP_KERNEL 640 default 0x00000000 641 help 642 This is the virtual address where XIP kernel data is copied. 643 It must be within KSEG if MMU is used. 644 645config PLATFORM_WANT_DEFAULT_MEM 646 def_bool n 647 648config DEFAULT_MEM_START 649 hex 650 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 651 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 652 default 0x00000000 653 help 654 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 655 in noMMU configurations. 656 657 If unsure, leave the default value here. 658 659choice 660 prompt "KSEG layout" 661 depends on MMU 662 default XTENSA_KSEG_MMU_V2 663 664config XTENSA_KSEG_MMU_V2 665 bool "MMUv2: 128MB cached + 128MB uncached" 666 help 667 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 668 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 669 without cache. 670 KSEG_PADDR must be aligned to 128MB. 671 672config XTENSA_KSEG_256M 673 bool "256MB cached + 256MB uncached" 674 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 675 help 676 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 677 with cache and to 0xc0000000 without cache. 678 KSEG_PADDR must be aligned to 256MB. 679 680config XTENSA_KSEG_512M 681 bool "512MB cached + 512MB uncached" 682 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 683 help 684 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 685 with cache and to 0xc0000000 without cache. 686 KSEG_PADDR must be aligned to 256MB. 687 688endchoice 689 690config HIGHMEM 691 bool "High Memory Support" 692 depends on MMU 693 select KMAP_LOCAL 694 help 695 Linux can use the full amount of RAM in the system by 696 default. However, the default MMUv2 setup only maps the 697 lowermost 128 MB of memory linearly to the areas starting 698 at 0xd0000000 (cached) and 0xd8000000 (uncached). 699 When there are more than 128 MB memory in the system not 700 all of it can be "permanently mapped" by the kernel. 701 The physical memory that's not permanently mapped is called 702 "high memory". 703 704 If you are compiling a kernel which will never run on a 705 machine with more than 128 MB total physical RAM, answer 706 N here. 707 708 If unsure, say Y. 709 710config FORCE_MAX_ZONEORDER 711 int "Maximum zone order" 712 default "11" 713 help 714 The kernel memory allocator divides physically contiguous memory 715 blocks into "zones", where each zone is a power of two number of 716 pages. This option selects the largest power of two that the kernel 717 keeps in the memory allocator. If you need to allocate very large 718 blocks of physically contiguous memory, then you may need to 719 increase this value. 720 721 This config option is actually maximum order plus one. For example, 722 a value of 11 means that the largest free memory block is 2^10 pages. 723 724endmenu 725 726menu "Power management options" 727 728source "kernel/power/Kconfig" 729 730endmenu 731