1# SPDX-License-Identifier: GPL-2.0 2config ZONE_DMA 3 def_bool y 4 5config XTENSA 6 def_bool y 7 select ARCH_HAS_SG_CHAIN 8 select ARCH_HAS_SYNC_DMA_FOR_CPU 9 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 10 select ARCH_NO_COHERENT_DMA_MMAP if !MMU 11 select ARCH_WANT_FRAME_POINTERS 12 select ARCH_WANT_IPC_PARSE_VERSION 13 select BUILDTIME_EXTABLE_SORT 14 select CLONE_BACKWARDS 15 select COMMON_CLK 16 select DMA_DIRECT_OPS 17 select GENERIC_ATOMIC64 18 select GENERIC_CLOCKEVENTS 19 select GENERIC_IRQ_SHOW 20 select GENERIC_PCI_IOMAP 21 select GENERIC_SCHED_CLOCK 22 select GENERIC_STRNCPY_FROM_USER if KASAN 23 select HAVE_ARCH_KASAN if MMU 24 select HAVE_DEBUG_KMEMLEAK 25 select HAVE_DMA_CONTIGUOUS 26 select HAVE_EXIT_THREAD 27 select HAVE_FUNCTION_TRACER 28 select HAVE_FUTEX_CMPXCHG if !MMU 29 select HAVE_HW_BREAKPOINT if PERF_EVENTS 30 select HAVE_IRQ_TIME_ACCOUNTING 31 select HAVE_OPROFILE 32 select HAVE_PERF_EVENTS 33 select HAVE_STACKPROTECTOR 34 select IRQ_DOMAIN 35 select MODULES_USE_ELF_RELA 36 select PERF_USE_VMALLOC 37 select VIRT_TO_BUS 38 help 39 Xtensa processors are 32-bit RISC machines designed by Tensilica 40 primarily for embedded systems. These processors are both 41 configurable and extensible. The Linux port to the Xtensa 42 architecture supports all processor configurations and extensions, 43 with reasonable minimum requirements. The Xtensa Linux project has 44 a home page at <http://www.linux-xtensa.org/>. 45 46config RWSEM_XCHGADD_ALGORITHM 47 def_bool y 48 49config GENERIC_HWEIGHT 50 def_bool y 51 52config ARCH_HAS_ILOG2_U32 53 def_bool n 54 55config ARCH_HAS_ILOG2_U64 56 def_bool n 57 58config NO_IOPORT_MAP 59 def_bool n 60 61config HZ 62 int 63 default 100 64 65config LOCKDEP_SUPPORT 66 def_bool y 67 68config STACKTRACE_SUPPORT 69 def_bool y 70 71config TRACE_IRQFLAGS_SUPPORT 72 def_bool y 73 74config MMU 75 def_bool n 76 77config HAVE_XTENSA_GPIO32 78 def_bool n 79 80config KASAN_SHADOW_OFFSET 81 hex 82 default 0x6e400000 83 84menu "Processor type and features" 85 86choice 87 prompt "Xtensa Processor Configuration" 88 default XTENSA_VARIANT_FSF 89 90config XTENSA_VARIANT_FSF 91 bool "fsf - default (not generic) configuration" 92 select MMU 93 94config XTENSA_VARIANT_DC232B 95 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 96 select MMU 97 select HAVE_XTENSA_GPIO32 98 help 99 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 100 101config XTENSA_VARIANT_DC233C 102 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 103 select MMU 104 select HAVE_XTENSA_GPIO32 105 help 106 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 107 108config XTENSA_VARIANT_CUSTOM 109 bool "Custom Xtensa processor configuration" 110 select HAVE_XTENSA_GPIO32 111 help 112 Select this variant to use a custom Xtensa processor configuration. 113 You will be prompted for a processor variant CORENAME. 114endchoice 115 116config XTENSA_VARIANT_CUSTOM_NAME 117 string "Xtensa Processor Custom Core Variant Name" 118 depends on XTENSA_VARIANT_CUSTOM 119 help 120 Provide the name of a custom Xtensa processor variant. 121 This CORENAME selects arch/xtensa/variant/CORENAME. 122 Dont forget you have to select MMU if you have one. 123 124config XTENSA_VARIANT_NAME 125 string 126 default "dc232b" if XTENSA_VARIANT_DC232B 127 default "dc233c" if XTENSA_VARIANT_DC233C 128 default "fsf" if XTENSA_VARIANT_FSF 129 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 130 131config XTENSA_VARIANT_MMU 132 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 133 depends on XTENSA_VARIANT_CUSTOM 134 default y 135 select MMU 136 help 137 Build a Conventional Kernel with full MMU support, 138 ie: it supports a TLB with auto-loading, page protection. 139 140config XTENSA_VARIANT_HAVE_PERF_EVENTS 141 bool "Core variant has Performance Monitor Module" 142 depends on XTENSA_VARIANT_CUSTOM 143 default n 144 help 145 Enable if core variant has Performance Monitor Module with 146 External Registers Interface. 147 148 If unsure, say N. 149 150config XTENSA_FAKE_NMI 151 bool "Treat PMM IRQ as NMI" 152 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 153 default n 154 help 155 If PMM IRQ is the only IRQ at EXCM level it is safe to 156 treat it as NMI, which improves accuracy of profiling. 157 158 If there are other interrupts at or above PMM IRQ priority level 159 but not above the EXCM level, PMM IRQ still may be treated as NMI, 160 but only if these IRQs are not used. There will be a build warning 161 saying that this is not safe, and a bugcheck if one of these IRQs 162 actually fire. 163 164 If unsure, say N. 165 166config XTENSA_UNALIGNED_USER 167 bool "Unaligned memory access in use space" 168 help 169 The Xtensa architecture currently does not handle unaligned 170 memory accesses in hardware but through an exception handler. 171 Per default, unaligned memory accesses are disabled in user space. 172 173 Say Y here to enable unaligned memory access in user space. 174 175config HAVE_SMP 176 bool "System Supports SMP (MX)" 177 depends on XTENSA_VARIANT_CUSTOM 178 select XTENSA_MX 179 help 180 This option is use to indicate that the system-on-a-chip (SOC) 181 supports Multiprocessing. Multiprocessor support implemented above 182 the CPU core definition and currently needs to be selected manually. 183 184 Multiprocessor support in implemented with external cache and 185 interrupt controllers. 186 187 The MX interrupt distributer adds Interprocessor Interrupts 188 and causes the IRQ numbers to be increased by 4 for devices 189 like the open cores ethernet driver and the serial interface. 190 191 You still have to select "Enable SMP" to enable SMP on this SOC. 192 193config SMP 194 bool "Enable Symmetric multi-processing support" 195 depends on HAVE_SMP 196 select GENERIC_SMP_IDLE_THREAD 197 help 198 Enabled SMP Software; allows more than one CPU/CORE 199 to be activated during startup. 200 201config NR_CPUS 202 depends on SMP 203 int "Maximum number of CPUs (2-32)" 204 range 2 32 205 default "4" 206 207config HOTPLUG_CPU 208 bool "Enable CPU hotplug support" 209 depends on SMP 210 help 211 Say Y here to allow turning CPUs off and on. CPUs can be 212 controlled through /sys/devices/system/cpu. 213 214 Say N if you want to disable CPU hotplug. 215 216config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 217 bool "Initialize Xtensa MMU inside the Linux kernel code" 218 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 219 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 220 help 221 Earlier version initialized the MMU in the exception vector 222 before jumping to _startup in head.S and had an advantage that 223 it was possible to place a software breakpoint at 'reset' and 224 then enter your normal kernel breakpoints once the MMU was mapped 225 to the kernel mappings (0XC0000000). 226 227 This unfortunately won't work for U-Boot and likely also wont 228 work for using KEXEC to have a hot kernel ready for doing a 229 KDUMP. 230 231 So now the MMU is initialized in head.S but it's necessary to 232 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 233 xt-gdb can't place a Software Breakpoint in the 0XD region prior 234 to mapping the MMU and after mapping even if the area of low memory 235 was mapped gdb wouldn't remove the breakpoint on hitting it as the 236 PC wouldn't match. Since Hardware Breakpoints are recommended for 237 Linux configurations it seems reasonable to just assume they exist 238 and leave this older mechanism for unfortunate souls that choose 239 not to follow Tensilica's recommendation. 240 241 Selecting this will cause U-Boot to set the KERNEL Load and Entry 242 address at 0x00003000 instead of the mapped std of 0xD0003000. 243 244 If in doubt, say Y. 245 246config MEMMAP_CACHEATTR 247 hex "Cache attributes for the memory address space" 248 depends on !MMU 249 default 0x22222222 250 help 251 These cache attributes are set up for noMMU systems. Each hex digit 252 specifies cache attributes for the corresponding 512MB memory 253 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 254 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 255 256 Cache attribute values are specific for the MMU type, so e.g. 257 for region protection MMUs: 2 is cache bypass, 4 is WB cached, 258 1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable, 259 bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass, 260 1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is 261 reserved). 262 263config KSEG_PADDR 264 hex "Physical address of the KSEG mapping" 265 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 266 default 0x00000000 267 help 268 This is the physical address where KSEG is mapped. Please refer to 269 the chosen KSEG layout help for the required address alignment. 270 Unpacked kernel image (including vectors) must be located completely 271 within KSEG. 272 Physical memory below this address is not available to linux. 273 274 If unsure, leave the default value here. 275 276config KERNEL_LOAD_ADDRESS 277 hex "Kernel load address" 278 default 0x60003000 if !MMU 279 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 280 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 281 help 282 This is the address where the kernel is loaded. 283 It is virtual address for MMUv2 configurations and physical address 284 for all other configurations. 285 286 If unsure, leave the default value here. 287 288config VECTORS_OFFSET 289 hex "Kernel vectors offset" 290 default 0x00003000 291 help 292 This is the offset of the kernel image from the relocatable vectors 293 base. 294 295 If unsure, leave the default value here. 296 297choice 298 prompt "KSEG layout" 299 depends on MMU 300 default XTENSA_KSEG_MMU_V2 301 302config XTENSA_KSEG_MMU_V2 303 bool "MMUv2: 128MB cached + 128MB uncached" 304 help 305 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 306 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 307 without cache. 308 KSEG_PADDR must be aligned to 128MB. 309 310config XTENSA_KSEG_256M 311 bool "256MB cached + 256MB uncached" 312 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 313 help 314 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 315 with cache and to 0xc0000000 without cache. 316 KSEG_PADDR must be aligned to 256MB. 317 318config XTENSA_KSEG_512M 319 bool "512MB cached + 512MB uncached" 320 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 321 help 322 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 323 with cache and to 0xc0000000 without cache. 324 KSEG_PADDR must be aligned to 256MB. 325 326endchoice 327 328config HIGHMEM 329 bool "High Memory Support" 330 depends on MMU 331 help 332 Linux can use the full amount of RAM in the system by 333 default. However, the default MMUv2 setup only maps the 334 lowermost 128 MB of memory linearly to the areas starting 335 at 0xd0000000 (cached) and 0xd8000000 (uncached). 336 When there are more than 128 MB memory in the system not 337 all of it can be "permanently mapped" by the kernel. 338 The physical memory that's not permanently mapped is called 339 "high memory". 340 341 If you are compiling a kernel which will never run on a 342 machine with more than 128 MB total physical RAM, answer 343 N here. 344 345 If unsure, say Y. 346 347config FAST_SYSCALL_XTENSA 348 bool "Enable fast atomic syscalls" 349 default n 350 help 351 fast_syscall_xtensa is a syscall that can make atomic operations 352 on UP kernel when processor has no s32c1i support. 353 354 This syscall is deprecated. It may have issues when called with 355 invalid arguments. It is provided only for backwards compatibility. 356 Only enable it if your userspace software requires it. 357 358 If unsure, say N. 359 360config FAST_SYSCALL_SPILL_REGISTERS 361 bool "Enable spill registers syscall" 362 default n 363 help 364 fast_syscall_spill_registers is a syscall that spills all active 365 register windows of a calling userspace task onto its stack. 366 367 This syscall is deprecated. It may have issues when called with 368 invalid arguments. It is provided only for backwards compatibility. 369 Only enable it if your userspace software requires it. 370 371 If unsure, say N. 372 373endmenu 374 375config XTENSA_CALIBRATE_CCOUNT 376 def_bool n 377 help 378 On some platforms (XT2000, for example), the CPU clock rate can 379 vary. The frequency can be determined, however, by measuring 380 against a well known, fixed frequency, such as an UART oscillator. 381 382config SERIAL_CONSOLE 383 def_bool n 384 385menu "Bus options" 386 387config PCI 388 bool "PCI support" 389 default y 390 help 391 Find out whether you have a PCI motherboard. PCI is the name of a 392 bus system, i.e. the way the CPU talks to the other stuff inside 393 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 394 VESA. If you have PCI, say Y, otherwise N. 395 396source "drivers/pci/Kconfig" 397 398endmenu 399 400menu "Platform options" 401 402choice 403 prompt "Xtensa System Type" 404 default XTENSA_PLATFORM_ISS 405 406config XTENSA_PLATFORM_ISS 407 bool "ISS" 408 select XTENSA_CALIBRATE_CCOUNT 409 select SERIAL_CONSOLE 410 help 411 ISS is an acronym for Tensilica's Instruction Set Simulator. 412 413config XTENSA_PLATFORM_XT2000 414 bool "XT2000" 415 select HAVE_IDE 416 help 417 XT2000 is the name of Tensilica's feature-rich emulation platform. 418 This hardware is capable of running a full Linux distribution. 419 420config XTENSA_PLATFORM_XTFPGA 421 bool "XTFPGA" 422 select ETHOC if ETHERNET 423 select PLATFORM_WANT_DEFAULT_MEM if !MMU 424 select SERIAL_CONSOLE 425 select XTENSA_CALIBRATE_CCOUNT 426 help 427 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 428 This hardware is capable of running a full Linux distribution. 429 430endchoice 431 432config PLATFORM_NR_IRQS 433 int 434 default 3 if XTENSA_PLATFORM_XT2000 435 default 0 436 437config XTENSA_CPU_CLOCK 438 int "CPU clock rate [MHz]" 439 depends on !XTENSA_CALIBRATE_CCOUNT 440 default 16 441 442config GENERIC_CALIBRATE_DELAY 443 bool "Auto calibration of the BogoMIPS value" 444 help 445 The BogoMIPS value can easily be derived from the CPU frequency. 446 447config CMDLINE_BOOL 448 bool "Default bootloader kernel arguments" 449 450config CMDLINE 451 string "Initial kernel command string" 452 depends on CMDLINE_BOOL 453 default "console=ttyS0,38400 root=/dev/ram" 454 help 455 On some architectures (EBSA110 and CATS), there is currently no way 456 for the boot loader to pass arguments to the kernel. For these 457 architectures, you should supply some command-line options at build 458 time by entering them here. As a minimum, you should specify the 459 memory size and the root device (e.g., mem=64M root=/dev/nfs). 460 461config USE_OF 462 bool "Flattened Device Tree support" 463 select OF 464 select OF_EARLY_FLATTREE 465 select OF_RESERVED_MEM 466 help 467 Include support for flattened device tree machine descriptions. 468 469config BUILTIN_DTB 470 string "DTB to build into the kernel image" 471 depends on OF 472 473config PARSE_BOOTPARAM 474 bool "Parse bootparam block" 475 default y 476 help 477 Parse parameters passed to the kernel from the bootloader. It may 478 be disabled if the kernel is known to run without the bootloader. 479 480 If unsure, say Y. 481 482config BLK_DEV_SIMDISK 483 tristate "Host file-based simulated block device support" 484 default n 485 depends on XTENSA_PLATFORM_ISS && BLOCK 486 help 487 Create block devices that map to files in the host file system. 488 Device binding to host file may be changed at runtime via proc 489 interface provided the device is not in use. 490 491config BLK_DEV_SIMDISK_COUNT 492 int "Number of host file-based simulated block devices" 493 range 1 10 494 depends on BLK_DEV_SIMDISK 495 default 2 496 help 497 This is the default minimal number of created block devices. 498 Kernel/module parameter 'simdisk_count' may be used to change this 499 value at runtime. More file names (but no more than 10) may be 500 specified as parameters, simdisk_count grows accordingly. 501 502config SIMDISK0_FILENAME 503 string "Host filename for the first simulated device" 504 depends on BLK_DEV_SIMDISK = y 505 default "" 506 help 507 Attach a first simdisk to a host file. Conventionally, this file 508 contains a root file system. 509 510config SIMDISK1_FILENAME 511 string "Host filename for the second simulated device" 512 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 513 default "" 514 help 515 Another simulated disk in a host file for a buildroot-independent 516 storage. 517 518config FORCE_MAX_ZONEORDER 519 int "Maximum zone order" 520 default "11" 521 help 522 The kernel memory allocator divides physically contiguous memory 523 blocks into "zones", where each zone is a power of two number of 524 pages. This option selects the largest power of two that the kernel 525 keeps in the memory allocator. If you need to allocate very large 526 blocks of physically contiguous memory, then you may need to 527 increase this value. 528 529 This config option is actually maximum order plus one. For example, 530 a value of 11 means that the largest free memory block is 2^10 pages. 531 532source "drivers/pcmcia/Kconfig" 533 534config PLATFORM_WANT_DEFAULT_MEM 535 def_bool n 536 537config DEFAULT_MEM_START 538 hex 539 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 540 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 541 default 0x00000000 542 help 543 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 544 in noMMU configurations. 545 546 If unsure, leave the default value here. 547 548config XTFPGA_LCD 549 bool "Enable XTFPGA LCD driver" 550 depends on XTENSA_PLATFORM_XTFPGA 551 default n 552 help 553 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 554 progress messages there during bootup/shutdown. It may be useful 555 during board bringup. 556 557 If unsure, say N. 558 559config XTFPGA_LCD_BASE_ADDR 560 hex "XTFPGA LCD base address" 561 depends on XTFPGA_LCD 562 default "0x0d0c0000" 563 help 564 Base address of the LCD controller inside KIO region. 565 Different boards from XTFPGA family have LCD controller at different 566 addresses. Please consult prototyping user guide for your board for 567 the correct address. Wrong address here may lead to hardware lockup. 568 569config XTFPGA_LCD_8BIT_ACCESS 570 bool "Use 8-bit access to XTFPGA LCD" 571 depends on XTFPGA_LCD 572 default n 573 help 574 LCD may be connected with 4- or 8-bit interface, 8-bit access may 575 only be used with 8-bit interface. Please consult prototyping user 576 guide for your board for the correct interface width. 577 578endmenu 579 580menu "Power management options" 581 582source "kernel/power/Kconfig" 583 584endmenu 585