1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_BINFMT_FLAT if !MMU 6 select ARCH_HAS_DMA_PREP_COHERENT if MMU 7 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 8 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 9 select ARCH_HAS_UNCACHED_SEGMENT if MMU 10 select ARCH_USE_QUEUED_RWLOCKS 11 select ARCH_USE_QUEUED_SPINLOCKS 12 select ARCH_WANT_FRAME_POINTERS 13 select ARCH_WANT_IPC_PARSE_VERSION 14 select BUILDTIME_EXTABLE_SORT 15 select CLONE_BACKWARDS 16 select COMMON_CLK 17 select DMA_REMAP if MMU 18 select GENERIC_ATOMIC64 19 select GENERIC_CLOCKEVENTS 20 select GENERIC_IRQ_SHOW 21 select GENERIC_PCI_IOMAP 22 select GENERIC_SCHED_CLOCK 23 select GENERIC_STRNCPY_FROM_USER if KASAN 24 select HAVE_ARCH_JUMP_LABEL 25 select HAVE_ARCH_KASAN if MMU 26 select HAVE_ARCH_TRACEHOOK 27 select HAVE_DEBUG_KMEMLEAK 28 select HAVE_DMA_CONTIGUOUS 29 select HAVE_EXIT_THREAD 30 select HAVE_FUNCTION_TRACER 31 select HAVE_FUTEX_CMPXCHG if !MMU 32 select HAVE_HW_BREAKPOINT if PERF_EVENTS 33 select HAVE_IRQ_TIME_ACCOUNTING 34 select HAVE_OPROFILE 35 select HAVE_PCI 36 select HAVE_PERF_EVENTS 37 select HAVE_STACKPROTECTOR 38 select HAVE_SYSCALL_TRACEPOINTS 39 select IRQ_DOMAIN 40 select MODULES_USE_ELF_RELA 41 select PERF_USE_VMALLOC 42 select VIRT_TO_BUS 43 help 44 Xtensa processors are 32-bit RISC machines designed by Tensilica 45 primarily for embedded systems. These processors are both 46 configurable and extensible. The Linux port to the Xtensa 47 architecture supports all processor configurations and extensions, 48 with reasonable minimum requirements. The Xtensa Linux project has 49 a home page at <http://www.linux-xtensa.org/>. 50 51config GENERIC_HWEIGHT 52 def_bool y 53 54config ARCH_HAS_ILOG2_U32 55 def_bool n 56 57config ARCH_HAS_ILOG2_U64 58 def_bool n 59 60config NO_IOPORT_MAP 61 def_bool n 62 63config HZ 64 int 65 default 100 66 67config LOCKDEP_SUPPORT 68 def_bool y 69 70config STACKTRACE_SUPPORT 71 def_bool y 72 73config TRACE_IRQFLAGS_SUPPORT 74 def_bool y 75 76config MMU 77 def_bool n 78 79config HAVE_XTENSA_GPIO32 80 def_bool n 81 82config KASAN_SHADOW_OFFSET 83 hex 84 default 0x6e400000 85 86menu "Processor type and features" 87 88choice 89 prompt "Xtensa Processor Configuration" 90 default XTENSA_VARIANT_FSF 91 92config XTENSA_VARIANT_FSF 93 bool "fsf - default (not generic) configuration" 94 select MMU 95 96config XTENSA_VARIANT_DC232B 97 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 98 select MMU 99 select HAVE_XTENSA_GPIO32 100 help 101 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 102 103config XTENSA_VARIANT_DC233C 104 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 105 select MMU 106 select HAVE_XTENSA_GPIO32 107 help 108 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 109 110config XTENSA_VARIANT_CUSTOM 111 bool "Custom Xtensa processor configuration" 112 select HAVE_XTENSA_GPIO32 113 help 114 Select this variant to use a custom Xtensa processor configuration. 115 You will be prompted for a processor variant CORENAME. 116endchoice 117 118config XTENSA_VARIANT_CUSTOM_NAME 119 string "Xtensa Processor Custom Core Variant Name" 120 depends on XTENSA_VARIANT_CUSTOM 121 help 122 Provide the name of a custom Xtensa processor variant. 123 This CORENAME selects arch/xtensa/variant/CORENAME. 124 Dont forget you have to select MMU if you have one. 125 126config XTENSA_VARIANT_NAME 127 string 128 default "dc232b" if XTENSA_VARIANT_DC232B 129 default "dc233c" if XTENSA_VARIANT_DC233C 130 default "fsf" if XTENSA_VARIANT_FSF 131 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 132 133config XTENSA_VARIANT_MMU 134 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 135 depends on XTENSA_VARIANT_CUSTOM 136 default y 137 select MMU 138 help 139 Build a Conventional Kernel with full MMU support, 140 ie: it supports a TLB with auto-loading, page protection. 141 142config XTENSA_VARIANT_HAVE_PERF_EVENTS 143 bool "Core variant has Performance Monitor Module" 144 depends on XTENSA_VARIANT_CUSTOM 145 default n 146 help 147 Enable if core variant has Performance Monitor Module with 148 External Registers Interface. 149 150 If unsure, say N. 151 152config XTENSA_FAKE_NMI 153 bool "Treat PMM IRQ as NMI" 154 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 155 default n 156 help 157 If PMM IRQ is the only IRQ at EXCM level it is safe to 158 treat it as NMI, which improves accuracy of profiling. 159 160 If there are other interrupts at or above PMM IRQ priority level 161 but not above the EXCM level, PMM IRQ still may be treated as NMI, 162 but only if these IRQs are not used. There will be a build warning 163 saying that this is not safe, and a bugcheck if one of these IRQs 164 actually fire. 165 166 If unsure, say N. 167 168config XTENSA_UNALIGNED_USER 169 bool "Unaligned memory access in user space" 170 help 171 The Xtensa architecture currently does not handle unaligned 172 memory accesses in hardware but through an exception handler. 173 Per default, unaligned memory accesses are disabled in user space. 174 175 Say Y here to enable unaligned memory access in user space. 176 177config HAVE_SMP 178 bool "System Supports SMP (MX)" 179 depends on XTENSA_VARIANT_CUSTOM 180 select XTENSA_MX 181 help 182 This option is use to indicate that the system-on-a-chip (SOC) 183 supports Multiprocessing. Multiprocessor support implemented above 184 the CPU core definition and currently needs to be selected manually. 185 186 Multiprocessor support in implemented with external cache and 187 interrupt controllers. 188 189 The MX interrupt distributer adds Interprocessor Interrupts 190 and causes the IRQ numbers to be increased by 4 for devices 191 like the open cores ethernet driver and the serial interface. 192 193 You still have to select "Enable SMP" to enable SMP on this SOC. 194 195config SMP 196 bool "Enable Symmetric multi-processing support" 197 depends on HAVE_SMP 198 select GENERIC_SMP_IDLE_THREAD 199 help 200 Enabled SMP Software; allows more than one CPU/CORE 201 to be activated during startup. 202 203config NR_CPUS 204 depends on SMP 205 int "Maximum number of CPUs (2-32)" 206 range 2 32 207 default "4" 208 209config HOTPLUG_CPU 210 bool "Enable CPU hotplug support" 211 depends on SMP 212 help 213 Say Y here to allow turning CPUs off and on. CPUs can be 214 controlled through /sys/devices/system/cpu. 215 216 Say N if you want to disable CPU hotplug. 217 218config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 219 bool "Initialize Xtensa MMU inside the Linux kernel code" 220 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 221 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 222 help 223 Earlier version initialized the MMU in the exception vector 224 before jumping to _startup in head.S and had an advantage that 225 it was possible to place a software breakpoint at 'reset' and 226 then enter your normal kernel breakpoints once the MMU was mapped 227 to the kernel mappings (0XC0000000). 228 229 This unfortunately won't work for U-Boot and likely also wont 230 work for using KEXEC to have a hot kernel ready for doing a 231 KDUMP. 232 233 So now the MMU is initialized in head.S but it's necessary to 234 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 235 xt-gdb can't place a Software Breakpoint in the 0XD region prior 236 to mapping the MMU and after mapping even if the area of low memory 237 was mapped gdb wouldn't remove the breakpoint on hitting it as the 238 PC wouldn't match. Since Hardware Breakpoints are recommended for 239 Linux configurations it seems reasonable to just assume they exist 240 and leave this older mechanism for unfortunate souls that choose 241 not to follow Tensilica's recommendation. 242 243 Selecting this will cause U-Boot to set the KERNEL Load and Entry 244 address at 0x00003000 instead of the mapped std of 0xD0003000. 245 246 If in doubt, say Y. 247 248config MEMMAP_CACHEATTR 249 hex "Cache attributes for the memory address space" 250 depends on !MMU 251 default 0x22222222 252 help 253 These cache attributes are set up for noMMU systems. Each hex digit 254 specifies cache attributes for the corresponding 512MB memory 255 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 256 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 257 258 Cache attribute values are specific for the MMU type. 259 For region protection MMUs: 260 1: WT cached, 261 2: cache bypass, 262 4: WB cached, 263 f: illegal. 264 For ful MMU: 265 bit 0: executable, 266 bit 1: writable, 267 bits 2..3: 268 0: cache bypass, 269 1: WB cache, 270 2: WT cache, 271 3: special (c and e are illegal, f is reserved). 272 For MPU: 273 0: illegal, 274 1: WB cache, 275 2: WB, no-write-allocate cache, 276 3: WT cache, 277 4: cache bypass. 278 279config KSEG_PADDR 280 hex "Physical address of the KSEG mapping" 281 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 282 default 0x00000000 283 help 284 This is the physical address where KSEG is mapped. Please refer to 285 the chosen KSEG layout help for the required address alignment. 286 Unpacked kernel image (including vectors) must be located completely 287 within KSEG. 288 Physical memory below this address is not available to linux. 289 290 If unsure, leave the default value here. 291 292config KERNEL_LOAD_ADDRESS 293 hex "Kernel load address" 294 default 0x60003000 if !MMU 295 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 296 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 297 help 298 This is the address where the kernel is loaded. 299 It is virtual address for MMUv2 configurations and physical address 300 for all other configurations. 301 302 If unsure, leave the default value here. 303 304config VECTORS_OFFSET 305 hex "Kernel vectors offset" 306 default 0x00003000 307 help 308 This is the offset of the kernel image from the relocatable vectors 309 base. 310 311 If unsure, leave the default value here. 312 313choice 314 prompt "KSEG layout" 315 depends on MMU 316 default XTENSA_KSEG_MMU_V2 317 318config XTENSA_KSEG_MMU_V2 319 bool "MMUv2: 128MB cached + 128MB uncached" 320 help 321 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 322 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 323 without cache. 324 KSEG_PADDR must be aligned to 128MB. 325 326config XTENSA_KSEG_256M 327 bool "256MB cached + 256MB uncached" 328 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 329 help 330 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 331 with cache and to 0xc0000000 without cache. 332 KSEG_PADDR must be aligned to 256MB. 333 334config XTENSA_KSEG_512M 335 bool "512MB cached + 512MB uncached" 336 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 337 help 338 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 339 with cache and to 0xc0000000 without cache. 340 KSEG_PADDR must be aligned to 256MB. 341 342endchoice 343 344config HIGHMEM 345 bool "High Memory Support" 346 depends on MMU 347 help 348 Linux can use the full amount of RAM in the system by 349 default. However, the default MMUv2 setup only maps the 350 lowermost 128 MB of memory linearly to the areas starting 351 at 0xd0000000 (cached) and 0xd8000000 (uncached). 352 When there are more than 128 MB memory in the system not 353 all of it can be "permanently mapped" by the kernel. 354 The physical memory that's not permanently mapped is called 355 "high memory". 356 357 If you are compiling a kernel which will never run on a 358 machine with more than 128 MB total physical RAM, answer 359 N here. 360 361 If unsure, say Y. 362 363config FAST_SYSCALL_XTENSA 364 bool "Enable fast atomic syscalls" 365 default n 366 help 367 fast_syscall_xtensa is a syscall that can make atomic operations 368 on UP kernel when processor has no s32c1i support. 369 370 This syscall is deprecated. It may have issues when called with 371 invalid arguments. It is provided only for backwards compatibility. 372 Only enable it if your userspace software requires it. 373 374 If unsure, say N. 375 376config FAST_SYSCALL_SPILL_REGISTERS 377 bool "Enable spill registers syscall" 378 default n 379 help 380 fast_syscall_spill_registers is a syscall that spills all active 381 register windows of a calling userspace task onto its stack. 382 383 This syscall is deprecated. It may have issues when called with 384 invalid arguments. It is provided only for backwards compatibility. 385 Only enable it if your userspace software requires it. 386 387 If unsure, say N. 388 389config USER_ABI_CALL0 390 bool 391 392choice 393 prompt "Userspace ABI" 394 default USER_ABI_DEFAULT 395 help 396 Select supported userspace ABI. 397 398 If unsure, choose the default ABI. 399 400config USER_ABI_DEFAULT 401 bool "Default ABI only" 402 help 403 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 404 call0 ABI binaries may be run on such kernel, but signal delivery 405 will not work correctly for them. 406 407config USER_ABI_CALL0_ONLY 408 bool "Call0 ABI only" 409 select USER_ABI_CALL0 410 help 411 Select this option to support only call0 ABI in userspace. 412 Windowed ABI binaries will crash with a segfault caused by 413 an illegal instruction exception on the first 'entry' opcode. 414 415 Choose this option if you're planning to run only user code 416 built with call0 ABI. 417 418config USER_ABI_CALL0_PROBE 419 bool "Support both windowed and call0 ABI by probing" 420 select USER_ABI_CALL0 421 help 422 Select this option to support both windowed and call0 userspace 423 ABIs. When enabled all processes are started with PS.WOE disabled 424 and a fast user exception handler for an illegal instruction is 425 used to turn on PS.WOE bit on the first 'entry' opcode executed by 426 the userspace. 427 428 This option should be enabled for the kernel that must support 429 both call0 and windowed ABIs in userspace at the same time. 430 431 Note that Xtensa ISA does not guarantee that entry opcode will 432 raise an illegal instruction exception on cores with XEA2 when 433 PS.WOE is disabled, check whether the target core supports it. 434 435endchoice 436 437endmenu 438 439config XTENSA_CALIBRATE_CCOUNT 440 def_bool n 441 help 442 On some platforms (XT2000, for example), the CPU clock rate can 443 vary. The frequency can be determined, however, by measuring 444 against a well known, fixed frequency, such as an UART oscillator. 445 446config SERIAL_CONSOLE 447 def_bool n 448 449menu "Platform options" 450 451choice 452 prompt "Xtensa System Type" 453 default XTENSA_PLATFORM_ISS 454 455config XTENSA_PLATFORM_ISS 456 bool "ISS" 457 select XTENSA_CALIBRATE_CCOUNT 458 select SERIAL_CONSOLE 459 help 460 ISS is an acronym for Tensilica's Instruction Set Simulator. 461 462config XTENSA_PLATFORM_XT2000 463 bool "XT2000" 464 select HAVE_IDE 465 help 466 XT2000 is the name of Tensilica's feature-rich emulation platform. 467 This hardware is capable of running a full Linux distribution. 468 469config XTENSA_PLATFORM_XTFPGA 470 bool "XTFPGA" 471 select ETHOC if ETHERNET 472 select PLATFORM_WANT_DEFAULT_MEM if !MMU 473 select SERIAL_CONSOLE 474 select XTENSA_CALIBRATE_CCOUNT 475 help 476 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 477 This hardware is capable of running a full Linux distribution. 478 479endchoice 480 481config PLATFORM_NR_IRQS 482 int 483 default 3 if XTENSA_PLATFORM_XT2000 484 default 0 485 486config XTENSA_CPU_CLOCK 487 int "CPU clock rate [MHz]" 488 depends on !XTENSA_CALIBRATE_CCOUNT 489 default 16 490 491config GENERIC_CALIBRATE_DELAY 492 bool "Auto calibration of the BogoMIPS value" 493 help 494 The BogoMIPS value can easily be derived from the CPU frequency. 495 496config CMDLINE_BOOL 497 bool "Default bootloader kernel arguments" 498 499config CMDLINE 500 string "Initial kernel command string" 501 depends on CMDLINE_BOOL 502 default "console=ttyS0,38400 root=/dev/ram" 503 help 504 On some architectures (EBSA110 and CATS), there is currently no way 505 for the boot loader to pass arguments to the kernel. For these 506 architectures, you should supply some command-line options at build 507 time by entering them here. As a minimum, you should specify the 508 memory size and the root device (e.g., mem=64M root=/dev/nfs). 509 510config USE_OF 511 bool "Flattened Device Tree support" 512 select OF 513 select OF_EARLY_FLATTREE 514 help 515 Include support for flattened device tree machine descriptions. 516 517config BUILTIN_DTB_SOURCE 518 string "DTB to build into the kernel image" 519 depends on OF 520 521config PARSE_BOOTPARAM 522 bool "Parse bootparam block" 523 default y 524 help 525 Parse parameters passed to the kernel from the bootloader. It may 526 be disabled if the kernel is known to run without the bootloader. 527 528 If unsure, say Y. 529 530config BLK_DEV_SIMDISK 531 tristate "Host file-based simulated block device support" 532 default n 533 depends on XTENSA_PLATFORM_ISS && BLOCK 534 help 535 Create block devices that map to files in the host file system. 536 Device binding to host file may be changed at runtime via proc 537 interface provided the device is not in use. 538 539config BLK_DEV_SIMDISK_COUNT 540 int "Number of host file-based simulated block devices" 541 range 1 10 542 depends on BLK_DEV_SIMDISK 543 default 2 544 help 545 This is the default minimal number of created block devices. 546 Kernel/module parameter 'simdisk_count' may be used to change this 547 value at runtime. More file names (but no more than 10) may be 548 specified as parameters, simdisk_count grows accordingly. 549 550config SIMDISK0_FILENAME 551 string "Host filename for the first simulated device" 552 depends on BLK_DEV_SIMDISK = y 553 default "" 554 help 555 Attach a first simdisk to a host file. Conventionally, this file 556 contains a root file system. 557 558config SIMDISK1_FILENAME 559 string "Host filename for the second simulated device" 560 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 561 default "" 562 help 563 Another simulated disk in a host file for a buildroot-independent 564 storage. 565 566config FORCE_MAX_ZONEORDER 567 int "Maximum zone order" 568 default "11" 569 help 570 The kernel memory allocator divides physically contiguous memory 571 blocks into "zones", where each zone is a power of two number of 572 pages. This option selects the largest power of two that the kernel 573 keeps in the memory allocator. If you need to allocate very large 574 blocks of physically contiguous memory, then you may need to 575 increase this value. 576 577 This config option is actually maximum order plus one. For example, 578 a value of 11 means that the largest free memory block is 2^10 pages. 579 580config PLATFORM_WANT_DEFAULT_MEM 581 def_bool n 582 583config DEFAULT_MEM_START 584 hex 585 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 586 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 587 default 0x00000000 588 help 589 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 590 in noMMU configurations. 591 592 If unsure, leave the default value here. 593 594config XTFPGA_LCD 595 bool "Enable XTFPGA LCD driver" 596 depends on XTENSA_PLATFORM_XTFPGA 597 default n 598 help 599 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 600 progress messages there during bootup/shutdown. It may be useful 601 during board bringup. 602 603 If unsure, say N. 604 605config XTFPGA_LCD_BASE_ADDR 606 hex "XTFPGA LCD base address" 607 depends on XTFPGA_LCD 608 default "0x0d0c0000" 609 help 610 Base address of the LCD controller inside KIO region. 611 Different boards from XTFPGA family have LCD controller at different 612 addresses. Please consult prototyping user guide for your board for 613 the correct address. Wrong address here may lead to hardware lockup. 614 615config XTFPGA_LCD_8BIT_ACCESS 616 bool "Use 8-bit access to XTFPGA LCD" 617 depends on XTFPGA_LCD 618 default n 619 help 620 LCD may be connected with 4- or 8-bit interface, 8-bit access may 621 only be used with 8-bit interface. Please consult prototyping user 622 guide for your board for the correct interface width. 623 624endmenu 625 626menu "Power management options" 627 628source "kernel/power/Kconfig" 629 630endmenu 631