1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_BINFMT_FLAT if !MMU 6 select ARCH_HAS_CURRENT_STACK_POINTER 7 select ARCH_HAS_DEBUG_VM_PGTABLE 8 select ARCH_HAS_DMA_PREP_COHERENT if MMU 9 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 10 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 11 select ARCH_HAS_DMA_SET_UNCACHED if MMU 12 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN 13 select ARCH_HAS_STRNLEN_USER 14 select ARCH_USE_MEMTEST 15 select ARCH_USE_QUEUED_RWLOCKS 16 select ARCH_USE_QUEUED_SPINLOCKS 17 select ARCH_WANT_FRAME_POINTERS 18 select ARCH_WANT_IPC_PARSE_VERSION 19 select BUILDTIME_TABLE_SORT 20 select CLONE_BACKWARDS 21 select COMMON_CLK 22 select DMA_NONCOHERENT_MMAP if MMU 23 select GENERIC_ATOMIC64 24 select GENERIC_IRQ_SHOW 25 select GENERIC_LIB_CMPDI2 26 select GENERIC_LIB_MULDI3 27 select GENERIC_LIB_UCMPDI2 28 select GENERIC_PCI_IOMAP 29 select GENERIC_SCHED_CLOCK 30 select HAVE_ARCH_AUDITSYSCALL 31 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 32 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 33 select HAVE_ARCH_KCSAN 34 select HAVE_ARCH_SECCOMP_FILTER 35 select HAVE_ARCH_TRACEHOOK 36 select HAVE_CONTEXT_TRACKING 37 select HAVE_DEBUG_KMEMLEAK 38 select HAVE_DMA_CONTIGUOUS 39 select HAVE_EXIT_THREAD 40 select HAVE_FUNCTION_TRACER 41 select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000 42 select HAVE_HW_BREAKPOINT if PERF_EVENTS 43 select HAVE_IRQ_TIME_ACCOUNTING 44 select HAVE_PCI 45 select HAVE_PERF_EVENTS 46 select HAVE_STACKPROTECTOR 47 select HAVE_SYSCALL_TRACEPOINTS 48 select HAVE_VIRT_CPU_ACCOUNTING_GEN 49 select IRQ_DOMAIN 50 select MODULES_USE_ELF_RELA 51 select PERF_USE_VMALLOC 52 select TRACE_IRQFLAGS_SUPPORT 53 select VIRT_TO_BUS 54 help 55 Xtensa processors are 32-bit RISC machines designed by Tensilica 56 primarily for embedded systems. These processors are both 57 configurable and extensible. The Linux port to the Xtensa 58 architecture supports all processor configurations and extensions, 59 with reasonable minimum requirements. The Xtensa Linux project has 60 a home page at <http://www.linux-xtensa.org/>. 61 62config GENERIC_HWEIGHT 63 def_bool y 64 65config ARCH_HAS_ILOG2_U32 66 def_bool n 67 68config ARCH_HAS_ILOG2_U64 69 def_bool n 70 71config NO_IOPORT_MAP 72 def_bool n 73 74config HZ 75 int 76 default 100 77 78config LOCKDEP_SUPPORT 79 def_bool y 80 81config STACKTRACE_SUPPORT 82 def_bool y 83 84config MMU 85 def_bool n 86 select PFAULT 87 88config HAVE_XTENSA_GPIO32 89 def_bool n 90 91config KASAN_SHADOW_OFFSET 92 hex 93 default 0x6e400000 94 95config CPU_BIG_ENDIAN 96 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1) 97 98config CPU_LITTLE_ENDIAN 99 def_bool !CPU_BIG_ENDIAN 100 101config CC_HAVE_CALL0_ABI 102 def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1) 103 104menu "Processor type and features" 105 106choice 107 prompt "Xtensa Processor Configuration" 108 default XTENSA_VARIANT_FSF 109 110config XTENSA_VARIANT_FSF 111 bool "fsf - default (not generic) configuration" 112 select MMU 113 114config XTENSA_VARIANT_DC232B 115 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 116 select MMU 117 select HAVE_XTENSA_GPIO32 118 help 119 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 120 121config XTENSA_VARIANT_DC233C 122 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 123 select MMU 124 select HAVE_XTENSA_GPIO32 125 help 126 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 127 128config XTENSA_VARIANT_CUSTOM 129 bool "Custom Xtensa processor configuration" 130 select HAVE_XTENSA_GPIO32 131 help 132 Select this variant to use a custom Xtensa processor configuration. 133 You will be prompted for a processor variant CORENAME. 134endchoice 135 136config XTENSA_VARIANT_CUSTOM_NAME 137 string "Xtensa Processor Custom Core Variant Name" 138 depends on XTENSA_VARIANT_CUSTOM 139 help 140 Provide the name of a custom Xtensa processor variant. 141 This CORENAME selects arch/xtensa/variant/CORENAME. 142 Don't forget you have to select MMU if you have one. 143 144config XTENSA_VARIANT_NAME 145 string 146 default "dc232b" if XTENSA_VARIANT_DC232B 147 default "dc233c" if XTENSA_VARIANT_DC233C 148 default "fsf" if XTENSA_VARIANT_FSF 149 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 150 151config XTENSA_VARIANT_MMU 152 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 153 depends on XTENSA_VARIANT_CUSTOM 154 default y 155 select MMU 156 help 157 Build a Conventional Kernel with full MMU support, 158 ie: it supports a TLB with auto-loading, page protection. 159 160config XTENSA_VARIANT_HAVE_PERF_EVENTS 161 bool "Core variant has Performance Monitor Module" 162 depends on XTENSA_VARIANT_CUSTOM 163 default n 164 help 165 Enable if core variant has Performance Monitor Module with 166 External Registers Interface. 167 168 If unsure, say N. 169 170config XTENSA_FAKE_NMI 171 bool "Treat PMM IRQ as NMI" 172 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 173 default n 174 help 175 If PMM IRQ is the only IRQ at EXCM level it is safe to 176 treat it as NMI, which improves accuracy of profiling. 177 178 If there are other interrupts at or above PMM IRQ priority level 179 but not above the EXCM level, PMM IRQ still may be treated as NMI, 180 but only if these IRQs are not used. There will be a build warning 181 saying that this is not safe, and a bugcheck if one of these IRQs 182 actually fire. 183 184 If unsure, say N. 185 186config PFAULT 187 bool "Handle protection faults" if EXPERT && !MMU 188 default y 189 help 190 Handle protection faults. MMU configurations must enable it. 191 noMMU configurations may disable it if used memory map never 192 generates protection faults or faults are always fatal. 193 194 If unsure, say Y. 195 196config XTENSA_UNALIGNED_USER 197 bool "Unaligned memory access in user space" 198 help 199 The Xtensa architecture currently does not handle unaligned 200 memory accesses in hardware but through an exception handler. 201 Per default, unaligned memory accesses are disabled in user space. 202 203 Say Y here to enable unaligned memory access in user space. 204 205config HAVE_SMP 206 bool "System Supports SMP (MX)" 207 depends on XTENSA_VARIANT_CUSTOM 208 select XTENSA_MX 209 help 210 This option is used to indicate that the system-on-a-chip (SOC) 211 supports Multiprocessing. Multiprocessor support implemented above 212 the CPU core definition and currently needs to be selected manually. 213 214 Multiprocessor support is implemented with external cache and 215 interrupt controllers. 216 217 The MX interrupt distributer adds Interprocessor Interrupts 218 and causes the IRQ numbers to be increased by 4 for devices 219 like the open cores ethernet driver and the serial interface. 220 221 You still have to select "Enable SMP" to enable SMP on this SOC. 222 223config SMP 224 bool "Enable Symmetric multi-processing support" 225 depends on HAVE_SMP 226 select GENERIC_SMP_IDLE_THREAD 227 help 228 Enabled SMP Software; allows more than one CPU/CORE 229 to be activated during startup. 230 231config NR_CPUS 232 depends on SMP 233 int "Maximum number of CPUs (2-32)" 234 range 2 32 235 default "4" 236 237config HOTPLUG_CPU 238 bool "Enable CPU hotplug support" 239 depends on SMP 240 help 241 Say Y here to allow turning CPUs off and on. CPUs can be 242 controlled through /sys/devices/system/cpu. 243 244 Say N if you want to disable CPU hotplug. 245 246config SECONDARY_RESET_VECTOR 247 bool "Secondary cores use alternative reset vector" 248 default y 249 depends on HAVE_SMP 250 help 251 Secondary cores may be configured to use alternative reset vector, 252 or all cores may use primary reset vector. 253 Say Y here to supply handler for the alternative reset location. 254 255config FAST_SYSCALL_XTENSA 256 bool "Enable fast atomic syscalls" 257 default n 258 help 259 fast_syscall_xtensa is a syscall that can make atomic operations 260 on UP kernel when processor has no s32c1i support. 261 262 This syscall is deprecated. It may have issues when called with 263 invalid arguments. It is provided only for backwards compatibility. 264 Only enable it if your userspace software requires it. 265 266 If unsure, say N. 267 268config FAST_SYSCALL_SPILL_REGISTERS 269 bool "Enable spill registers syscall" 270 default n 271 help 272 fast_syscall_spill_registers is a syscall that spills all active 273 register windows of a calling userspace task onto its stack. 274 275 This syscall is deprecated. It may have issues when called with 276 invalid arguments. It is provided only for backwards compatibility. 277 Only enable it if your userspace software requires it. 278 279 If unsure, say N. 280 281choice 282 prompt "Kernel ABI" 283 default KERNEL_ABI_DEFAULT 284 help 285 Select ABI for the kernel code. This ABI is independent of the 286 supported userspace ABI and any combination of the 287 kernel/userspace ABI is possible and should work. 288 289 In case both kernel and userspace support only call0 ABI 290 all register windows support code will be omitted from the 291 build. 292 293 If unsure, choose the default ABI. 294 295config KERNEL_ABI_DEFAULT 296 bool "Default ABI" 297 help 298 Select this option to compile kernel code with the default ABI 299 selected for the toolchain. 300 Normally cores with windowed registers option use windowed ABI and 301 cores without it use call0 ABI. 302 303config KERNEL_ABI_CALL0 304 bool "Call0 ABI" if CC_HAVE_CALL0_ABI 305 help 306 Select this option to compile kernel code with call0 ABI even with 307 toolchain that defaults to windowed ABI. 308 When this option is not selected the default toolchain ABI will 309 be used for the kernel code. 310 311endchoice 312 313config USER_ABI_CALL0 314 bool 315 316choice 317 prompt "Userspace ABI" 318 default USER_ABI_DEFAULT 319 help 320 Select supported userspace ABI. 321 322 If unsure, choose the default ABI. 323 324config USER_ABI_DEFAULT 325 bool "Default ABI only" 326 help 327 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 328 call0 ABI binaries may be run on such kernel, but signal delivery 329 will not work correctly for them. 330 331config USER_ABI_CALL0_ONLY 332 bool "Call0 ABI only" 333 select USER_ABI_CALL0 334 help 335 Select this option to support only call0 ABI in userspace. 336 Windowed ABI binaries will crash with a segfault caused by 337 an illegal instruction exception on the first 'entry' opcode. 338 339 Choose this option if you're planning to run only user code 340 built with call0 ABI. 341 342config USER_ABI_CALL0_PROBE 343 bool "Support both windowed and call0 ABI by probing" 344 select USER_ABI_CALL0 345 help 346 Select this option to support both windowed and call0 userspace 347 ABIs. When enabled all processes are started with PS.WOE disabled 348 and a fast user exception handler for an illegal instruction is 349 used to turn on PS.WOE bit on the first 'entry' opcode executed by 350 the userspace. 351 352 This option should be enabled for the kernel that must support 353 both call0 and windowed ABIs in userspace at the same time. 354 355 Note that Xtensa ISA does not guarantee that entry opcode will 356 raise an illegal instruction exception on cores with XEA2 when 357 PS.WOE is disabled, check whether the target core supports it. 358 359endchoice 360 361endmenu 362 363config XTENSA_CALIBRATE_CCOUNT 364 def_bool n 365 help 366 On some platforms (XT2000, for example), the CPU clock rate can 367 vary. The frequency can be determined, however, by measuring 368 against a well known, fixed frequency, such as an UART oscillator. 369 370config SERIAL_CONSOLE 371 def_bool n 372 373config PLATFORM_HAVE_XIP 374 def_bool n 375 376menu "Platform options" 377 378choice 379 prompt "Xtensa System Type" 380 default XTENSA_PLATFORM_ISS 381 382config XTENSA_PLATFORM_ISS 383 bool "ISS" 384 select XTENSA_CALIBRATE_CCOUNT 385 select SERIAL_CONSOLE 386 help 387 ISS is an acronym for Tensilica's Instruction Set Simulator. 388 389config XTENSA_PLATFORM_XT2000 390 bool "XT2000" 391 help 392 XT2000 is the name of Tensilica's feature-rich emulation platform. 393 This hardware is capable of running a full Linux distribution. 394 395config XTENSA_PLATFORM_XTFPGA 396 bool "XTFPGA" 397 select ETHOC if ETHERNET 398 select PLATFORM_WANT_DEFAULT_MEM if !MMU 399 select SERIAL_CONSOLE 400 select XTENSA_CALIBRATE_CCOUNT 401 select PLATFORM_HAVE_XIP 402 help 403 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 404 This hardware is capable of running a full Linux distribution. 405 406endchoice 407 408config PLATFORM_NR_IRQS 409 int 410 default 3 if XTENSA_PLATFORM_XT2000 411 default 0 412 413config XTENSA_CPU_CLOCK 414 int "CPU clock rate [MHz]" 415 depends on !XTENSA_CALIBRATE_CCOUNT 416 default 16 417 418config GENERIC_CALIBRATE_DELAY 419 bool "Auto calibration of the BogoMIPS value" 420 help 421 The BogoMIPS value can easily be derived from the CPU frequency. 422 423config CMDLINE_BOOL 424 bool "Default bootloader kernel arguments" 425 426config CMDLINE 427 string "Initial kernel command string" 428 depends on CMDLINE_BOOL 429 default "console=ttyS0,38400 root=/dev/ram" 430 help 431 On some architectures (EBSA110 and CATS), there is currently no way 432 for the boot loader to pass arguments to the kernel. For these 433 architectures, you should supply some command-line options at build 434 time by entering them here. As a minimum, you should specify the 435 memory size and the root device (e.g., mem=64M root=/dev/nfs). 436 437config USE_OF 438 bool "Flattened Device Tree support" 439 select OF 440 select OF_EARLY_FLATTREE 441 help 442 Include support for flattened device tree machine descriptions. 443 444config BUILTIN_DTB_SOURCE 445 string "DTB to build into the kernel image" 446 depends on OF 447 448config PARSE_BOOTPARAM 449 bool "Parse bootparam block" 450 default y 451 help 452 Parse parameters passed to the kernel from the bootloader. It may 453 be disabled if the kernel is known to run without the bootloader. 454 455 If unsure, say Y. 456 457choice 458 prompt "Semihosting interface" 459 default XTENSA_SIMCALL_ISS 460 depends on XTENSA_PLATFORM_ISS 461 help 462 Choose semihosting interface that will be used for serial port, 463 block device and networking. 464 465config XTENSA_SIMCALL_ISS 466 bool "simcall" 467 help 468 Use simcall instruction. simcall is only available on simulators, 469 it does nothing on hardware. 470 471config XTENSA_SIMCALL_GDBIO 472 bool "GDBIO" 473 help 474 Use break instruction. It is available on real hardware when GDB 475 is attached to it via JTAG. 476 477endchoice 478 479config BLK_DEV_SIMDISK 480 tristate "Host file-based simulated block device support" 481 default n 482 depends on XTENSA_PLATFORM_ISS && BLOCK 483 help 484 Create block devices that map to files in the host file system. 485 Device binding to host file may be changed at runtime via proc 486 interface provided the device is not in use. 487 488config BLK_DEV_SIMDISK_COUNT 489 int "Number of host file-based simulated block devices" 490 range 1 10 491 depends on BLK_DEV_SIMDISK 492 default 2 493 help 494 This is the default minimal number of created block devices. 495 Kernel/module parameter 'simdisk_count' may be used to change this 496 value at runtime. More file names (but no more than 10) may be 497 specified as parameters, simdisk_count grows accordingly. 498 499config SIMDISK0_FILENAME 500 string "Host filename for the first simulated device" 501 depends on BLK_DEV_SIMDISK = y 502 default "" 503 help 504 Attach a first simdisk to a host file. Conventionally, this file 505 contains a root file system. 506 507config SIMDISK1_FILENAME 508 string "Host filename for the second simulated device" 509 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 510 default "" 511 help 512 Another simulated disk in a host file for a buildroot-independent 513 storage. 514 515config XTFPGA_LCD 516 bool "Enable XTFPGA LCD driver" 517 depends on XTENSA_PLATFORM_XTFPGA 518 default n 519 help 520 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 521 progress messages there during bootup/shutdown. It may be useful 522 during board bringup. 523 524 If unsure, say N. 525 526config XTFPGA_LCD_BASE_ADDR 527 hex "XTFPGA LCD base address" 528 depends on XTFPGA_LCD 529 default "0x0d0c0000" 530 help 531 Base address of the LCD controller inside KIO region. 532 Different boards from XTFPGA family have LCD controller at different 533 addresses. Please consult prototyping user guide for your board for 534 the correct address. Wrong address here may lead to hardware lockup. 535 536config XTFPGA_LCD_8BIT_ACCESS 537 bool "Use 8-bit access to XTFPGA LCD" 538 depends on XTFPGA_LCD 539 default n 540 help 541 LCD may be connected with 4- or 8-bit interface, 8-bit access may 542 only be used with 8-bit interface. Please consult prototyping user 543 guide for your board for the correct interface width. 544 545comment "Kernel memory layout" 546 547config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 548 bool "Initialize Xtensa MMU inside the Linux kernel code" 549 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 550 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 551 help 552 Earlier version initialized the MMU in the exception vector 553 before jumping to _startup in head.S and had an advantage that 554 it was possible to place a software breakpoint at 'reset' and 555 then enter your normal kernel breakpoints once the MMU was mapped 556 to the kernel mappings (0XC0000000). 557 558 This unfortunately won't work for U-Boot and likely also won't 559 work for using KEXEC to have a hot kernel ready for doing a 560 KDUMP. 561 562 So now the MMU is initialized in head.S but it's necessary to 563 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 564 xt-gdb can't place a Software Breakpoint in the 0XD region prior 565 to mapping the MMU and after mapping even if the area of low memory 566 was mapped gdb wouldn't remove the breakpoint on hitting it as the 567 PC wouldn't match. Since Hardware Breakpoints are recommended for 568 Linux configurations it seems reasonable to just assume they exist 569 and leave this older mechanism for unfortunate souls that choose 570 not to follow Tensilica's recommendation. 571 572 Selecting this will cause U-Boot to set the KERNEL Load and Entry 573 address at 0x00003000 instead of the mapped std of 0xD0003000. 574 575 If in doubt, say Y. 576 577config XIP_KERNEL 578 bool "Kernel Execute-In-Place from ROM" 579 depends on PLATFORM_HAVE_XIP 580 help 581 Execute-In-Place allows the kernel to run from non-volatile storage 582 directly addressable by the CPU, such as NOR flash. This saves RAM 583 space since the text section of the kernel is not loaded from flash 584 to RAM. Read-write sections, such as the data section and stack, 585 are still copied to RAM. The XIP kernel is not compressed since 586 it has to run directly from flash, so it will take more space to 587 store it. The flash address used to link the kernel object files, 588 and for storing it, is configuration dependent. Therefore, if you 589 say Y here, you must know the proper physical address where to 590 store the kernel image depending on your own flash memory usage. 591 592 Also note that the make target becomes "make xipImage" rather than 593 "make Image" or "make uImage". The final kernel binary to put in 594 ROM memory will be arch/xtensa/boot/xipImage. 595 596 If unsure, say N. 597 598config MEMMAP_CACHEATTR 599 hex "Cache attributes for the memory address space" 600 depends on !MMU 601 default 0x22222222 602 help 603 These cache attributes are set up for noMMU systems. Each hex digit 604 specifies cache attributes for the corresponding 512MB memory 605 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 606 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 607 608 Cache attribute values are specific for the MMU type. 609 For region protection MMUs: 610 1: WT cached, 611 2: cache bypass, 612 4: WB cached, 613 f: illegal. 614 For full MMU: 615 bit 0: executable, 616 bit 1: writable, 617 bits 2..3: 618 0: cache bypass, 619 1: WB cache, 620 2: WT cache, 621 3: special (c and e are illegal, f is reserved). 622 For MPU: 623 0: illegal, 624 1: WB cache, 625 2: WB, no-write-allocate cache, 626 3: WT cache, 627 4: cache bypass. 628 629config KSEG_PADDR 630 hex "Physical address of the KSEG mapping" 631 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 632 default 0x00000000 633 help 634 This is the physical address where KSEG is mapped. Please refer to 635 the chosen KSEG layout help for the required address alignment. 636 Unpacked kernel image (including vectors) must be located completely 637 within KSEG. 638 Physical memory below this address is not available to linux. 639 640 If unsure, leave the default value here. 641 642config KERNEL_VIRTUAL_ADDRESS 643 hex "Kernel virtual address" 644 depends on MMU && XIP_KERNEL 645 default 0xd0003000 646 help 647 This is the virtual address where the XIP kernel is mapped. 648 XIP kernel may be mapped into KSEG or KIO region, virtual address 649 provided here must match kernel load address provided in 650 KERNEL_LOAD_ADDRESS. 651 652config KERNEL_LOAD_ADDRESS 653 hex "Kernel load address" 654 default 0x60003000 if !MMU 655 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 656 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 657 help 658 This is the address where the kernel is loaded. 659 It is virtual address for MMUv2 configurations and physical address 660 for all other configurations. 661 662 If unsure, leave the default value here. 663 664choice 665 prompt "Relocatable vectors location" 666 default XTENSA_VECTORS_IN_TEXT 667 help 668 Choose whether relocatable vectors are merged into the kernel .text 669 or placed separately at runtime. This option does not affect 670 configurations without VECBASE register where vectors are always 671 placed at their hardware-defined locations. 672 673config XTENSA_VECTORS_IN_TEXT 674 bool "Merge relocatable vectors into kernel text" 675 depends on !MTD_XIP 676 help 677 This option puts relocatable vectors into the kernel .text section 678 with proper alignment. 679 This is a safe choice for most configurations. 680 681config XTENSA_VECTORS_SEPARATE 682 bool "Put relocatable vectors at fixed address" 683 help 684 This option puts relocatable vectors at specific virtual address. 685 Vectors are merged with the .init data in the kernel image and 686 are copied into their designated location during kernel startup. 687 Use it to put vectors into IRAM or out of FLASH on kernels with 688 XIP-aware MTD support. 689 690endchoice 691 692config VECTORS_ADDR 693 hex "Kernel vectors virtual address" 694 default 0x00000000 695 depends on XTENSA_VECTORS_SEPARATE 696 help 697 This is the virtual address of the (relocatable) vectors base. 698 It must be within KSEG if MMU is used. 699 700config XIP_DATA_ADDR 701 hex "XIP kernel data virtual address" 702 depends on XIP_KERNEL 703 default 0x00000000 704 help 705 This is the virtual address where XIP kernel data is copied. 706 It must be within KSEG if MMU is used. 707 708config PLATFORM_WANT_DEFAULT_MEM 709 def_bool n 710 711config DEFAULT_MEM_START 712 hex 713 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 714 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 715 default 0x00000000 716 help 717 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 718 in noMMU configurations. 719 720 If unsure, leave the default value here. 721 722choice 723 prompt "KSEG layout" 724 depends on MMU 725 default XTENSA_KSEG_MMU_V2 726 727config XTENSA_KSEG_MMU_V2 728 bool "MMUv2: 128MB cached + 128MB uncached" 729 help 730 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 731 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 732 without cache. 733 KSEG_PADDR must be aligned to 128MB. 734 735config XTENSA_KSEG_256M 736 bool "256MB cached + 256MB uncached" 737 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 738 help 739 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 740 with cache and to 0xc0000000 without cache. 741 KSEG_PADDR must be aligned to 256MB. 742 743config XTENSA_KSEG_512M 744 bool "512MB cached + 512MB uncached" 745 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 746 help 747 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 748 with cache and to 0xc0000000 without cache. 749 KSEG_PADDR must be aligned to 256MB. 750 751endchoice 752 753config HIGHMEM 754 bool "High Memory Support" 755 depends on MMU 756 select KMAP_LOCAL 757 help 758 Linux can use the full amount of RAM in the system by 759 default. However, the default MMUv2 setup only maps the 760 lowermost 128 MB of memory linearly to the areas starting 761 at 0xd0000000 (cached) and 0xd8000000 (uncached). 762 When there are more than 128 MB memory in the system not 763 all of it can be "permanently mapped" by the kernel. 764 The physical memory that's not permanently mapped is called 765 "high memory". 766 767 If you are compiling a kernel which will never run on a 768 machine with more than 128 MB total physical RAM, answer 769 N here. 770 771 If unsure, say Y. 772 773config FORCE_MAX_ZONEORDER 774 int "Maximum zone order" 775 default "11" 776 help 777 The kernel memory allocator divides physically contiguous memory 778 blocks into "zones", where each zone is a power of two number of 779 pages. This option selects the largest power of two that the kernel 780 keeps in the memory allocator. If you need to allocate very large 781 blocks of physically contiguous memory, then you may need to 782 increase this value. 783 784 This config option is actually maximum order plus one. For example, 785 a value of 11 means that the largest free memory block is 2^10 pages. 786 787endmenu 788 789menu "Power management options" 790 791config ARCH_HIBERNATION_POSSIBLE 792 def_bool y 793 794source "kernel/power/Kconfig" 795 796endmenu 797