1# SPDX-License-Identifier: GPL-2.0 2config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_CPU_CACHE_ALIASING 6 select ARCH_HAS_BINFMT_FLAT if !MMU 7 select ARCH_HAS_CURRENT_STACK_POINTER 8 select ARCH_HAS_DEBUG_VM_PGTABLE 9 select ARCH_HAS_DMA_PREP_COHERENT if MMU 10 select ARCH_HAS_GCOV_PROFILE_ALL 11 select ARCH_HAS_KCOV 12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 14 select ARCH_HAS_DMA_SET_UNCACHED if MMU 15 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN 16 select ARCH_HAS_STRNLEN_USER 17 select ARCH_USE_MEMTEST 18 select ARCH_USE_QUEUED_RWLOCKS 19 select ARCH_USE_QUEUED_SPINLOCKS 20 select ARCH_WANT_IPC_PARSE_VERSION 21 select BUILDTIME_TABLE_SORT 22 select CLONE_BACKWARDS 23 select COMMON_CLK 24 select DMA_NONCOHERENT_MMAP if MMU 25 select GENERIC_ATOMIC64 26 select GENERIC_IRQ_SHOW 27 select GENERIC_LIB_CMPDI2 28 select GENERIC_LIB_MULDI3 29 select GENERIC_LIB_UCMPDI2 30 select GENERIC_PCI_IOMAP 31 select GENERIC_SCHED_CLOCK 32 select GENERIC_IOREMAP if MMU 33 select HAVE_ARCH_AUDITSYSCALL 34 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 35 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 36 select HAVE_ARCH_KCSAN 37 select HAVE_ARCH_SECCOMP_FILTER 38 select HAVE_ARCH_TRACEHOOK 39 select HAVE_ASM_MODVERSIONS 40 select HAVE_CONTEXT_TRACKING_USER 41 select HAVE_DEBUG_KMEMLEAK 42 select HAVE_DMA_CONTIGUOUS 43 select HAVE_EXIT_THREAD 44 select HAVE_FUNCTION_TRACER 45 select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000 46 select HAVE_HW_BREAKPOINT if PERF_EVENTS 47 select HAVE_IRQ_TIME_ACCOUNTING 48 select HAVE_PAGE_SIZE_4KB 49 select HAVE_PCI 50 select HAVE_PERF_EVENTS 51 select HAVE_STACKPROTECTOR 52 select HAVE_SYSCALL_TRACEPOINTS 53 select HAVE_VIRT_CPU_ACCOUNTING_GEN 54 select IRQ_DOMAIN 55 select LOCK_MM_AND_FIND_VMA 56 select MODULES_USE_ELF_RELA 57 select PERF_USE_VMALLOC 58 select TRACE_IRQFLAGS_SUPPORT 59 help 60 Xtensa processors are 32-bit RISC machines designed by Tensilica 61 primarily for embedded systems. These processors are both 62 configurable and extensible. The Linux port to the Xtensa 63 architecture supports all processor configurations and extensions, 64 with reasonable minimum requirements. The Xtensa Linux project has 65 a home page at <http://www.linux-xtensa.org/>. 66 67config GENERIC_HWEIGHT 68 def_bool y 69 70config ARCH_HAS_ILOG2_U32 71 def_bool n 72 73config ARCH_HAS_ILOG2_U64 74 def_bool n 75 76config ARCH_MTD_XIP 77 def_bool y 78 79config NO_IOPORT_MAP 80 def_bool n 81 82config HZ 83 int 84 default 100 85 86config LOCKDEP_SUPPORT 87 def_bool y 88 89config STACKTRACE_SUPPORT 90 def_bool y 91 92config MMU 93 def_bool n 94 select PFAULT 95 96config HAVE_XTENSA_GPIO32 97 def_bool n 98 99config KASAN_SHADOW_OFFSET 100 hex 101 default 0x6e400000 102 103config CPU_BIG_ENDIAN 104 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1) 105 106config CPU_LITTLE_ENDIAN 107 def_bool !CPU_BIG_ENDIAN 108 109config CC_HAVE_CALL0_ABI 110 def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1) 111 112menu "Processor type and features" 113 114choice 115 prompt "Xtensa Processor Configuration" 116 default XTENSA_VARIANT_FSF 117 118config XTENSA_VARIANT_FSF 119 bool "fsf - default (not generic) configuration" 120 select MMU 121 122config XTENSA_VARIANT_DC232B 123 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 124 select MMU 125 select HAVE_XTENSA_GPIO32 126 help 127 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 128 129config XTENSA_VARIANT_DC233C 130 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 131 select MMU 132 select HAVE_XTENSA_GPIO32 133 help 134 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 135 136config XTENSA_VARIANT_CUSTOM 137 bool "Custom Xtensa processor configuration" 138 select HAVE_XTENSA_GPIO32 139 help 140 Select this variant to use a custom Xtensa processor configuration. 141 You will be prompted for a processor variant CORENAME. 142endchoice 143 144config XTENSA_VARIANT_CUSTOM_NAME 145 string "Xtensa Processor Custom Core Variant Name" 146 depends on XTENSA_VARIANT_CUSTOM 147 help 148 Provide the name of a custom Xtensa processor variant. 149 This CORENAME selects arch/xtensa/variants/CORENAME. 150 Don't forget you have to select MMU if you have one. 151 152config XTENSA_VARIANT_NAME 153 string 154 default "dc232b" if XTENSA_VARIANT_DC232B 155 default "dc233c" if XTENSA_VARIANT_DC233C 156 default "fsf" if XTENSA_VARIANT_FSF 157 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 158 159config XTENSA_VARIANT_MMU 160 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 161 depends on XTENSA_VARIANT_CUSTOM 162 default y 163 select MMU 164 help 165 Build a Conventional Kernel with full MMU support, 166 ie: it supports a TLB with auto-loading, page protection. 167 168config XTENSA_VARIANT_HAVE_PERF_EVENTS 169 bool "Core variant has Performance Monitor Module" 170 depends on XTENSA_VARIANT_CUSTOM 171 default n 172 help 173 Enable if core variant has Performance Monitor Module with 174 External Registers Interface. 175 176 If unsure, say N. 177 178config XTENSA_FAKE_NMI 179 bool "Treat PMM IRQ as NMI" 180 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 181 default n 182 help 183 If PMM IRQ is the only IRQ at EXCM level it is safe to 184 treat it as NMI, which improves accuracy of profiling. 185 186 If there are other interrupts at or above PMM IRQ priority level 187 but not above the EXCM level, PMM IRQ still may be treated as NMI, 188 but only if these IRQs are not used. There will be a build warning 189 saying that this is not safe, and a bugcheck if one of these IRQs 190 actually fire. 191 192 If unsure, say N. 193 194config PFAULT 195 bool "Handle protection faults" if EXPERT && !MMU 196 default y 197 help 198 Handle protection faults. MMU configurations must enable it. 199 noMMU configurations may disable it if used memory map never 200 generates protection faults or faults are always fatal. 201 202 If unsure, say Y. 203 204config XTENSA_UNALIGNED_USER 205 bool "Unaligned memory access in user space" 206 help 207 The Xtensa architecture currently does not handle unaligned 208 memory accesses in hardware but through an exception handler. 209 Per default, unaligned memory accesses are disabled in user space. 210 211 Say Y here to enable unaligned memory access in user space. 212 213config XTENSA_LOAD_STORE 214 bool "Load/store exception handler for memory only readable with l32" 215 help 216 The Xtensa architecture only allows reading memory attached to its 217 instruction bus with l32r and l32i instructions, all other 218 instructions raise an exception with the LoadStoreErrorCause code. 219 This makes it hard to use some configurations, e.g. store string 220 literals in FLASH memory attached to the instruction bus. 221 222 Say Y here to enable exception handler that allows transparent 223 byte and 2-byte access to memory attached to instruction bus. 224 225config HAVE_SMP 226 bool "System Supports SMP (MX)" 227 depends on XTENSA_VARIANT_CUSTOM 228 select XTENSA_MX 229 help 230 This option is used to indicate that the system-on-a-chip (SOC) 231 supports Multiprocessing. Multiprocessor support implemented above 232 the CPU core definition and currently needs to be selected manually. 233 234 Multiprocessor support is implemented with external cache and 235 interrupt controllers. 236 237 The MX interrupt distributer adds Interprocessor Interrupts 238 and causes the IRQ numbers to be increased by 4 for devices 239 like the open cores ethernet driver and the serial interface. 240 241 You still have to select "Enable SMP" to enable SMP on this SOC. 242 243config SMP 244 bool "Enable Symmetric multi-processing support" 245 depends on HAVE_SMP 246 select GENERIC_SMP_IDLE_THREAD 247 help 248 Enabled SMP Software; allows more than one CPU/CORE 249 to be activated during startup. 250 251config NR_CPUS 252 depends on SMP 253 int "Maximum number of CPUs (2-32)" 254 range 2 32 255 default "4" 256 257config HOTPLUG_CPU 258 bool "Enable CPU hotplug support" 259 depends on SMP 260 help 261 Say Y here to allow turning CPUs off and on. CPUs can be 262 controlled through /sys/devices/system/cpu. 263 264 Say N if you want to disable CPU hotplug. 265 266config SECONDARY_RESET_VECTOR 267 bool "Secondary cores use alternative reset vector" 268 default y 269 depends on HAVE_SMP 270 help 271 Secondary cores may be configured to use alternative reset vector, 272 or all cores may use primary reset vector. 273 Say Y here to supply handler for the alternative reset location. 274 275config FAST_SYSCALL_XTENSA 276 bool "Enable fast atomic syscalls" 277 default n 278 help 279 fast_syscall_xtensa is a syscall that can make atomic operations 280 on UP kernel when processor has no s32c1i support. 281 282 This syscall is deprecated. It may have issues when called with 283 invalid arguments. It is provided only for backwards compatibility. 284 Only enable it if your userspace software requires it. 285 286 If unsure, say N. 287 288config FAST_SYSCALL_SPILL_REGISTERS 289 bool "Enable spill registers syscall" 290 default n 291 help 292 fast_syscall_spill_registers is a syscall that spills all active 293 register windows of a calling userspace task onto its stack. 294 295 This syscall is deprecated. It may have issues when called with 296 invalid arguments. It is provided only for backwards compatibility. 297 Only enable it if your userspace software requires it. 298 299 If unsure, say N. 300 301choice 302 prompt "Kernel ABI" 303 default KERNEL_ABI_DEFAULT 304 help 305 Select ABI for the kernel code. This ABI is independent of the 306 supported userspace ABI and any combination of the 307 kernel/userspace ABI is possible and should work. 308 309 In case both kernel and userspace support only call0 ABI 310 all register windows support code will be omitted from the 311 build. 312 313 If unsure, choose the default ABI. 314 315config KERNEL_ABI_DEFAULT 316 bool "Default ABI" 317 help 318 Select this option to compile kernel code with the default ABI 319 selected for the toolchain. 320 Normally cores with windowed registers option use windowed ABI and 321 cores without it use call0 ABI. 322 323config KERNEL_ABI_CALL0 324 bool "Call0 ABI" if CC_HAVE_CALL0_ABI 325 help 326 Select this option to compile kernel code with call0 ABI even with 327 toolchain that defaults to windowed ABI. 328 When this option is not selected the default toolchain ABI will 329 be used for the kernel code. 330 331endchoice 332 333config USER_ABI_CALL0 334 bool 335 336choice 337 prompt "Userspace ABI" 338 default USER_ABI_DEFAULT 339 help 340 Select supported userspace ABI. 341 342 If unsure, choose the default ABI. 343 344config USER_ABI_DEFAULT 345 bool "Default ABI only" 346 help 347 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 348 call0 ABI binaries may be run on such kernel, but signal delivery 349 will not work correctly for them. 350 351config USER_ABI_CALL0_ONLY 352 bool "Call0 ABI only" 353 select USER_ABI_CALL0 354 help 355 Select this option to support only call0 ABI in userspace. 356 Windowed ABI binaries will crash with a segfault caused by 357 an illegal instruction exception on the first 'entry' opcode. 358 359 Choose this option if you're planning to run only user code 360 built with call0 ABI. 361 362config USER_ABI_CALL0_PROBE 363 bool "Support both windowed and call0 ABI by probing" 364 select USER_ABI_CALL0 365 help 366 Select this option to support both windowed and call0 userspace 367 ABIs. When enabled all processes are started with PS.WOE disabled 368 and a fast user exception handler for an illegal instruction is 369 used to turn on PS.WOE bit on the first 'entry' opcode executed by 370 the userspace. 371 372 This option should be enabled for the kernel that must support 373 both call0 and windowed ABIs in userspace at the same time. 374 375 Note that Xtensa ISA does not guarantee that entry opcode will 376 raise an illegal instruction exception on cores with XEA2 when 377 PS.WOE is disabled, check whether the target core supports it. 378 379endchoice 380 381endmenu 382 383config XTENSA_CALIBRATE_CCOUNT 384 def_bool n 385 help 386 On some platforms (XT2000, for example), the CPU clock rate can 387 vary. The frequency can be determined, however, by measuring 388 against a well known, fixed frequency, such as an UART oscillator. 389 390config SERIAL_CONSOLE 391 def_bool n 392 393config PLATFORM_HAVE_XIP 394 def_bool n 395 396menu "Platform options" 397 398choice 399 prompt "Xtensa System Type" 400 default XTENSA_PLATFORM_ISS 401 402config XTENSA_PLATFORM_ISS 403 bool "ISS" 404 select XTENSA_CALIBRATE_CCOUNT 405 select SERIAL_CONSOLE 406 help 407 ISS is an acronym for Tensilica's Instruction Set Simulator. 408 409config XTENSA_PLATFORM_XT2000 410 bool "XT2000" 411 help 412 XT2000 is the name of Tensilica's feature-rich emulation platform. 413 This hardware is capable of running a full Linux distribution. 414 415config XTENSA_PLATFORM_XTFPGA 416 bool "XTFPGA" 417 select ETHOC if ETHERNET 418 select PLATFORM_WANT_DEFAULT_MEM if !MMU 419 select SERIAL_CONSOLE 420 select XTENSA_CALIBRATE_CCOUNT 421 select PLATFORM_HAVE_XIP 422 help 423 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 424 This hardware is capable of running a full Linux distribution. 425 426endchoice 427 428config PLATFORM_NR_IRQS 429 int 430 default 3 if XTENSA_PLATFORM_XT2000 431 default 0 432 433config XTENSA_CPU_CLOCK 434 int "CPU clock rate [MHz]" 435 depends on !XTENSA_CALIBRATE_CCOUNT 436 default 16 437 438config GENERIC_CALIBRATE_DELAY 439 bool "Auto calibration of the BogoMIPS value" 440 help 441 The BogoMIPS value can easily be derived from the CPU frequency. 442 443config CMDLINE_BOOL 444 bool "Default bootloader kernel arguments" 445 446config CMDLINE 447 string "Initial kernel command string" 448 depends on CMDLINE_BOOL 449 default "console=ttyS0,38400 root=/dev/ram" 450 help 451 On some architectures (EBSA110 and CATS), there is currently no way 452 for the boot loader to pass arguments to the kernel. For these 453 architectures, you should supply some command-line options at build 454 time by entering them here. As a minimum, you should specify the 455 memory size and the root device (e.g., mem=64M root=/dev/nfs). 456 457config USE_OF 458 bool "Flattened Device Tree support" 459 select OF 460 select OF_EARLY_FLATTREE 461 help 462 Include support for flattened device tree machine descriptions. 463 464config BUILTIN_DTB_SOURCE 465 string "DTB to build into the kernel image" 466 depends on OF 467 468config PARSE_BOOTPARAM 469 bool "Parse bootparam block" 470 default y 471 help 472 Parse parameters passed to the kernel from the bootloader. It may 473 be disabled if the kernel is known to run without the bootloader. 474 475 If unsure, say Y. 476 477choice 478 prompt "Semihosting interface" 479 default XTENSA_SIMCALL_ISS 480 depends on XTENSA_PLATFORM_ISS 481 help 482 Choose semihosting interface that will be used for serial port, 483 block device and networking. 484 485config XTENSA_SIMCALL_ISS 486 bool "simcall" 487 help 488 Use simcall instruction. simcall is only available on simulators, 489 it does nothing on hardware. 490 491config XTENSA_SIMCALL_GDBIO 492 bool "GDBIO" 493 help 494 Use break instruction. It is available on real hardware when GDB 495 is attached to it via JTAG. 496 497endchoice 498 499config BLK_DEV_SIMDISK 500 tristate "Host file-based simulated block device support" 501 default n 502 depends on XTENSA_PLATFORM_ISS && BLOCK 503 help 504 Create block devices that map to files in the host file system. 505 Device binding to host file may be changed at runtime via proc 506 interface provided the device is not in use. 507 508config BLK_DEV_SIMDISK_COUNT 509 int "Number of host file-based simulated block devices" 510 range 1 10 511 depends on BLK_DEV_SIMDISK 512 default 2 513 help 514 This is the default minimal number of created block devices. 515 Kernel/module parameter 'simdisk_count' may be used to change this 516 value at runtime. More file names (but no more than 10) may be 517 specified as parameters, simdisk_count grows accordingly. 518 519config SIMDISK0_FILENAME 520 string "Host filename for the first simulated device" 521 depends on BLK_DEV_SIMDISK = y 522 default "" 523 help 524 Attach a first simdisk to a host file. Conventionally, this file 525 contains a root file system. 526 527config SIMDISK1_FILENAME 528 string "Host filename for the second simulated device" 529 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 530 default "" 531 help 532 Another simulated disk in a host file for a buildroot-independent 533 storage. 534 535config XTFPGA_LCD 536 bool "Enable XTFPGA LCD driver" 537 depends on XTENSA_PLATFORM_XTFPGA 538 default n 539 help 540 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 541 progress messages there during bootup/shutdown. It may be useful 542 during board bringup. 543 544 If unsure, say N. 545 546config XTFPGA_LCD_BASE_ADDR 547 hex "XTFPGA LCD base address" 548 depends on XTFPGA_LCD 549 default "0x0d0c0000" 550 help 551 Base address of the LCD controller inside KIO region. 552 Different boards from XTFPGA family have LCD controller at different 553 addresses. Please consult prototyping user guide for your board for 554 the correct address. Wrong address here may lead to hardware lockup. 555 556config XTFPGA_LCD_8BIT_ACCESS 557 bool "Use 8-bit access to XTFPGA LCD" 558 depends on XTFPGA_LCD 559 default n 560 help 561 LCD may be connected with 4- or 8-bit interface, 8-bit access may 562 only be used with 8-bit interface. Please consult prototyping user 563 guide for your board for the correct interface width. 564 565comment "Kernel memory layout" 566 567config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 568 bool "Initialize Xtensa MMU inside the Linux kernel code" 569 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 570 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 571 help 572 Earlier version initialized the MMU in the exception vector 573 before jumping to _startup in head.S and had an advantage that 574 it was possible to place a software breakpoint at 'reset' and 575 then enter your normal kernel breakpoints once the MMU was mapped 576 to the kernel mappings (0XC0000000). 577 578 This unfortunately won't work for U-Boot and likely also won't 579 work for using KEXEC to have a hot kernel ready for doing a 580 KDUMP. 581 582 So now the MMU is initialized in head.S but it's necessary to 583 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 584 xt-gdb can't place a Software Breakpoint in the 0XD region prior 585 to mapping the MMU and after mapping even if the area of low memory 586 was mapped gdb wouldn't remove the breakpoint on hitting it as the 587 PC wouldn't match. Since Hardware Breakpoints are recommended for 588 Linux configurations it seems reasonable to just assume they exist 589 and leave this older mechanism for unfortunate souls that choose 590 not to follow Tensilica's recommendation. 591 592 Selecting this will cause U-Boot to set the KERNEL Load and Entry 593 address at 0x00003000 instead of the mapped std of 0xD0003000. 594 595 If in doubt, say Y. 596 597config XIP_KERNEL 598 bool "Kernel Execute-In-Place from ROM" 599 depends on PLATFORM_HAVE_XIP 600 help 601 Execute-In-Place allows the kernel to run from non-volatile storage 602 directly addressable by the CPU, such as NOR flash. This saves RAM 603 space since the text section of the kernel is not loaded from flash 604 to RAM. Read-write sections, such as the data section and stack, 605 are still copied to RAM. The XIP kernel is not compressed since 606 it has to run directly from flash, so it will take more space to 607 store it. The flash address used to link the kernel object files, 608 and for storing it, is configuration dependent. Therefore, if you 609 say Y here, you must know the proper physical address where to 610 store the kernel image depending on your own flash memory usage. 611 612 Also note that the make target becomes "make xipImage" rather than 613 "make Image" or "make uImage". The final kernel binary to put in 614 ROM memory will be arch/xtensa/boot/xipImage. 615 616 If unsure, say N. 617 618config MEMMAP_CACHEATTR 619 hex "Cache attributes for the memory address space" 620 depends on !MMU 621 default 0x22222222 622 help 623 These cache attributes are set up for noMMU systems. Each hex digit 624 specifies cache attributes for the corresponding 512MB memory 625 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 626 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 627 628 Cache attribute values are specific for the MMU type. 629 For region protection MMUs: 630 1: WT cached, 631 2: cache bypass, 632 4: WB cached, 633 f: illegal. 634 For full MMU: 635 bit 0: executable, 636 bit 1: writable, 637 bits 2..3: 638 0: cache bypass, 639 1: WB cache, 640 2: WT cache, 641 3: special (c and e are illegal, f is reserved). 642 For MPU: 643 0: illegal, 644 1: WB cache, 645 2: WB, no-write-allocate cache, 646 3: WT cache, 647 4: cache bypass. 648 649config KSEG_PADDR 650 hex "Physical address of the KSEG mapping" 651 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 652 default 0x00000000 653 help 654 This is the physical address where KSEG is mapped. Please refer to 655 the chosen KSEG layout help for the required address alignment. 656 Unpacked kernel image (including vectors) must be located completely 657 within KSEG. 658 Physical memory below this address is not available to linux. 659 660 If unsure, leave the default value here. 661 662config KERNEL_VIRTUAL_ADDRESS 663 hex "Kernel virtual address" 664 depends on MMU && XIP_KERNEL 665 default 0xd0003000 666 help 667 This is the virtual address where the XIP kernel is mapped. 668 XIP kernel may be mapped into KSEG or KIO region, virtual address 669 provided here must match kernel load address provided in 670 KERNEL_LOAD_ADDRESS. 671 672config KERNEL_LOAD_ADDRESS 673 hex "Kernel load address" 674 default 0x60003000 if !MMU 675 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 676 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 677 help 678 This is the address where the kernel is loaded. 679 It is virtual address for MMUv2 configurations and physical address 680 for all other configurations. 681 682 If unsure, leave the default value here. 683 684choice 685 prompt "Relocatable vectors location" 686 default XTENSA_VECTORS_IN_TEXT 687 help 688 Choose whether relocatable vectors are merged into the kernel .text 689 or placed separately at runtime. This option does not affect 690 configurations without VECBASE register where vectors are always 691 placed at their hardware-defined locations. 692 693config XTENSA_VECTORS_IN_TEXT 694 bool "Merge relocatable vectors into kernel text" 695 depends on !MTD_XIP 696 help 697 This option puts relocatable vectors into the kernel .text section 698 with proper alignment. 699 This is a safe choice for most configurations. 700 701config XTENSA_VECTORS_SEPARATE 702 bool "Put relocatable vectors at fixed address" 703 help 704 This option puts relocatable vectors at specific virtual address. 705 Vectors are merged with the .init data in the kernel image and 706 are copied into their designated location during kernel startup. 707 Use it to put vectors into IRAM or out of FLASH on kernels with 708 XIP-aware MTD support. 709 710endchoice 711 712config VECTORS_ADDR 713 hex "Kernel vectors virtual address" 714 default 0x00000000 715 depends on XTENSA_VECTORS_SEPARATE 716 help 717 This is the virtual address of the (relocatable) vectors base. 718 It must be within KSEG if MMU is used. 719 720config XIP_DATA_ADDR 721 hex "XIP kernel data virtual address" 722 depends on XIP_KERNEL 723 default 0x00000000 724 help 725 This is the virtual address where XIP kernel data is copied. 726 It must be within KSEG if MMU is used. 727 728config PLATFORM_WANT_DEFAULT_MEM 729 def_bool n 730 731config DEFAULT_MEM_START 732 hex 733 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 734 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 735 default 0x00000000 736 help 737 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 738 in noMMU configurations. 739 740 If unsure, leave the default value here. 741 742choice 743 prompt "KSEG layout" 744 depends on MMU 745 default XTENSA_KSEG_MMU_V2 746 747config XTENSA_KSEG_MMU_V2 748 bool "MMUv2: 128MB cached + 128MB uncached" 749 help 750 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 751 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 752 without cache. 753 KSEG_PADDR must be aligned to 128MB. 754 755config XTENSA_KSEG_256M 756 bool "256MB cached + 256MB uncached" 757 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 758 help 759 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 760 with cache and to 0xc0000000 without cache. 761 KSEG_PADDR must be aligned to 256MB. 762 763config XTENSA_KSEG_512M 764 bool "512MB cached + 512MB uncached" 765 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 766 help 767 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 768 with cache and to 0xc0000000 without cache. 769 KSEG_PADDR must be aligned to 256MB. 770 771endchoice 772 773config HIGHMEM 774 bool "High Memory Support" 775 depends on MMU 776 select KMAP_LOCAL 777 help 778 Linux can use the full amount of RAM in the system by 779 default. However, the default MMUv2 setup only maps the 780 lowermost 128 MB of memory linearly to the areas starting 781 at 0xd0000000 (cached) and 0xd8000000 (uncached). 782 When there are more than 128 MB memory in the system not 783 all of it can be "permanently mapped" by the kernel. 784 The physical memory that's not permanently mapped is called 785 "high memory". 786 787 If you are compiling a kernel which will never run on a 788 machine with more than 128 MB total physical RAM, answer 789 N here. 790 791 If unsure, say Y. 792 793config ARCH_FORCE_MAX_ORDER 794 int "Order of maximal physically contiguous allocations" 795 default "10" 796 help 797 The kernel page allocator limits the size of maximal physically 798 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 799 defines the maximal power of two of number of pages that can be 800 allocated as a single contiguous block. This option allows 801 overriding the default setting when ability to allocate very 802 large blocks of physically contiguous memory is required. 803 804 Don't change if unsure. 805 806endmenu 807 808menu "Power management options" 809 810config ARCH_HIBERNATION_POSSIBLE 811 def_bool y 812 813source "kernel/power/Kconfig" 814 815endmenu 816