1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Core of Xen paravirt_ops implementation. 4 * 5 * This file contains the xen_paravirt_ops structure itself, and the 6 * implementations for: 7 * - privileged instructions 8 * - interrupt flags 9 * - segment operations 10 * - booting and setup 11 * 12 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/preempt.h> 20 #include <linux/hardirq.h> 21 #include <linux/percpu.h> 22 #include <linux/delay.h> 23 #include <linux/start_kernel.h> 24 #include <linux/sched.h> 25 #include <linux/kprobes.h> 26 #include <linux/memblock.h> 27 #include <linux/export.h> 28 #include <linux/mm.h> 29 #include <linux/page-flags.h> 30 #include <linux/highmem.h> 31 #include <linux/pci.h> 32 #include <linux/gfp.h> 33 #include <linux/edd.h> 34 #include <linux/objtool.h> 35 36 #include <xen/xen.h> 37 #include <xen/events.h> 38 #include <xen/interface/xen.h> 39 #include <xen/interface/version.h> 40 #include <xen/interface/physdev.h> 41 #include <xen/interface/vcpu.h> 42 #include <xen/interface/memory.h> 43 #include <xen/interface/nmi.h> 44 #include <xen/interface/xen-mca.h> 45 #include <xen/features.h> 46 #include <xen/page.h> 47 #include <xen/hvc-console.h> 48 #include <xen/acpi.h> 49 50 #include <asm/paravirt.h> 51 #include <asm/apic.h> 52 #include <asm/page.h> 53 #include <asm/xen/pci.h> 54 #include <asm/xen/hypercall.h> 55 #include <asm/xen/hypervisor.h> 56 #include <asm/xen/cpuid.h> 57 #include <asm/fixmap.h> 58 #include <asm/processor.h> 59 #include <asm/proto.h> 60 #include <asm/msr-index.h> 61 #include <asm/traps.h> 62 #include <asm/setup.h> 63 #include <asm/desc.h> 64 #include <asm/pgalloc.h> 65 #include <asm/tlbflush.h> 66 #include <asm/reboot.h> 67 #include <asm/stackprotector.h> 68 #include <asm/hypervisor.h> 69 #include <asm/mach_traps.h> 70 #include <asm/mwait.h> 71 #include <asm/pci_x86.h> 72 #include <asm/cpu.h> 73 #ifdef CONFIG_X86_IOPL_IOPERM 74 #include <asm/io_bitmap.h> 75 #endif 76 77 #ifdef CONFIG_ACPI 78 #include <linux/acpi.h> 79 #include <asm/acpi.h> 80 #include <acpi/pdc_intel.h> 81 #include <acpi/processor.h> 82 #include <xen/interface/platform.h> 83 #endif 84 85 #include "xen-ops.h" 86 #include "mmu.h" 87 #include "smp.h" 88 #include "multicalls.h" 89 #include "pmu.h" 90 91 #include "../kernel/cpu/cpu.h" /* get_cpu_cap() */ 92 93 void *xen_initial_gdt; 94 95 static int xen_cpu_up_prepare_pv(unsigned int cpu); 96 static int xen_cpu_dead_pv(unsigned int cpu); 97 98 struct tls_descs { 99 struct desc_struct desc[3]; 100 }; 101 102 /* 103 * Updating the 3 TLS descriptors in the GDT on every task switch is 104 * surprisingly expensive so we avoid updating them if they haven't 105 * changed. Since Xen writes different descriptors than the one 106 * passed in the update_descriptor hypercall we keep shadow copies to 107 * compare against. 108 */ 109 static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); 110 111 static void __init xen_pv_init_platform(void) 112 { 113 populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP)); 114 115 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info); 116 HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); 117 118 /* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */ 119 xen_vcpu_info_reset(0); 120 121 /* pvclock is in shared info area */ 122 xen_init_time_ops(); 123 } 124 125 static void __init xen_pv_guest_late_init(void) 126 { 127 #ifndef CONFIG_SMP 128 /* Setup shared vcpu info for non-smp configurations */ 129 xen_setup_vcpu_info_placement(); 130 #endif 131 } 132 133 static __read_mostly unsigned int cpuid_leaf5_ecx_val; 134 static __read_mostly unsigned int cpuid_leaf5_edx_val; 135 136 static void xen_cpuid(unsigned int *ax, unsigned int *bx, 137 unsigned int *cx, unsigned int *dx) 138 { 139 unsigned maskebx = ~0; 140 141 /* 142 * Mask out inconvenient features, to try and disable as many 143 * unsupported kernel subsystems as possible. 144 */ 145 switch (*ax) { 146 case CPUID_MWAIT_LEAF: 147 /* Synthesize the values.. */ 148 *ax = 0; 149 *bx = 0; 150 *cx = cpuid_leaf5_ecx_val; 151 *dx = cpuid_leaf5_edx_val; 152 return; 153 154 case 0xb: 155 /* Suppress extended topology stuff */ 156 maskebx = 0; 157 break; 158 } 159 160 asm(XEN_EMULATE_PREFIX "cpuid" 161 : "=a" (*ax), 162 "=b" (*bx), 163 "=c" (*cx), 164 "=d" (*dx) 165 : "0" (*ax), "2" (*cx)); 166 167 *bx &= maskebx; 168 } 169 STACK_FRAME_NON_STANDARD(xen_cpuid); /* XEN_EMULATE_PREFIX */ 170 171 static bool __init xen_check_mwait(void) 172 { 173 #ifdef CONFIG_ACPI 174 struct xen_platform_op op = { 175 .cmd = XENPF_set_processor_pminfo, 176 .u.set_pminfo.id = -1, 177 .u.set_pminfo.type = XEN_PM_PDC, 178 }; 179 uint32_t buf[3]; 180 unsigned int ax, bx, cx, dx; 181 unsigned int mwait_mask; 182 183 /* We need to determine whether it is OK to expose the MWAIT 184 * capability to the kernel to harvest deeper than C3 states from ACPI 185 * _CST using the processor_harvest_xen.c module. For this to work, we 186 * need to gather the MWAIT_LEAF values (which the cstate.c code 187 * checks against). The hypervisor won't expose the MWAIT flag because 188 * it would break backwards compatibility; so we will find out directly 189 * from the hardware and hypercall. 190 */ 191 if (!xen_initial_domain()) 192 return false; 193 194 /* 195 * When running under platform earlier than Xen4.2, do not expose 196 * mwait, to avoid the risk of loading native acpi pad driver 197 */ 198 if (!xen_running_on_version_or_later(4, 2)) 199 return false; 200 201 ax = 1; 202 cx = 0; 203 204 native_cpuid(&ax, &bx, &cx, &dx); 205 206 mwait_mask = (1 << (X86_FEATURE_EST % 32)) | 207 (1 << (X86_FEATURE_MWAIT % 32)); 208 209 if ((cx & mwait_mask) != mwait_mask) 210 return false; 211 212 /* We need to emulate the MWAIT_LEAF and for that we need both 213 * ecx and edx. The hypercall provides only partial information. 214 */ 215 216 ax = CPUID_MWAIT_LEAF; 217 bx = 0; 218 cx = 0; 219 dx = 0; 220 221 native_cpuid(&ax, &bx, &cx, &dx); 222 223 /* Ask the Hypervisor whether to clear ACPI_PDC_C_C2C3_FFH. If so, 224 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. 225 */ 226 buf[0] = ACPI_PDC_REVISION_ID; 227 buf[1] = 1; 228 buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP); 229 230 set_xen_guest_handle(op.u.set_pminfo.pdc, buf); 231 232 if ((HYPERVISOR_platform_op(&op) == 0) && 233 (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) { 234 cpuid_leaf5_ecx_val = cx; 235 cpuid_leaf5_edx_val = dx; 236 } 237 return true; 238 #else 239 return false; 240 #endif 241 } 242 243 static bool __init xen_check_xsave(void) 244 { 245 unsigned int cx, xsave_mask; 246 247 cx = cpuid_ecx(1); 248 249 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) | 250 (1 << (X86_FEATURE_OSXSAVE % 32)); 251 252 /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ 253 return (cx & xsave_mask) == xsave_mask; 254 } 255 256 static void __init xen_init_capabilities(void) 257 { 258 setup_force_cpu_cap(X86_FEATURE_XENPV); 259 setup_clear_cpu_cap(X86_FEATURE_DCA); 260 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF); 261 setup_clear_cpu_cap(X86_FEATURE_MTRR); 262 setup_clear_cpu_cap(X86_FEATURE_ACC); 263 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 264 setup_clear_cpu_cap(X86_FEATURE_SME); 265 266 /* 267 * Xen PV would need some work to support PCID: CR3 handling as well 268 * as xen_flush_tlb_others() would need updating. 269 */ 270 setup_clear_cpu_cap(X86_FEATURE_PCID); 271 272 if (!xen_initial_domain()) 273 setup_clear_cpu_cap(X86_FEATURE_ACPI); 274 275 if (xen_check_mwait()) 276 setup_force_cpu_cap(X86_FEATURE_MWAIT); 277 else 278 setup_clear_cpu_cap(X86_FEATURE_MWAIT); 279 280 if (!xen_check_xsave()) { 281 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 282 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE); 283 } 284 } 285 286 static noinstr void xen_set_debugreg(int reg, unsigned long val) 287 { 288 HYPERVISOR_set_debugreg(reg, val); 289 } 290 291 static noinstr unsigned long xen_get_debugreg(int reg) 292 { 293 return HYPERVISOR_get_debugreg(reg); 294 } 295 296 static void xen_end_context_switch(struct task_struct *next) 297 { 298 xen_mc_flush(); 299 paravirt_end_context_switch(next); 300 } 301 302 static unsigned long xen_store_tr(void) 303 { 304 return 0; 305 } 306 307 /* 308 * Set the page permissions for a particular virtual address. If the 309 * address is a vmalloc mapping (or other non-linear mapping), then 310 * find the linear mapping of the page and also set its protections to 311 * match. 312 */ 313 static void set_aliased_prot(void *v, pgprot_t prot) 314 { 315 int level; 316 pte_t *ptep; 317 pte_t pte; 318 unsigned long pfn; 319 unsigned char dummy; 320 void *va; 321 322 ptep = lookup_address((unsigned long)v, &level); 323 BUG_ON(ptep == NULL); 324 325 pfn = pte_pfn(*ptep); 326 pte = pfn_pte(pfn, prot); 327 328 /* 329 * Careful: update_va_mapping() will fail if the virtual address 330 * we're poking isn't populated in the page tables. We don't 331 * need to worry about the direct map (that's always in the page 332 * tables), but we need to be careful about vmap space. In 333 * particular, the top level page table can lazily propagate 334 * entries between processes, so if we've switched mms since we 335 * vmapped the target in the first place, we might not have the 336 * top-level page table entry populated. 337 * 338 * We disable preemption because we want the same mm active when 339 * we probe the target and when we issue the hypercall. We'll 340 * have the same nominal mm, but if we're a kernel thread, lazy 341 * mm dropping could change our pgd. 342 * 343 * Out of an abundance of caution, this uses __get_user() to fault 344 * in the target address just in case there's some obscure case 345 * in which the target address isn't readable. 346 */ 347 348 preempt_disable(); 349 350 copy_from_kernel_nofault(&dummy, v, 1); 351 352 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) 353 BUG(); 354 355 va = __va(PFN_PHYS(pfn)); 356 357 if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 358 BUG(); 359 360 preempt_enable(); 361 } 362 363 static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) 364 { 365 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 366 int i; 367 368 /* 369 * We need to mark the all aliases of the LDT pages RO. We 370 * don't need to call vm_flush_aliases(), though, since that's 371 * only responsible for flushing aliases out the TLBs, not the 372 * page tables, and Xen will flush the TLB for us if needed. 373 * 374 * To avoid confusing future readers: none of this is necessary 375 * to load the LDT. The hypervisor only checks this when the 376 * LDT is faulted in due to subsequent descriptor access. 377 */ 378 379 for (i = 0; i < entries; i += entries_per_page) 380 set_aliased_prot(ldt + i, PAGE_KERNEL_RO); 381 } 382 383 static void xen_free_ldt(struct desc_struct *ldt, unsigned entries) 384 { 385 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 386 int i; 387 388 for (i = 0; i < entries; i += entries_per_page) 389 set_aliased_prot(ldt + i, PAGE_KERNEL); 390 } 391 392 static void xen_set_ldt(const void *addr, unsigned entries) 393 { 394 struct mmuext_op *op; 395 struct multicall_space mcs = xen_mc_entry(sizeof(*op)); 396 397 trace_xen_cpu_set_ldt(addr, entries); 398 399 op = mcs.args; 400 op->cmd = MMUEXT_SET_LDT; 401 op->arg1.linear_addr = (unsigned long)addr; 402 op->arg2.nr_ents = entries; 403 404 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF); 405 406 xen_mc_issue(PARAVIRT_LAZY_CPU); 407 } 408 409 static void xen_load_gdt(const struct desc_ptr *dtr) 410 { 411 unsigned long va = dtr->address; 412 unsigned int size = dtr->size + 1; 413 unsigned long pfn, mfn; 414 int level; 415 pte_t *ptep; 416 void *virt; 417 418 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 419 BUG_ON(size > PAGE_SIZE); 420 BUG_ON(va & ~PAGE_MASK); 421 422 /* 423 * The GDT is per-cpu and is in the percpu data area. 424 * That can be virtually mapped, so we need to do a 425 * page-walk to get the underlying MFN for the 426 * hypercall. The page can also be in the kernel's 427 * linear range, so we need to RO that mapping too. 428 */ 429 ptep = lookup_address(va, &level); 430 BUG_ON(ptep == NULL); 431 432 pfn = pte_pfn(*ptep); 433 mfn = pfn_to_mfn(pfn); 434 virt = __va(PFN_PHYS(pfn)); 435 436 make_lowmem_page_readonly((void *)va); 437 make_lowmem_page_readonly(virt); 438 439 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 440 BUG(); 441 } 442 443 /* 444 * load_gdt for early boot, when the gdt is only mapped once 445 */ 446 static void __init xen_load_gdt_boot(const struct desc_ptr *dtr) 447 { 448 unsigned long va = dtr->address; 449 unsigned int size = dtr->size + 1; 450 unsigned long pfn, mfn; 451 pte_t pte; 452 453 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 454 BUG_ON(size > PAGE_SIZE); 455 BUG_ON(va & ~PAGE_MASK); 456 457 pfn = virt_to_pfn(va); 458 mfn = pfn_to_mfn(pfn); 459 460 pte = pfn_pte(pfn, PAGE_KERNEL_RO); 461 462 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 463 BUG(); 464 465 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 466 BUG(); 467 } 468 469 static inline bool desc_equal(const struct desc_struct *d1, 470 const struct desc_struct *d2) 471 { 472 return !memcmp(d1, d2, sizeof(*d1)); 473 } 474 475 static void load_TLS_descriptor(struct thread_struct *t, 476 unsigned int cpu, unsigned int i) 477 { 478 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i]; 479 struct desc_struct *gdt; 480 xmaddr_t maddr; 481 struct multicall_space mc; 482 483 if (desc_equal(shadow, &t->tls_array[i])) 484 return; 485 486 *shadow = t->tls_array[i]; 487 488 gdt = get_cpu_gdt_rw(cpu); 489 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); 490 mc = __xen_mc_entry(0); 491 492 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); 493 } 494 495 static void xen_load_tls(struct thread_struct *t, unsigned int cpu) 496 { 497 /* 498 * In lazy mode we need to zero %fs, otherwise we may get an 499 * exception between the new %fs descriptor being loaded and 500 * %fs being effectively cleared at __switch_to(). 501 */ 502 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU) 503 loadsegment(fs, 0); 504 505 xen_mc_batch(); 506 507 load_TLS_descriptor(t, cpu, 0); 508 load_TLS_descriptor(t, cpu, 1); 509 load_TLS_descriptor(t, cpu, 2); 510 511 xen_mc_issue(PARAVIRT_LAZY_CPU); 512 } 513 514 static void xen_load_gs_index(unsigned int idx) 515 { 516 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx)) 517 BUG(); 518 } 519 520 static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum, 521 const void *ptr) 522 { 523 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]); 524 u64 entry = *(u64 *)ptr; 525 526 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry); 527 528 preempt_disable(); 529 530 xen_mc_flush(); 531 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry)) 532 BUG(); 533 534 preempt_enable(); 535 } 536 537 void noist_exc_debug(struct pt_regs *regs); 538 539 DEFINE_IDTENTRY_RAW(xenpv_exc_nmi) 540 { 541 /* On Xen PV, NMI doesn't use IST. The C part is the same as native. */ 542 exc_nmi(regs); 543 } 544 545 DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault) 546 { 547 /* On Xen PV, DF doesn't use IST. The C part is the same as native. */ 548 exc_double_fault(regs, error_code); 549 } 550 551 DEFINE_IDTENTRY_RAW(xenpv_exc_debug) 552 { 553 /* 554 * There's no IST on Xen PV, but we still need to dispatch 555 * to the correct handler. 556 */ 557 if (user_mode(regs)) 558 noist_exc_debug(regs); 559 else 560 exc_debug(regs); 561 } 562 563 DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap) 564 { 565 /* This should never happen and there is no way to handle it. */ 566 instrumentation_begin(); 567 pr_err("Unknown trap in Xen PV mode."); 568 BUG(); 569 instrumentation_end(); 570 } 571 572 #ifdef CONFIG_X86_MCE 573 DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check) 574 { 575 /* 576 * There's no IST on Xen PV, but we still need to dispatch 577 * to the correct handler. 578 */ 579 if (user_mode(regs)) 580 noist_exc_machine_check(regs); 581 else 582 exc_machine_check(regs); 583 } 584 #endif 585 586 struct trap_array_entry { 587 void (*orig)(void); 588 void (*xen)(void); 589 bool ist_okay; 590 }; 591 592 #define TRAP_ENTRY(func, ist_ok) { \ 593 .orig = asm_##func, \ 594 .xen = xen_asm_##func, \ 595 .ist_okay = ist_ok } 596 597 #define TRAP_ENTRY_REDIR(func, ist_ok) { \ 598 .orig = asm_##func, \ 599 .xen = xen_asm_xenpv_##func, \ 600 .ist_okay = ist_ok } 601 602 static struct trap_array_entry trap_array[] = { 603 TRAP_ENTRY_REDIR(exc_debug, true ), 604 TRAP_ENTRY_REDIR(exc_double_fault, true ), 605 #ifdef CONFIG_X86_MCE 606 TRAP_ENTRY_REDIR(exc_machine_check, true ), 607 #endif 608 TRAP_ENTRY_REDIR(exc_nmi, true ), 609 TRAP_ENTRY(exc_int3, false ), 610 TRAP_ENTRY(exc_overflow, false ), 611 #ifdef CONFIG_IA32_EMULATION 612 { entry_INT80_compat, xen_entry_INT80_compat, false }, 613 #endif 614 TRAP_ENTRY(exc_page_fault, false ), 615 TRAP_ENTRY(exc_divide_error, false ), 616 TRAP_ENTRY(exc_bounds, false ), 617 TRAP_ENTRY(exc_invalid_op, false ), 618 TRAP_ENTRY(exc_device_not_available, false ), 619 TRAP_ENTRY(exc_coproc_segment_overrun, false ), 620 TRAP_ENTRY(exc_invalid_tss, false ), 621 TRAP_ENTRY(exc_segment_not_present, false ), 622 TRAP_ENTRY(exc_stack_segment, false ), 623 TRAP_ENTRY(exc_general_protection, false ), 624 TRAP_ENTRY(exc_spurious_interrupt_bug, false ), 625 TRAP_ENTRY(exc_coprocessor_error, false ), 626 TRAP_ENTRY(exc_alignment_check, false ), 627 TRAP_ENTRY(exc_simd_coprocessor_error, false ), 628 }; 629 630 static bool __ref get_trap_addr(void **addr, unsigned int ist) 631 { 632 unsigned int nr; 633 bool ist_okay = false; 634 bool found = false; 635 636 /* 637 * Replace trap handler addresses by Xen specific ones. 638 * Check for known traps using IST and whitelist them. 639 * The debugger ones are the only ones we care about. 640 * Xen will handle faults like double_fault, so we should never see 641 * them. Warn if there's an unexpected IST-using fault handler. 642 */ 643 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) { 644 struct trap_array_entry *entry = trap_array + nr; 645 646 if (*addr == entry->orig) { 647 *addr = entry->xen; 648 ist_okay = entry->ist_okay; 649 found = true; 650 break; 651 } 652 } 653 654 if (nr == ARRAY_SIZE(trap_array) && 655 *addr >= (void *)early_idt_handler_array[0] && 656 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { 657 nr = (*addr - (void *)early_idt_handler_array[0]) / 658 EARLY_IDT_HANDLER_SIZE; 659 *addr = (void *)xen_early_idt_handler_array[nr]; 660 found = true; 661 } 662 663 if (!found) 664 *addr = (void *)xen_asm_exc_xen_unknown_trap; 665 666 if (WARN_ON(found && ist != 0 && !ist_okay)) 667 return false; 668 669 return true; 670 } 671 672 static int cvt_gate_to_trap(int vector, const gate_desc *val, 673 struct trap_info *info) 674 { 675 unsigned long addr; 676 677 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT) 678 return 0; 679 680 info->vector = vector; 681 682 addr = gate_offset(val); 683 if (!get_trap_addr((void **)&addr, val->bits.ist)) 684 return 0; 685 info->address = addr; 686 687 info->cs = gate_segment(val); 688 info->flags = val->bits.dpl; 689 /* interrupt gates clear IF */ 690 if (val->bits.type == GATE_INTERRUPT) 691 info->flags |= 1 << 2; 692 693 return 1; 694 } 695 696 /* Locations of each CPU's IDT */ 697 static DEFINE_PER_CPU(struct desc_ptr, idt_desc); 698 699 /* Set an IDT entry. If the entry is part of the current IDT, then 700 also update Xen. */ 701 static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) 702 { 703 unsigned long p = (unsigned long)&dt[entrynum]; 704 unsigned long start, end; 705 706 trace_xen_cpu_write_idt_entry(dt, entrynum, g); 707 708 preempt_disable(); 709 710 start = __this_cpu_read(idt_desc.address); 711 end = start + __this_cpu_read(idt_desc.size) + 1; 712 713 xen_mc_flush(); 714 715 native_write_idt_entry(dt, entrynum, g); 716 717 if (p >= start && (p + 8) <= end) { 718 struct trap_info info[2]; 719 720 info[1].address = 0; 721 722 if (cvt_gate_to_trap(entrynum, g, &info[0])) 723 if (HYPERVISOR_set_trap_table(info)) 724 BUG(); 725 } 726 727 preempt_enable(); 728 } 729 730 static unsigned xen_convert_trap_info(const struct desc_ptr *desc, 731 struct trap_info *traps, bool full) 732 { 733 unsigned in, out, count; 734 735 count = (desc->size+1) / sizeof(gate_desc); 736 BUG_ON(count > 256); 737 738 for (in = out = 0; in < count; in++) { 739 gate_desc *entry = (gate_desc *)(desc->address) + in; 740 741 if (cvt_gate_to_trap(in, entry, &traps[out]) || full) 742 out++; 743 } 744 745 return out; 746 } 747 748 void xen_copy_trap_info(struct trap_info *traps) 749 { 750 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc); 751 752 xen_convert_trap_info(desc, traps, true); 753 } 754 755 /* Load a new IDT into Xen. In principle this can be per-CPU, so we 756 hold a spinlock to protect the static traps[] array (static because 757 it avoids allocation, and saves stack space). */ 758 static void xen_load_idt(const struct desc_ptr *desc) 759 { 760 static DEFINE_SPINLOCK(lock); 761 static struct trap_info traps[257]; 762 unsigned out; 763 764 trace_xen_cpu_load_idt(desc); 765 766 spin_lock(&lock); 767 768 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); 769 770 out = xen_convert_trap_info(desc, traps, false); 771 memset(&traps[out], 0, sizeof(traps[0])); 772 773 xen_mc_flush(); 774 if (HYPERVISOR_set_trap_table(traps)) 775 BUG(); 776 777 spin_unlock(&lock); 778 } 779 780 /* Write a GDT descriptor entry. Ignore LDT descriptors, since 781 they're handled differently. */ 782 static void xen_write_gdt_entry(struct desc_struct *dt, int entry, 783 const void *desc, int type) 784 { 785 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 786 787 preempt_disable(); 788 789 switch (type) { 790 case DESC_LDT: 791 case DESC_TSS: 792 /* ignore */ 793 break; 794 795 default: { 796 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]); 797 798 xen_mc_flush(); 799 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 800 BUG(); 801 } 802 803 } 804 805 preempt_enable(); 806 } 807 808 /* 809 * Version of write_gdt_entry for use at early boot-time needed to 810 * update an entry as simply as possible. 811 */ 812 static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry, 813 const void *desc, int type) 814 { 815 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 816 817 switch (type) { 818 case DESC_LDT: 819 case DESC_TSS: 820 /* ignore */ 821 break; 822 823 default: { 824 xmaddr_t maddr = virt_to_machine(&dt[entry]); 825 826 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 827 dt[entry] = *(struct desc_struct *)desc; 828 } 829 830 } 831 } 832 833 static void xen_load_sp0(unsigned long sp0) 834 { 835 struct multicall_space mcs; 836 837 mcs = xen_mc_entry(0); 838 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0); 839 xen_mc_issue(PARAVIRT_LAZY_CPU); 840 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 841 } 842 843 #ifdef CONFIG_X86_IOPL_IOPERM 844 static void xen_invalidate_io_bitmap(void) 845 { 846 struct physdev_set_iobitmap iobitmap = { 847 .bitmap = NULL, 848 .nr_ports = 0, 849 }; 850 851 native_tss_invalidate_io_bitmap(); 852 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 853 } 854 855 static void xen_update_io_bitmap(void) 856 { 857 struct physdev_set_iobitmap iobitmap; 858 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 859 860 native_tss_update_io_bitmap(); 861 862 iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) + 863 tss->x86_tss.io_bitmap_base; 864 if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID) 865 iobitmap.nr_ports = 0; 866 else 867 iobitmap.nr_ports = IO_BITMAP_BITS; 868 869 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 870 } 871 #endif 872 873 static void xen_io_delay(void) 874 { 875 } 876 877 static DEFINE_PER_CPU(unsigned long, xen_cr0_value); 878 879 static unsigned long xen_read_cr0(void) 880 { 881 unsigned long cr0 = this_cpu_read(xen_cr0_value); 882 883 if (unlikely(cr0 == 0)) { 884 cr0 = native_read_cr0(); 885 this_cpu_write(xen_cr0_value, cr0); 886 } 887 888 return cr0; 889 } 890 891 static void xen_write_cr0(unsigned long cr0) 892 { 893 struct multicall_space mcs; 894 895 this_cpu_write(xen_cr0_value, cr0); 896 897 /* Only pay attention to cr0.TS; everything else is 898 ignored. */ 899 mcs = xen_mc_entry(0); 900 901 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0); 902 903 xen_mc_issue(PARAVIRT_LAZY_CPU); 904 } 905 906 static void xen_write_cr4(unsigned long cr4) 907 { 908 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE); 909 910 native_write_cr4(cr4); 911 } 912 913 static u64 xen_read_msr_safe(unsigned int msr, int *err) 914 { 915 u64 val; 916 917 if (pmu_msr_read(msr, &val, err)) 918 return val; 919 920 val = native_read_msr_safe(msr, err); 921 switch (msr) { 922 case MSR_IA32_APICBASE: 923 val &= ~X2APIC_ENABLE; 924 break; 925 } 926 return val; 927 } 928 929 static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high) 930 { 931 int ret; 932 unsigned int which; 933 u64 base; 934 935 ret = 0; 936 937 switch (msr) { 938 case MSR_FS_BASE: which = SEGBASE_FS; goto set; 939 case MSR_KERNEL_GS_BASE: which = SEGBASE_GS_USER; goto set; 940 case MSR_GS_BASE: which = SEGBASE_GS_KERNEL; goto set; 941 942 set: 943 base = ((u64)high << 32) | low; 944 if (HYPERVISOR_set_segment_base(which, base) != 0) 945 ret = -EIO; 946 break; 947 948 case MSR_STAR: 949 case MSR_CSTAR: 950 case MSR_LSTAR: 951 case MSR_SYSCALL_MASK: 952 case MSR_IA32_SYSENTER_CS: 953 case MSR_IA32_SYSENTER_ESP: 954 case MSR_IA32_SYSENTER_EIP: 955 /* Fast syscall setup is all done in hypercalls, so 956 these are all ignored. Stub them out here to stop 957 Xen console noise. */ 958 break; 959 960 default: 961 if (!pmu_msr_write(msr, low, high, &ret)) 962 ret = native_write_msr_safe(msr, low, high); 963 } 964 965 return ret; 966 } 967 968 static u64 xen_read_msr(unsigned int msr) 969 { 970 /* 971 * This will silently swallow a #GP from RDMSR. It may be worth 972 * changing that. 973 */ 974 int err; 975 976 return xen_read_msr_safe(msr, &err); 977 } 978 979 static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) 980 { 981 /* 982 * This will silently swallow a #GP from WRMSR. It may be worth 983 * changing that. 984 */ 985 xen_write_msr_safe(msr, low, high); 986 } 987 988 /* This is called once we have the cpu_possible_mask */ 989 void __init xen_setup_vcpu_info_placement(void) 990 { 991 int cpu; 992 993 for_each_possible_cpu(cpu) { 994 /* Set up direct vCPU id mapping for PV guests. */ 995 per_cpu(xen_vcpu_id, cpu) = cpu; 996 997 /* 998 * xen_vcpu_setup(cpu) can fail -- in which case it 999 * falls back to the shared_info version for cpus 1000 * where xen_vcpu_nr(cpu) < MAX_VIRT_CPUS. 1001 * 1002 * xen_cpu_up_prepare_pv() handles the rest by failing 1003 * them in hotplug. 1004 */ 1005 (void) xen_vcpu_setup(cpu); 1006 } 1007 1008 /* 1009 * xen_vcpu_setup managed to place the vcpu_info within the 1010 * percpu area for all cpus, so make use of it. 1011 */ 1012 if (xen_have_vcpu_info_placement) { 1013 pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct); 1014 pv_ops.irq.irq_disable = 1015 __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); 1016 pv_ops.irq.irq_enable = 1017 __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); 1018 pv_ops.mmu.read_cr2 = 1019 __PV_IS_CALLEE_SAVE(xen_read_cr2_direct); 1020 } 1021 } 1022 1023 static const struct pv_info xen_info __initconst = { 1024 .extra_user_64bit_cs = FLAT_USER_CS64, 1025 .name = "Xen", 1026 }; 1027 1028 static const typeof(pv_ops) xen_cpu_ops __initconst = { 1029 .cpu = { 1030 .cpuid = xen_cpuid, 1031 1032 .set_debugreg = xen_set_debugreg, 1033 .get_debugreg = xen_get_debugreg, 1034 1035 .read_cr0 = xen_read_cr0, 1036 .write_cr0 = xen_write_cr0, 1037 1038 .write_cr4 = xen_write_cr4, 1039 1040 .wbinvd = native_wbinvd, 1041 1042 .read_msr = xen_read_msr, 1043 .write_msr = xen_write_msr, 1044 1045 .read_msr_safe = xen_read_msr_safe, 1046 .write_msr_safe = xen_write_msr_safe, 1047 1048 .read_pmc = xen_read_pmc, 1049 1050 .load_tr_desc = paravirt_nop, 1051 .set_ldt = xen_set_ldt, 1052 .load_gdt = xen_load_gdt, 1053 .load_idt = xen_load_idt, 1054 .load_tls = xen_load_tls, 1055 .load_gs_index = xen_load_gs_index, 1056 1057 .alloc_ldt = xen_alloc_ldt, 1058 .free_ldt = xen_free_ldt, 1059 1060 .store_tr = xen_store_tr, 1061 1062 .write_ldt_entry = xen_write_ldt_entry, 1063 .write_gdt_entry = xen_write_gdt_entry, 1064 .write_idt_entry = xen_write_idt_entry, 1065 .load_sp0 = xen_load_sp0, 1066 1067 #ifdef CONFIG_X86_IOPL_IOPERM 1068 .invalidate_io_bitmap = xen_invalidate_io_bitmap, 1069 .update_io_bitmap = xen_update_io_bitmap, 1070 #endif 1071 .io_delay = xen_io_delay, 1072 1073 .start_context_switch = paravirt_start_context_switch, 1074 .end_context_switch = xen_end_context_switch, 1075 }, 1076 }; 1077 1078 static void xen_restart(char *msg) 1079 { 1080 xen_reboot(SHUTDOWN_reboot); 1081 } 1082 1083 static void xen_machine_halt(void) 1084 { 1085 xen_reboot(SHUTDOWN_poweroff); 1086 } 1087 1088 static void xen_machine_power_off(void) 1089 { 1090 if (pm_power_off) 1091 pm_power_off(); 1092 xen_reboot(SHUTDOWN_poweroff); 1093 } 1094 1095 static void xen_crash_shutdown(struct pt_regs *regs) 1096 { 1097 xen_reboot(SHUTDOWN_crash); 1098 } 1099 1100 static const struct machine_ops xen_machine_ops __initconst = { 1101 .restart = xen_restart, 1102 .halt = xen_machine_halt, 1103 .power_off = xen_machine_power_off, 1104 .shutdown = xen_machine_halt, 1105 .crash_shutdown = xen_crash_shutdown, 1106 .emergency_restart = xen_emergency_restart, 1107 }; 1108 1109 static unsigned char xen_get_nmi_reason(void) 1110 { 1111 unsigned char reason = 0; 1112 1113 /* Construct a value which looks like it came from port 0x61. */ 1114 if (test_bit(_XEN_NMIREASON_io_error, 1115 &HYPERVISOR_shared_info->arch.nmi_reason)) 1116 reason |= NMI_REASON_IOCHK; 1117 if (test_bit(_XEN_NMIREASON_pci_serr, 1118 &HYPERVISOR_shared_info->arch.nmi_reason)) 1119 reason |= NMI_REASON_SERR; 1120 1121 return reason; 1122 } 1123 1124 static void __init xen_boot_params_init_edd(void) 1125 { 1126 #if IS_ENABLED(CONFIG_EDD) 1127 struct xen_platform_op op; 1128 struct edd_info *edd_info; 1129 u32 *mbr_signature; 1130 unsigned nr; 1131 int ret; 1132 1133 edd_info = boot_params.eddbuf; 1134 mbr_signature = boot_params.edd_mbr_sig_buffer; 1135 1136 op.cmd = XENPF_firmware_info; 1137 1138 op.u.firmware_info.type = XEN_FW_DISK_INFO; 1139 for (nr = 0; nr < EDDMAXNR; nr++) { 1140 struct edd_info *info = edd_info + nr; 1141 1142 op.u.firmware_info.index = nr; 1143 info->params.length = sizeof(info->params); 1144 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params, 1145 &info->params); 1146 ret = HYPERVISOR_platform_op(&op); 1147 if (ret) 1148 break; 1149 1150 #define C(x) info->x = op.u.firmware_info.u.disk_info.x 1151 C(device); 1152 C(version); 1153 C(interface_support); 1154 C(legacy_max_cylinder); 1155 C(legacy_max_head); 1156 C(legacy_sectors_per_track); 1157 #undef C 1158 } 1159 boot_params.eddbuf_entries = nr; 1160 1161 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE; 1162 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) { 1163 op.u.firmware_info.index = nr; 1164 ret = HYPERVISOR_platform_op(&op); 1165 if (ret) 1166 break; 1167 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature; 1168 } 1169 boot_params.edd_mbr_sig_buf_entries = nr; 1170 #endif 1171 } 1172 1173 /* 1174 * Set up the GDT and segment registers for -fstack-protector. Until 1175 * we do this, we have to be careful not to call any stack-protected 1176 * function, which is most of the kernel. 1177 */ 1178 static void __init xen_setup_gdt(int cpu) 1179 { 1180 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot; 1181 pv_ops.cpu.load_gdt = xen_load_gdt_boot; 1182 1183 switch_to_new_gdt(cpu); 1184 1185 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry; 1186 pv_ops.cpu.load_gdt = xen_load_gdt; 1187 } 1188 1189 static void __init xen_dom0_set_legacy_features(void) 1190 { 1191 x86_platform.legacy.rtc = 1; 1192 } 1193 1194 static void __init xen_domu_set_legacy_features(void) 1195 { 1196 x86_platform.legacy.rtc = 0; 1197 } 1198 1199 /* First C function to be called on Xen boot */ 1200 asmlinkage __visible void __init xen_start_kernel(void) 1201 { 1202 struct physdev_set_iopl set_iopl; 1203 unsigned long initrd_start = 0; 1204 int rc; 1205 1206 if (!xen_start_info) 1207 return; 1208 1209 xen_domain_type = XEN_PV_DOMAIN; 1210 xen_start_flags = xen_start_info->flags; 1211 1212 xen_setup_features(); 1213 1214 /* Install Xen paravirt ops */ 1215 pv_info = xen_info; 1216 pv_ops.cpu = xen_cpu_ops.cpu; 1217 paravirt_iret = xen_iret; 1218 xen_init_irq_ops(); 1219 1220 /* 1221 * Setup xen_vcpu early because it is needed for 1222 * local_irq_disable(), irqs_disabled(), e.g. in printk(). 1223 * 1224 * Don't do the full vcpu_info placement stuff until we have 1225 * the cpu_possible_mask and a non-dummy shared_info. 1226 */ 1227 xen_vcpu_info_reset(0); 1228 1229 x86_platform.get_nmi_reason = xen_get_nmi_reason; 1230 1231 x86_init.resources.memory_setup = xen_memory_setup; 1232 x86_init.irqs.intr_mode_select = x86_init_noop; 1233 x86_init.irqs.intr_mode_init = x86_init_noop; 1234 x86_init.oem.arch_setup = xen_arch_setup; 1235 x86_init.oem.banner = xen_banner; 1236 x86_init.hyper.init_platform = xen_pv_init_platform; 1237 x86_init.hyper.guest_late_init = xen_pv_guest_late_init; 1238 1239 /* 1240 * Set up some pagetable state before starting to set any ptes. 1241 */ 1242 1243 xen_setup_machphys_mapping(); 1244 xen_init_mmu_ops(); 1245 1246 /* Prevent unwanted bits from being set in PTEs. */ 1247 __supported_pte_mask &= ~_PAGE_GLOBAL; 1248 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 1249 1250 /* 1251 * Prevent page tables from being allocated in highmem, even 1252 * if CONFIG_HIGHPTE is enabled. 1253 */ 1254 __userpte_alloc_gfp &= ~__GFP_HIGHMEM; 1255 1256 /* Get mfn list */ 1257 xen_build_dynamic_phys_to_machine(); 1258 1259 /* Work out if we support NX */ 1260 get_cpu_cap(&boot_cpu_data); 1261 x86_configure_nx(); 1262 1263 /* 1264 * Set up kernel GDT and segment registers, mainly so that 1265 * -fstack-protector code can be executed. 1266 */ 1267 xen_setup_gdt(0); 1268 1269 /* Determine virtual and physical address sizes */ 1270 get_cpu_address_sizes(&boot_cpu_data); 1271 1272 /* Let's presume PV guests always boot on vCPU with id 0. */ 1273 per_cpu(xen_vcpu_id, 0) = 0; 1274 1275 idt_setup_early_handler(); 1276 1277 xen_init_capabilities(); 1278 1279 #ifdef CONFIG_X86_LOCAL_APIC 1280 /* 1281 * set up the basic apic ops. 1282 */ 1283 xen_init_apic(); 1284 #endif 1285 1286 machine_ops = xen_machine_ops; 1287 1288 /* 1289 * The only reliable way to retain the initial address of the 1290 * percpu gdt_page is to remember it here, so we can go and 1291 * mark it RW later, when the initial percpu area is freed. 1292 */ 1293 xen_initial_gdt = &per_cpu(gdt_page, 0); 1294 1295 xen_smp_init(); 1296 1297 #ifdef CONFIG_ACPI_NUMA 1298 /* 1299 * The pages we from Xen are not related to machine pages, so 1300 * any NUMA information the kernel tries to get from ACPI will 1301 * be meaningless. Prevent it from trying. 1302 */ 1303 disable_srat(); 1304 #endif 1305 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); 1306 1307 local_irq_disable(); 1308 early_boot_irqs_disabled = true; 1309 1310 xen_raw_console_write("mapping kernel into physical memory\n"); 1311 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, 1312 xen_start_info->nr_pages); 1313 xen_reserve_special_pages(); 1314 1315 /* 1316 * We used to do this in xen_arch_setup, but that is too late 1317 * on AMD were early_cpu_init (run before ->arch_setup()) calls 1318 * early_amd_init which pokes 0xcf8 port. 1319 */ 1320 set_iopl.iopl = 1; 1321 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); 1322 if (rc != 0) 1323 xen_raw_printk("physdev_op failed %d\n", rc); 1324 1325 1326 if (xen_start_info->mod_start) { 1327 if (xen_start_info->flags & SIF_MOD_START_PFN) 1328 initrd_start = PFN_PHYS(xen_start_info->mod_start); 1329 else 1330 initrd_start = __pa(xen_start_info->mod_start); 1331 } 1332 1333 /* Poke various useful things into boot_params */ 1334 boot_params.hdr.type_of_loader = (9 << 4) | 0; 1335 boot_params.hdr.ramdisk_image = initrd_start; 1336 boot_params.hdr.ramdisk_size = xen_start_info->mod_len; 1337 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); 1338 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN; 1339 1340 if (!xen_initial_domain()) { 1341 if (pci_xen) 1342 x86_init.pci.arch_init = pci_xen_init; 1343 x86_platform.set_legacy_features = 1344 xen_domu_set_legacy_features; 1345 } else { 1346 const struct dom0_vga_console_info *info = 1347 (void *)((char *)xen_start_info + 1348 xen_start_info->console.dom0.info_off); 1349 struct xen_platform_op op = { 1350 .cmd = XENPF_firmware_info, 1351 .interface_version = XENPF_INTERFACE_VERSION, 1352 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS, 1353 }; 1354 1355 x86_platform.set_legacy_features = 1356 xen_dom0_set_legacy_features; 1357 xen_init_vga(info, xen_start_info->console.dom0.info_size); 1358 xen_start_info->console.domU.mfn = 0; 1359 xen_start_info->console.domU.evtchn = 0; 1360 1361 if (HYPERVISOR_platform_op(&op) == 0) 1362 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags; 1363 1364 /* Make sure ACS will be enabled */ 1365 pci_request_acs(); 1366 1367 xen_acpi_sleep_register(); 1368 1369 /* Avoid searching for BIOS MP tables */ 1370 x86_init.mpparse.find_smp_config = x86_init_noop; 1371 x86_init.mpparse.get_smp_config = x86_init_uint_noop; 1372 1373 xen_boot_params_init_edd(); 1374 1375 #ifdef CONFIG_ACPI 1376 /* 1377 * Disable selecting "Firmware First mode" for correctable 1378 * memory errors, as this is the duty of the hypervisor to 1379 * decide. 1380 */ 1381 acpi_disable_cmcff = 1; 1382 #endif 1383 } 1384 1385 xen_add_preferred_consoles(); 1386 1387 #ifdef CONFIG_PCI 1388 /* PCI BIOS service won't work from a PV guest. */ 1389 pci_probe &= ~PCI_PROBE_BIOS; 1390 #endif 1391 xen_raw_console_write("about to get started...\n"); 1392 1393 /* We need this for printk timestamps */ 1394 xen_setup_runstate_info(0); 1395 1396 xen_efi_init(&boot_params); 1397 1398 /* Start the world */ 1399 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */ 1400 x86_64_start_reservations((char *)__pa_symbol(&boot_params)); 1401 } 1402 1403 static int xen_cpu_up_prepare_pv(unsigned int cpu) 1404 { 1405 int rc; 1406 1407 if (per_cpu(xen_vcpu, cpu) == NULL) 1408 return -ENODEV; 1409 1410 xen_setup_timer(cpu); 1411 1412 rc = xen_smp_intr_init(cpu); 1413 if (rc) { 1414 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n", 1415 cpu, rc); 1416 return rc; 1417 } 1418 1419 rc = xen_smp_intr_init_pv(cpu); 1420 if (rc) { 1421 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n", 1422 cpu, rc); 1423 return rc; 1424 } 1425 1426 return 0; 1427 } 1428 1429 static int xen_cpu_dead_pv(unsigned int cpu) 1430 { 1431 xen_smp_intr_free(cpu); 1432 xen_smp_intr_free_pv(cpu); 1433 1434 xen_teardown_timer(cpu); 1435 1436 return 0; 1437 } 1438 1439 static uint32_t __init xen_platform_pv(void) 1440 { 1441 if (xen_pv_domain()) 1442 return xen_cpuid_base(); 1443 1444 return 0; 1445 } 1446 1447 const __initconst struct hypervisor_x86 x86_hyper_xen_pv = { 1448 .name = "Xen PV", 1449 .detect = xen_platform_pv, 1450 .type = X86_HYPER_XEN_PV, 1451 .runtime.pin_vcpu = xen_pin_vcpu, 1452 .ignore_nopv = true, 1453 }; 1454