1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Core of Xen paravirt_ops implementation. 4 * 5 * This file contains the xen_paravirt_ops structure itself, and the 6 * implementations for: 7 * - privileged instructions 8 * - interrupt flags 9 * - segment operations 10 * - booting and setup 11 * 12 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/preempt.h> 20 #include <linux/hardirq.h> 21 #include <linux/percpu.h> 22 #include <linux/delay.h> 23 #include <linux/start_kernel.h> 24 #include <linux/sched.h> 25 #include <linux/kprobes.h> 26 #include <linux/kstrtox.h> 27 #include <linux/memblock.h> 28 #include <linux/export.h> 29 #include <linux/mm.h> 30 #include <linux/page-flags.h> 31 #include <linux/pci.h> 32 #include <linux/gfp.h> 33 #include <linux/edd.h> 34 #include <linux/reboot.h> 35 #include <linux/virtio_anchor.h> 36 #include <linux/stackprotector.h> 37 38 #include <xen/xen.h> 39 #include <xen/events.h> 40 #include <xen/interface/xen.h> 41 #include <xen/interface/version.h> 42 #include <xen/interface/physdev.h> 43 #include <xen/interface/vcpu.h> 44 #include <xen/interface/memory.h> 45 #include <xen/interface/nmi.h> 46 #include <xen/interface/xen-mca.h> 47 #include <xen/features.h> 48 #include <xen/page.h> 49 #include <xen/hvc-console.h> 50 #include <xen/acpi.h> 51 52 #include <asm/cpuid.h> 53 #include <asm/paravirt.h> 54 #include <asm/apic.h> 55 #include <asm/page.h> 56 #include <asm/xen/pci.h> 57 #include <asm/xen/hypercall.h> 58 #include <asm/xen/hypervisor.h> 59 #include <asm/xen/cpuid.h> 60 #include <asm/fixmap.h> 61 #include <asm/processor.h> 62 #include <asm/proto.h> 63 #include <asm/msr-index.h> 64 #include <asm/traps.h> 65 #include <asm/setup.h> 66 #include <asm/desc.h> 67 #include <asm/pgalloc.h> 68 #include <asm/tlbflush.h> 69 #include <asm/reboot.h> 70 #include <asm/hypervisor.h> 71 #include <asm/mach_traps.h> 72 #include <asm/mtrr.h> 73 #include <asm/mwait.h> 74 #include <asm/pci_x86.h> 75 #include <asm/cpu.h> 76 #ifdef CONFIG_X86_IOPL_IOPERM 77 #include <asm/io_bitmap.h> 78 #endif 79 80 #ifdef CONFIG_ACPI 81 #include <linux/acpi.h> 82 #include <asm/acpi.h> 83 #include <acpi/proc_cap_intel.h> 84 #include <acpi/processor.h> 85 #include <xen/interface/platform.h> 86 #endif 87 88 #include "xen-ops.h" 89 90 #include "../kernel/cpu/cpu.h" /* get_cpu_cap() */ 91 92 void *xen_initial_gdt; 93 94 static int xen_cpu_up_prepare_pv(unsigned int cpu); 95 static int xen_cpu_dead_pv(unsigned int cpu); 96 97 struct tls_descs { 98 struct desc_struct desc[3]; 99 }; 100 101 DEFINE_PER_CPU(enum xen_lazy_mode, xen_lazy_mode) = XEN_LAZY_NONE; 102 DEFINE_PER_CPU(unsigned int, xen_lazy_nesting); 103 104 enum xen_lazy_mode xen_get_lazy_mode(void) 105 { 106 if (in_interrupt()) 107 return XEN_LAZY_NONE; 108 109 return this_cpu_read(xen_lazy_mode); 110 } 111 112 /* 113 * Updating the 3 TLS descriptors in the GDT on every task switch is 114 * surprisingly expensive so we avoid updating them if they haven't 115 * changed. Since Xen writes different descriptors than the one 116 * passed in the update_descriptor hypercall we keep shadow copies to 117 * compare against. 118 */ 119 static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); 120 121 static __read_mostly bool xen_msr_safe = IS_ENABLED(CONFIG_XEN_PV_MSR_SAFE); 122 123 static int __init parse_xen_msr_safe(char *str) 124 { 125 if (str) 126 return kstrtobool(str, &xen_msr_safe); 127 return -EINVAL; 128 } 129 early_param("xen_msr_safe", parse_xen_msr_safe); 130 131 /* Get MTRR settings from Xen and put them into mtrr_state. */ 132 static void __init xen_set_mtrr_data(void) 133 { 134 #ifdef CONFIG_MTRR 135 struct xen_platform_op op = { 136 .cmd = XENPF_read_memtype, 137 .interface_version = XENPF_INTERFACE_VERSION, 138 }; 139 unsigned int reg; 140 unsigned long mask; 141 uint32_t eax, width; 142 static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata; 143 144 /* Get physical address width (only 64-bit cpus supported). */ 145 width = 36; 146 eax = cpuid_eax(0x80000000); 147 if ((eax >> 16) == 0x8000 && eax >= 0x80000008) { 148 eax = cpuid_eax(0x80000008); 149 width = eax & 0xff; 150 } 151 152 for (reg = 0; reg < MTRR_MAX_VAR_RANGES; reg++) { 153 op.u.read_memtype.reg = reg; 154 if (HYPERVISOR_platform_op(&op)) 155 break; 156 157 /* 158 * Only called in dom0, which has all RAM PFNs mapped at 159 * RAM MFNs, and all PCI space etc. is identity mapped. 160 * This means we can treat MFN == PFN regarding MTRR settings. 161 */ 162 var[reg].base_lo = op.u.read_memtype.type; 163 var[reg].base_lo |= op.u.read_memtype.mfn << PAGE_SHIFT; 164 var[reg].base_hi = op.u.read_memtype.mfn >> (32 - PAGE_SHIFT); 165 mask = ~((op.u.read_memtype.nr_mfns << PAGE_SHIFT) - 1); 166 mask &= (1UL << width) - 1; 167 if (mask) 168 mask |= MTRR_PHYSMASK_V; 169 var[reg].mask_lo = mask; 170 var[reg].mask_hi = mask >> 32; 171 } 172 173 /* Only overwrite MTRR state if any MTRR could be got from Xen. */ 174 if (reg) 175 guest_force_mtrr_state(var, reg, MTRR_TYPE_UNCACHABLE); 176 #endif 177 } 178 179 static void __init xen_pv_init_platform(void) 180 { 181 /* PV guests can't operate virtio devices without grants. */ 182 if (IS_ENABLED(CONFIG_XEN_VIRTIO)) 183 virtio_set_mem_acc_cb(xen_virtio_restricted_mem_acc); 184 185 populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP)); 186 187 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info); 188 HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); 189 190 /* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */ 191 xen_vcpu_info_reset(0); 192 193 /* pvclock is in shared info area */ 194 xen_init_time_ops(); 195 196 if (xen_initial_domain()) 197 xen_set_mtrr_data(); 198 else 199 guest_force_mtrr_state(NULL, 0, MTRR_TYPE_WRBACK); 200 201 /* Adjust nr_cpu_ids before "enumeration" happens */ 202 xen_smp_count_cpus(); 203 } 204 205 static void __init xen_pv_guest_late_init(void) 206 { 207 #ifndef CONFIG_SMP 208 /* Setup shared vcpu info for non-smp configurations */ 209 xen_setup_vcpu_info_placement(); 210 #endif 211 } 212 213 static __read_mostly unsigned int cpuid_leaf5_ecx_val; 214 static __read_mostly unsigned int cpuid_leaf5_edx_val; 215 216 static void xen_cpuid(unsigned int *ax, unsigned int *bx, 217 unsigned int *cx, unsigned int *dx) 218 { 219 unsigned int maskebx = ~0; 220 unsigned int or_ebx = 0; 221 222 /* 223 * Mask out inconvenient features, to try and disable as many 224 * unsupported kernel subsystems as possible. 225 */ 226 switch (*ax) { 227 case 0x1: 228 /* Replace initial APIC ID in bits 24-31 of EBX. */ 229 /* See xen_pv_smp_config() for related topology preparations. */ 230 maskebx = 0x00ffffff; 231 or_ebx = smp_processor_id() << 24; 232 break; 233 234 case CPUID_LEAF_MWAIT: 235 /* Synthesize the values.. */ 236 *ax = 0; 237 *bx = 0; 238 *cx = cpuid_leaf5_ecx_val; 239 *dx = cpuid_leaf5_edx_val; 240 return; 241 242 case 0xb: 243 /* Suppress extended topology stuff */ 244 maskebx = 0; 245 break; 246 } 247 248 asm(XEN_EMULATE_PREFIX "cpuid" 249 : "=a" (*ax), 250 "=b" (*bx), 251 "=c" (*cx), 252 "=d" (*dx) 253 : "0" (*ax), "2" (*cx)); 254 255 *bx &= maskebx; 256 *bx |= or_ebx; 257 } 258 259 static bool __init xen_check_mwait(void) 260 { 261 #ifdef CONFIG_ACPI 262 struct xen_platform_op op = { 263 .cmd = XENPF_set_processor_pminfo, 264 .u.set_pminfo.id = -1, 265 .u.set_pminfo.type = XEN_PM_PDC, 266 }; 267 uint32_t buf[3]; 268 unsigned int ax, bx, cx, dx; 269 unsigned int mwait_mask; 270 271 /* We need to determine whether it is OK to expose the MWAIT 272 * capability to the kernel to harvest deeper than C3 states from ACPI 273 * _CST using the processor_harvest_xen.c module. For this to work, we 274 * need to gather the MWAIT_LEAF values (which the cstate.c code 275 * checks against). The hypervisor won't expose the MWAIT flag because 276 * it would break backwards compatibility; so we will find out directly 277 * from the hardware and hypercall. 278 */ 279 if (!xen_initial_domain()) 280 return false; 281 282 /* 283 * When running under platform earlier than Xen4.2, do not expose 284 * mwait, to avoid the risk of loading native acpi pad driver 285 */ 286 if (!xen_running_on_version_or_later(4, 2)) 287 return false; 288 289 ax = 1; 290 cx = 0; 291 292 native_cpuid(&ax, &bx, &cx, &dx); 293 294 mwait_mask = (1 << (X86_FEATURE_EST % 32)) | 295 (1 << (X86_FEATURE_MWAIT % 32)); 296 297 if ((cx & mwait_mask) != mwait_mask) 298 return false; 299 300 /* We need to emulate the MWAIT_LEAF and for that we need both 301 * ecx and edx. The hypercall provides only partial information. 302 */ 303 304 ax = CPUID_LEAF_MWAIT; 305 bx = 0; 306 cx = 0; 307 dx = 0; 308 309 native_cpuid(&ax, &bx, &cx, &dx); 310 311 /* Ask the Hypervisor whether to clear ACPI_PROC_CAP_C_C2C3_FFH. If so, 312 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. 313 */ 314 buf[0] = ACPI_PDC_REVISION_ID; 315 buf[1] = 1; 316 buf[2] = (ACPI_PROC_CAP_C_CAPABILITY_SMP | ACPI_PROC_CAP_EST_CAPABILITY_SWSMP); 317 318 set_xen_guest_handle(op.u.set_pminfo.pdc, buf); 319 320 if ((HYPERVISOR_platform_op(&op) == 0) && 321 (buf[2] & (ACPI_PROC_CAP_C_C1_FFH | ACPI_PROC_CAP_C_C2C3_FFH))) { 322 cpuid_leaf5_ecx_val = cx; 323 cpuid_leaf5_edx_val = dx; 324 } 325 return true; 326 #else 327 return false; 328 #endif 329 } 330 331 static bool __init xen_check_xsave(void) 332 { 333 unsigned int cx, xsave_mask; 334 335 cx = cpuid_ecx(1); 336 337 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) | 338 (1 << (X86_FEATURE_OSXSAVE % 32)); 339 340 /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ 341 return (cx & xsave_mask) == xsave_mask; 342 } 343 344 static void __init xen_init_capabilities(void) 345 { 346 setup_force_cpu_cap(X86_FEATURE_XENPV); 347 setup_clear_cpu_cap(X86_FEATURE_DCA); 348 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF); 349 setup_clear_cpu_cap(X86_FEATURE_MTRR); 350 setup_clear_cpu_cap(X86_FEATURE_ACC); 351 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 352 setup_clear_cpu_cap(X86_FEATURE_SME); 353 setup_clear_cpu_cap(X86_FEATURE_LKGS); 354 355 /* 356 * Xen PV would need some work to support PCID: CR3 handling as well 357 * as xen_flush_tlb_others() would need updating. 358 */ 359 setup_clear_cpu_cap(X86_FEATURE_PCID); 360 361 if (!xen_initial_domain()) 362 setup_clear_cpu_cap(X86_FEATURE_ACPI); 363 364 if (xen_check_mwait()) 365 setup_force_cpu_cap(X86_FEATURE_MWAIT); 366 else 367 setup_clear_cpu_cap(X86_FEATURE_MWAIT); 368 369 if (!xen_check_xsave()) { 370 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 371 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE); 372 } 373 } 374 375 static noinstr void xen_set_debugreg(int reg, unsigned long val) 376 { 377 HYPERVISOR_set_debugreg(reg, val); 378 } 379 380 static noinstr unsigned long xen_get_debugreg(int reg) 381 { 382 return HYPERVISOR_get_debugreg(reg); 383 } 384 385 static void xen_start_context_switch(struct task_struct *prev) 386 { 387 BUG_ON(preemptible()); 388 389 if (this_cpu_read(xen_lazy_mode) == XEN_LAZY_MMU) { 390 arch_leave_lazy_mmu_mode(); 391 set_ti_thread_flag(task_thread_info(prev), TIF_LAZY_MMU_UPDATES); 392 } 393 enter_lazy(XEN_LAZY_CPU); 394 } 395 396 static void xen_end_context_switch(struct task_struct *next) 397 { 398 BUG_ON(preemptible()); 399 400 xen_mc_flush(); 401 leave_lazy(XEN_LAZY_CPU); 402 if (test_and_clear_ti_thread_flag(task_thread_info(next), TIF_LAZY_MMU_UPDATES)) 403 arch_enter_lazy_mmu_mode(); 404 } 405 406 static unsigned long xen_store_tr(void) 407 { 408 return 0; 409 } 410 411 /* 412 * Set the page permissions for a particular virtual address. If the 413 * address is a vmalloc mapping (or other non-linear mapping), then 414 * find the linear mapping of the page and also set its protections to 415 * match. 416 */ 417 static void set_aliased_prot(void *v, pgprot_t prot) 418 { 419 int level; 420 pte_t *ptep; 421 pte_t pte; 422 unsigned long pfn; 423 unsigned char dummy; 424 void *va; 425 426 ptep = lookup_address((unsigned long)v, &level); 427 BUG_ON(ptep == NULL); 428 429 pfn = pte_pfn(*ptep); 430 pte = pfn_pte(pfn, prot); 431 432 /* 433 * Careful: update_va_mapping() will fail if the virtual address 434 * we're poking isn't populated in the page tables. We don't 435 * need to worry about the direct map (that's always in the page 436 * tables), but we need to be careful about vmap space. In 437 * particular, the top level page table can lazily propagate 438 * entries between processes, so if we've switched mms since we 439 * vmapped the target in the first place, we might not have the 440 * top-level page table entry populated. 441 * 442 * We disable preemption because we want the same mm active when 443 * we probe the target and when we issue the hypercall. We'll 444 * have the same nominal mm, but if we're a kernel thread, lazy 445 * mm dropping could change our pgd. 446 * 447 * Out of an abundance of caution, this uses __get_user() to fault 448 * in the target address just in case there's some obscure case 449 * in which the target address isn't readable. 450 */ 451 452 preempt_disable(); 453 454 copy_from_kernel_nofault(&dummy, v, 1); 455 456 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) 457 BUG(); 458 459 va = __va(PFN_PHYS(pfn)); 460 461 if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 462 BUG(); 463 464 preempt_enable(); 465 } 466 467 static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) 468 { 469 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 470 int i; 471 472 /* 473 * We need to mark the all aliases of the LDT pages RO. We 474 * don't need to call vm_flush_aliases(), though, since that's 475 * only responsible for flushing aliases out the TLBs, not the 476 * page tables, and Xen will flush the TLB for us if needed. 477 * 478 * To avoid confusing future readers: none of this is necessary 479 * to load the LDT. The hypervisor only checks this when the 480 * LDT is faulted in due to subsequent descriptor access. 481 */ 482 483 for (i = 0; i < entries; i += entries_per_page) 484 set_aliased_prot(ldt + i, PAGE_KERNEL_RO); 485 } 486 487 static void xen_free_ldt(struct desc_struct *ldt, unsigned entries) 488 { 489 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 490 int i; 491 492 for (i = 0; i < entries; i += entries_per_page) 493 set_aliased_prot(ldt + i, PAGE_KERNEL); 494 } 495 496 static void xen_set_ldt(const void *addr, unsigned entries) 497 { 498 struct mmuext_op *op; 499 struct multicall_space mcs = xen_mc_entry(sizeof(*op)); 500 501 trace_xen_cpu_set_ldt(addr, entries); 502 503 op = mcs.args; 504 op->cmd = MMUEXT_SET_LDT; 505 op->arg1.linear_addr = (unsigned long)addr; 506 op->arg2.nr_ents = entries; 507 508 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF); 509 510 xen_mc_issue(XEN_LAZY_CPU); 511 } 512 513 static void xen_load_gdt(const struct desc_ptr *dtr) 514 { 515 unsigned long va = dtr->address; 516 unsigned int size = dtr->size + 1; 517 unsigned long pfn, mfn; 518 int level; 519 pte_t *ptep; 520 void *virt; 521 522 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 523 BUG_ON(size > PAGE_SIZE); 524 BUG_ON(va & ~PAGE_MASK); 525 526 /* 527 * The GDT is per-cpu and is in the percpu data area. 528 * That can be virtually mapped, so we need to do a 529 * page-walk to get the underlying MFN for the 530 * hypercall. The page can also be in the kernel's 531 * linear range, so we need to RO that mapping too. 532 */ 533 ptep = lookup_address(va, &level); 534 BUG_ON(ptep == NULL); 535 536 pfn = pte_pfn(*ptep); 537 mfn = pfn_to_mfn(pfn); 538 virt = __va(PFN_PHYS(pfn)); 539 540 make_lowmem_page_readonly((void *)va); 541 make_lowmem_page_readonly(virt); 542 543 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 544 BUG(); 545 } 546 547 /* 548 * load_gdt for early boot, when the gdt is only mapped once 549 */ 550 static void __init xen_load_gdt_boot(const struct desc_ptr *dtr) 551 { 552 unsigned long va = dtr->address; 553 unsigned int size = dtr->size + 1; 554 unsigned long pfn, mfn; 555 pte_t pte; 556 557 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 558 BUG_ON(size > PAGE_SIZE); 559 BUG_ON(va & ~PAGE_MASK); 560 561 pfn = virt_to_pfn((void *)va); 562 mfn = pfn_to_mfn(pfn); 563 564 pte = pfn_pte(pfn, PAGE_KERNEL_RO); 565 566 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 567 BUG(); 568 569 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 570 BUG(); 571 } 572 573 static inline bool desc_equal(const struct desc_struct *d1, 574 const struct desc_struct *d2) 575 { 576 return !memcmp(d1, d2, sizeof(*d1)); 577 } 578 579 static void load_TLS_descriptor(struct thread_struct *t, 580 unsigned int cpu, unsigned int i) 581 { 582 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i]; 583 struct desc_struct *gdt; 584 xmaddr_t maddr; 585 struct multicall_space mc; 586 587 if (desc_equal(shadow, &t->tls_array[i])) 588 return; 589 590 *shadow = t->tls_array[i]; 591 592 gdt = get_cpu_gdt_rw(cpu); 593 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); 594 mc = __xen_mc_entry(0); 595 596 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); 597 } 598 599 static void xen_load_tls(struct thread_struct *t, unsigned int cpu) 600 { 601 /* 602 * In lazy mode we need to zero %fs, otherwise we may get an 603 * exception between the new %fs descriptor being loaded and 604 * %fs being effectively cleared at __switch_to(). 605 */ 606 if (xen_get_lazy_mode() == XEN_LAZY_CPU) 607 loadsegment(fs, 0); 608 609 xen_mc_batch(); 610 611 load_TLS_descriptor(t, cpu, 0); 612 load_TLS_descriptor(t, cpu, 1); 613 load_TLS_descriptor(t, cpu, 2); 614 615 xen_mc_issue(XEN_LAZY_CPU); 616 } 617 618 static void xen_load_gs_index(unsigned int idx) 619 { 620 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx)) 621 BUG(); 622 } 623 624 static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum, 625 const void *ptr) 626 { 627 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]); 628 u64 entry = *(u64 *)ptr; 629 630 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry); 631 632 preempt_disable(); 633 634 xen_mc_flush(); 635 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry)) 636 BUG(); 637 638 preempt_enable(); 639 } 640 641 void noist_exc_debug(struct pt_regs *regs); 642 643 DEFINE_IDTENTRY_RAW(xenpv_exc_nmi) 644 { 645 /* On Xen PV, NMI doesn't use IST. The C part is the same as native. */ 646 exc_nmi(regs); 647 } 648 649 DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault) 650 { 651 /* On Xen PV, DF doesn't use IST. The C part is the same as native. */ 652 exc_double_fault(regs, error_code); 653 } 654 655 DEFINE_IDTENTRY_RAW(xenpv_exc_debug) 656 { 657 /* 658 * There's no IST on Xen PV, but we still need to dispatch 659 * to the correct handler. 660 */ 661 if (user_mode(regs)) 662 noist_exc_debug(regs); 663 else 664 exc_debug(regs); 665 } 666 667 DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap) 668 { 669 /* This should never happen and there is no way to handle it. */ 670 instrumentation_begin(); 671 pr_err("Unknown trap in Xen PV mode."); 672 BUG(); 673 instrumentation_end(); 674 } 675 676 #ifdef CONFIG_X86_MCE 677 DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check) 678 { 679 /* 680 * There's no IST on Xen PV, but we still need to dispatch 681 * to the correct handler. 682 */ 683 if (user_mode(regs)) 684 noist_exc_machine_check(regs); 685 else 686 exc_machine_check(regs); 687 } 688 #endif 689 690 struct trap_array_entry { 691 void (*orig)(void); 692 void (*xen)(void); 693 bool ist_okay; 694 }; 695 696 #define TRAP_ENTRY(func, ist_ok) { \ 697 .orig = asm_##func, \ 698 .xen = xen_asm_##func, \ 699 .ist_okay = ist_ok } 700 701 #define TRAP_ENTRY_REDIR(func, ist_ok) { \ 702 .orig = asm_##func, \ 703 .xen = xen_asm_xenpv_##func, \ 704 .ist_okay = ist_ok } 705 706 static struct trap_array_entry trap_array[] = { 707 TRAP_ENTRY_REDIR(exc_debug, true ), 708 TRAP_ENTRY_REDIR(exc_double_fault, true ), 709 #ifdef CONFIG_X86_MCE 710 TRAP_ENTRY_REDIR(exc_machine_check, true ), 711 #endif 712 TRAP_ENTRY_REDIR(exc_nmi, true ), 713 TRAP_ENTRY(exc_int3, false ), 714 TRAP_ENTRY(exc_overflow, false ), 715 #ifdef CONFIG_IA32_EMULATION 716 TRAP_ENTRY(int80_emulation, false ), 717 #endif 718 TRAP_ENTRY(exc_page_fault, false ), 719 TRAP_ENTRY(exc_divide_error, false ), 720 TRAP_ENTRY(exc_bounds, false ), 721 TRAP_ENTRY(exc_invalid_op, false ), 722 TRAP_ENTRY(exc_device_not_available, false ), 723 TRAP_ENTRY(exc_coproc_segment_overrun, false ), 724 TRAP_ENTRY(exc_invalid_tss, false ), 725 TRAP_ENTRY(exc_segment_not_present, false ), 726 TRAP_ENTRY(exc_stack_segment, false ), 727 TRAP_ENTRY(exc_general_protection, false ), 728 TRAP_ENTRY(exc_spurious_interrupt_bug, false ), 729 TRAP_ENTRY(exc_coprocessor_error, false ), 730 TRAP_ENTRY(exc_alignment_check, false ), 731 TRAP_ENTRY(exc_simd_coprocessor_error, false ), 732 #ifdef CONFIG_X86_CET 733 TRAP_ENTRY(exc_control_protection, false ), 734 #endif 735 }; 736 737 static bool __ref get_trap_addr(void **addr, unsigned int ist) 738 { 739 unsigned int nr; 740 bool ist_okay = false; 741 bool found = false; 742 743 /* 744 * Replace trap handler addresses by Xen specific ones. 745 * Check for known traps using IST and whitelist them. 746 * The debugger ones are the only ones we care about. 747 * Xen will handle faults like double_fault, so we should never see 748 * them. Warn if there's an unexpected IST-using fault handler. 749 */ 750 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) { 751 struct trap_array_entry *entry = trap_array + nr; 752 753 if (*addr == entry->orig) { 754 *addr = entry->xen; 755 ist_okay = entry->ist_okay; 756 found = true; 757 break; 758 } 759 } 760 761 if (nr == ARRAY_SIZE(trap_array) && 762 *addr >= (void *)early_idt_handler_array[0] && 763 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { 764 nr = (*addr - (void *)early_idt_handler_array[0]) / 765 EARLY_IDT_HANDLER_SIZE; 766 *addr = (void *)xen_early_idt_handler_array[nr]; 767 found = true; 768 } 769 770 if (!found) 771 *addr = (void *)xen_asm_exc_xen_unknown_trap; 772 773 if (WARN_ON(found && ist != 0 && !ist_okay)) 774 return false; 775 776 return true; 777 } 778 779 static int cvt_gate_to_trap(int vector, const gate_desc *val, 780 struct trap_info *info) 781 { 782 unsigned long addr; 783 784 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT) 785 return 0; 786 787 info->vector = vector; 788 789 addr = gate_offset(val); 790 if (!get_trap_addr((void **)&addr, val->bits.ist)) 791 return 0; 792 info->address = addr; 793 794 info->cs = gate_segment(val); 795 info->flags = val->bits.dpl; 796 /* interrupt gates clear IF */ 797 if (val->bits.type == GATE_INTERRUPT) 798 info->flags |= 1 << 2; 799 800 return 1; 801 } 802 803 /* Locations of each CPU's IDT */ 804 static DEFINE_PER_CPU(struct desc_ptr, idt_desc); 805 806 /* Set an IDT entry. If the entry is part of the current IDT, then 807 also update Xen. */ 808 static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) 809 { 810 unsigned long p = (unsigned long)&dt[entrynum]; 811 unsigned long start, end; 812 813 trace_xen_cpu_write_idt_entry(dt, entrynum, g); 814 815 preempt_disable(); 816 817 start = __this_cpu_read(idt_desc.address); 818 end = start + __this_cpu_read(idt_desc.size) + 1; 819 820 xen_mc_flush(); 821 822 native_write_idt_entry(dt, entrynum, g); 823 824 if (p >= start && (p + 8) <= end) { 825 struct trap_info info[2]; 826 827 info[1].address = 0; 828 829 if (cvt_gate_to_trap(entrynum, g, &info[0])) 830 if (HYPERVISOR_set_trap_table(info)) 831 BUG(); 832 } 833 834 preempt_enable(); 835 } 836 837 static unsigned xen_convert_trap_info(const struct desc_ptr *desc, 838 struct trap_info *traps, bool full) 839 { 840 unsigned in, out, count; 841 842 count = (desc->size+1) / sizeof(gate_desc); 843 BUG_ON(count > 256); 844 845 for (in = out = 0; in < count; in++) { 846 gate_desc *entry = (gate_desc *)(desc->address) + in; 847 848 if (cvt_gate_to_trap(in, entry, &traps[out]) || full) 849 out++; 850 } 851 852 return out; 853 } 854 855 void xen_copy_trap_info(struct trap_info *traps) 856 { 857 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc); 858 859 xen_convert_trap_info(desc, traps, true); 860 } 861 862 /* Load a new IDT into Xen. In principle this can be per-CPU, so we 863 hold a spinlock to protect the static traps[] array (static because 864 it avoids allocation, and saves stack space). */ 865 static void xen_load_idt(const struct desc_ptr *desc) 866 { 867 static DEFINE_SPINLOCK(lock); 868 static struct trap_info traps[257]; 869 static const struct trap_info zero = { }; 870 unsigned out; 871 872 trace_xen_cpu_load_idt(desc); 873 874 spin_lock(&lock); 875 876 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); 877 878 out = xen_convert_trap_info(desc, traps, false); 879 traps[out] = zero; 880 881 xen_mc_flush(); 882 if (HYPERVISOR_set_trap_table(traps)) 883 BUG(); 884 885 spin_unlock(&lock); 886 } 887 888 /* Write a GDT descriptor entry. Ignore LDT descriptors, since 889 they're handled differently. */ 890 static void xen_write_gdt_entry(struct desc_struct *dt, int entry, 891 const void *desc, int type) 892 { 893 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 894 895 preempt_disable(); 896 897 switch (type) { 898 case DESC_LDT: 899 case DESC_TSS: 900 /* ignore */ 901 break; 902 903 default: { 904 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]); 905 906 xen_mc_flush(); 907 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 908 BUG(); 909 } 910 911 } 912 913 preempt_enable(); 914 } 915 916 /* 917 * Version of write_gdt_entry for use at early boot-time needed to 918 * update an entry as simply as possible. 919 */ 920 static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry, 921 const void *desc, int type) 922 { 923 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 924 925 switch (type) { 926 case DESC_LDT: 927 case DESC_TSS: 928 /* ignore */ 929 break; 930 931 default: { 932 xmaddr_t maddr = virt_to_machine(&dt[entry]); 933 934 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 935 dt[entry] = *(struct desc_struct *)desc; 936 } 937 938 } 939 } 940 941 static void xen_load_sp0(unsigned long sp0) 942 { 943 struct multicall_space mcs; 944 945 mcs = xen_mc_entry(0); 946 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0); 947 xen_mc_issue(XEN_LAZY_CPU); 948 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 949 } 950 951 #ifdef CONFIG_X86_IOPL_IOPERM 952 static void xen_invalidate_io_bitmap(void) 953 { 954 struct physdev_set_iobitmap iobitmap = { 955 .bitmap = NULL, 956 .nr_ports = 0, 957 }; 958 959 native_tss_invalidate_io_bitmap(); 960 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 961 } 962 963 static void xen_update_io_bitmap(void) 964 { 965 struct physdev_set_iobitmap iobitmap; 966 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 967 968 native_tss_update_io_bitmap(); 969 970 iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) + 971 tss->x86_tss.io_bitmap_base; 972 if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID) 973 iobitmap.nr_ports = 0; 974 else 975 iobitmap.nr_ports = IO_BITMAP_BITS; 976 977 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 978 } 979 #endif 980 981 static void xen_io_delay(void) 982 { 983 } 984 985 static DEFINE_PER_CPU(unsigned long, xen_cr0_value); 986 987 static unsigned long xen_read_cr0(void) 988 { 989 unsigned long cr0 = this_cpu_read(xen_cr0_value); 990 991 if (unlikely(cr0 == 0)) { 992 cr0 = native_read_cr0(); 993 this_cpu_write(xen_cr0_value, cr0); 994 } 995 996 return cr0; 997 } 998 999 static void xen_write_cr0(unsigned long cr0) 1000 { 1001 struct multicall_space mcs; 1002 1003 this_cpu_write(xen_cr0_value, cr0); 1004 1005 /* Only pay attention to cr0.TS; everything else is 1006 ignored. */ 1007 mcs = xen_mc_entry(0); 1008 1009 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0); 1010 1011 xen_mc_issue(XEN_LAZY_CPU); 1012 } 1013 1014 static void xen_write_cr4(unsigned long cr4) 1015 { 1016 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE); 1017 1018 native_write_cr4(cr4); 1019 } 1020 1021 static u64 xen_do_read_msr(unsigned int msr, int *err) 1022 { 1023 u64 val = 0; /* Avoid uninitialized value for safe variant. */ 1024 1025 if (pmu_msr_read(msr, &val, err)) 1026 return val; 1027 1028 if (err) 1029 val = native_read_msr_safe(msr, err); 1030 else 1031 val = native_read_msr(msr); 1032 1033 switch (msr) { 1034 case MSR_IA32_APICBASE: 1035 val &= ~X2APIC_ENABLE; 1036 if (smp_processor_id() == 0) 1037 val |= MSR_IA32_APICBASE_BSP; 1038 else 1039 val &= ~MSR_IA32_APICBASE_BSP; 1040 break; 1041 } 1042 return val; 1043 } 1044 1045 static void set_seg(unsigned int which, unsigned int low, unsigned int high, 1046 int *err) 1047 { 1048 u64 base = ((u64)high << 32) | low; 1049 1050 if (HYPERVISOR_set_segment_base(which, base) == 0) 1051 return; 1052 1053 if (err) 1054 *err = -EIO; 1055 else 1056 WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base); 1057 } 1058 1059 /* 1060 * Support write_msr_safe() and write_msr() semantics. 1061 * With err == NULL write_msr() semantics are selected. 1062 * Supplying an err pointer requires err to be pre-initialized with 0. 1063 */ 1064 static void xen_do_write_msr(unsigned int msr, unsigned int low, 1065 unsigned int high, int *err) 1066 { 1067 switch (msr) { 1068 case MSR_FS_BASE: 1069 set_seg(SEGBASE_FS, low, high, err); 1070 break; 1071 1072 case MSR_KERNEL_GS_BASE: 1073 set_seg(SEGBASE_GS_USER, low, high, err); 1074 break; 1075 1076 case MSR_GS_BASE: 1077 set_seg(SEGBASE_GS_KERNEL, low, high, err); 1078 break; 1079 1080 case MSR_STAR: 1081 case MSR_CSTAR: 1082 case MSR_LSTAR: 1083 case MSR_SYSCALL_MASK: 1084 case MSR_IA32_SYSENTER_CS: 1085 case MSR_IA32_SYSENTER_ESP: 1086 case MSR_IA32_SYSENTER_EIP: 1087 /* Fast syscall setup is all done in hypercalls, so 1088 these are all ignored. Stub them out here to stop 1089 Xen console noise. */ 1090 break; 1091 1092 default: 1093 if (!pmu_msr_write(msr, low, high, err)) { 1094 if (err) 1095 *err = native_write_msr_safe(msr, low, high); 1096 else 1097 native_write_msr(msr, low, high); 1098 } 1099 } 1100 } 1101 1102 static u64 xen_read_msr_safe(unsigned int msr, int *err) 1103 { 1104 return xen_do_read_msr(msr, err); 1105 } 1106 1107 static int xen_write_msr_safe(unsigned int msr, unsigned int low, 1108 unsigned int high) 1109 { 1110 int err = 0; 1111 1112 xen_do_write_msr(msr, low, high, &err); 1113 1114 return err; 1115 } 1116 1117 static u64 xen_read_msr(unsigned int msr) 1118 { 1119 int err; 1120 1121 return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); 1122 } 1123 1124 static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) 1125 { 1126 int err; 1127 1128 xen_do_write_msr(msr, low, high, xen_msr_safe ? &err : NULL); 1129 } 1130 1131 /* This is called once we have the cpu_possible_mask */ 1132 void __init xen_setup_vcpu_info_placement(void) 1133 { 1134 int cpu; 1135 1136 for_each_possible_cpu(cpu) { 1137 /* Set up direct vCPU id mapping for PV guests. */ 1138 per_cpu(xen_vcpu_id, cpu) = cpu; 1139 xen_vcpu_setup(cpu); 1140 } 1141 1142 pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct); 1143 pv_ops.irq.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); 1144 pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); 1145 pv_ops.mmu.read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2_direct); 1146 } 1147 1148 static const struct pv_info xen_info __initconst = { 1149 .extra_user_64bit_cs = FLAT_USER_CS64, 1150 .name = "Xen", 1151 }; 1152 1153 static const typeof(pv_ops) xen_cpu_ops __initconst = { 1154 .cpu = { 1155 .cpuid = xen_cpuid, 1156 1157 .set_debugreg = xen_set_debugreg, 1158 .get_debugreg = xen_get_debugreg, 1159 1160 .read_cr0 = xen_read_cr0, 1161 .write_cr0 = xen_write_cr0, 1162 1163 .write_cr4 = xen_write_cr4, 1164 1165 .read_msr = xen_read_msr, 1166 .write_msr = xen_write_msr, 1167 1168 .read_msr_safe = xen_read_msr_safe, 1169 .write_msr_safe = xen_write_msr_safe, 1170 1171 .read_pmc = xen_read_pmc, 1172 1173 .load_tr_desc = paravirt_nop, 1174 .set_ldt = xen_set_ldt, 1175 .load_gdt = xen_load_gdt, 1176 .load_idt = xen_load_idt, 1177 .load_tls = xen_load_tls, 1178 .load_gs_index = xen_load_gs_index, 1179 1180 .alloc_ldt = xen_alloc_ldt, 1181 .free_ldt = xen_free_ldt, 1182 1183 .store_tr = xen_store_tr, 1184 1185 .write_ldt_entry = xen_write_ldt_entry, 1186 .write_gdt_entry = xen_write_gdt_entry, 1187 .write_idt_entry = xen_write_idt_entry, 1188 .load_sp0 = xen_load_sp0, 1189 1190 #ifdef CONFIG_X86_IOPL_IOPERM 1191 .invalidate_io_bitmap = xen_invalidate_io_bitmap, 1192 .update_io_bitmap = xen_update_io_bitmap, 1193 #endif 1194 .io_delay = xen_io_delay, 1195 1196 .start_context_switch = xen_start_context_switch, 1197 .end_context_switch = xen_end_context_switch, 1198 }, 1199 }; 1200 1201 static void xen_restart(char *msg) 1202 { 1203 xen_reboot(SHUTDOWN_reboot); 1204 } 1205 1206 static void xen_machine_halt(void) 1207 { 1208 xen_reboot(SHUTDOWN_poweroff); 1209 } 1210 1211 static void xen_machine_power_off(void) 1212 { 1213 do_kernel_power_off(); 1214 xen_reboot(SHUTDOWN_poweroff); 1215 } 1216 1217 static void xen_crash_shutdown(struct pt_regs *regs) 1218 { 1219 xen_reboot(SHUTDOWN_crash); 1220 } 1221 1222 static const struct machine_ops xen_machine_ops __initconst = { 1223 .restart = xen_restart, 1224 .halt = xen_machine_halt, 1225 .power_off = xen_machine_power_off, 1226 .shutdown = xen_machine_halt, 1227 .crash_shutdown = xen_crash_shutdown, 1228 .emergency_restart = xen_emergency_restart, 1229 }; 1230 1231 static unsigned char xen_get_nmi_reason(void) 1232 { 1233 unsigned char reason = 0; 1234 1235 /* Construct a value which looks like it came from port 0x61. */ 1236 if (test_bit(_XEN_NMIREASON_io_error, 1237 &HYPERVISOR_shared_info->arch.nmi_reason)) 1238 reason |= NMI_REASON_IOCHK; 1239 if (test_bit(_XEN_NMIREASON_pci_serr, 1240 &HYPERVISOR_shared_info->arch.nmi_reason)) 1241 reason |= NMI_REASON_SERR; 1242 1243 return reason; 1244 } 1245 1246 static void __init xen_boot_params_init_edd(void) 1247 { 1248 #if IS_ENABLED(CONFIG_EDD) 1249 struct xen_platform_op op; 1250 struct edd_info *edd_info; 1251 u32 *mbr_signature; 1252 unsigned nr; 1253 int ret; 1254 1255 edd_info = boot_params.eddbuf; 1256 mbr_signature = boot_params.edd_mbr_sig_buffer; 1257 1258 op.cmd = XENPF_firmware_info; 1259 1260 op.u.firmware_info.type = XEN_FW_DISK_INFO; 1261 for (nr = 0; nr < EDDMAXNR; nr++) { 1262 struct edd_info *info = edd_info + nr; 1263 1264 op.u.firmware_info.index = nr; 1265 info->params.length = sizeof(info->params); 1266 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params, 1267 &info->params); 1268 ret = HYPERVISOR_platform_op(&op); 1269 if (ret) 1270 break; 1271 1272 #define C(x) info->x = op.u.firmware_info.u.disk_info.x 1273 C(device); 1274 C(version); 1275 C(interface_support); 1276 C(legacy_max_cylinder); 1277 C(legacy_max_head); 1278 C(legacy_sectors_per_track); 1279 #undef C 1280 } 1281 boot_params.eddbuf_entries = nr; 1282 1283 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE; 1284 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) { 1285 op.u.firmware_info.index = nr; 1286 ret = HYPERVISOR_platform_op(&op); 1287 if (ret) 1288 break; 1289 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature; 1290 } 1291 boot_params.edd_mbr_sig_buf_entries = nr; 1292 #endif 1293 } 1294 1295 /* 1296 * Set up the GDT and segment registers for -fstack-protector. Until 1297 * we do this, we have to be careful not to call any stack-protected 1298 * function, which is most of the kernel. 1299 */ 1300 static void __init xen_setup_gdt(int cpu) 1301 { 1302 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot; 1303 pv_ops.cpu.load_gdt = xen_load_gdt_boot; 1304 1305 switch_gdt_and_percpu_base(cpu); 1306 1307 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry; 1308 pv_ops.cpu.load_gdt = xen_load_gdt; 1309 } 1310 1311 static void __init xen_dom0_set_legacy_features(void) 1312 { 1313 x86_platform.legacy.rtc = 1; 1314 } 1315 1316 static void __init xen_domu_set_legacy_features(void) 1317 { 1318 x86_platform.legacy.rtc = 0; 1319 } 1320 1321 extern void early_xen_iret_patch(void); 1322 1323 /* First C function to be called on Xen boot */ 1324 asmlinkage __visible void __init xen_start_kernel(struct start_info *si) 1325 { 1326 struct physdev_set_iopl set_iopl; 1327 unsigned long initrd_start = 0; 1328 int rc; 1329 1330 if (!si) 1331 return; 1332 1333 clear_bss(); 1334 1335 xen_start_info = si; 1336 1337 __text_gen_insn(&early_xen_iret_patch, 1338 JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret, 1339 JMP32_INSN_SIZE); 1340 1341 xen_domain_type = XEN_PV_DOMAIN; 1342 xen_start_flags = xen_start_info->flags; 1343 /* Interrupts are guaranteed to be off initially. */ 1344 early_boot_irqs_disabled = true; 1345 static_call_update_early(xen_hypercall, xen_hypercall_pv); 1346 1347 xen_setup_features(); 1348 1349 /* Install Xen paravirt ops */ 1350 pv_info = xen_info; 1351 pv_ops.cpu = xen_cpu_ops.cpu; 1352 xen_init_irq_ops(); 1353 1354 /* 1355 * Setup xen_vcpu early because it is needed for 1356 * local_irq_disable(), irqs_disabled(), e.g. in printk(). 1357 * 1358 * Don't do the full vcpu_info placement stuff until we have 1359 * the cpu_possible_mask and a non-dummy shared_info. 1360 */ 1361 xen_vcpu_info_reset(0); 1362 1363 x86_platform.get_nmi_reason = xen_get_nmi_reason; 1364 x86_platform.realmode_reserve = x86_init_noop; 1365 x86_platform.realmode_init = x86_init_noop; 1366 1367 x86_init.resources.memory_setup = xen_memory_setup; 1368 x86_init.irqs.intr_mode_select = x86_init_noop; 1369 x86_init.irqs.intr_mode_init = x86_64_probe_apic; 1370 x86_init.oem.arch_setup = xen_arch_setup; 1371 x86_init.oem.banner = xen_banner; 1372 x86_init.hyper.init_platform = xen_pv_init_platform; 1373 x86_init.hyper.guest_late_init = xen_pv_guest_late_init; 1374 1375 /* 1376 * Set up some pagetable state before starting to set any ptes. 1377 */ 1378 1379 xen_setup_machphys_mapping(); 1380 xen_init_mmu_ops(); 1381 1382 /* Prevent unwanted bits from being set in PTEs. */ 1383 __supported_pte_mask &= ~_PAGE_GLOBAL; 1384 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 1385 1386 /* Get mfn list */ 1387 xen_build_dynamic_phys_to_machine(); 1388 1389 /* Work out if we support NX */ 1390 get_cpu_cap(&boot_cpu_data); 1391 x86_configure_nx(); 1392 1393 /* 1394 * Set up kernel GDT and segment registers, mainly so that 1395 * -fstack-protector code can be executed. 1396 */ 1397 xen_setup_gdt(0); 1398 1399 /* Determine virtual and physical address sizes */ 1400 get_cpu_address_sizes(&boot_cpu_data); 1401 1402 /* Let's presume PV guests always boot on vCPU with id 0. */ 1403 per_cpu(xen_vcpu_id, 0) = 0; 1404 1405 idt_setup_early_handler(); 1406 1407 xen_init_capabilities(); 1408 1409 /* 1410 * set up the basic apic ops. 1411 */ 1412 xen_init_apic(); 1413 1414 machine_ops = xen_machine_ops; 1415 1416 /* 1417 * The only reliable way to retain the initial address of the 1418 * percpu gdt_page is to remember it here, so we can go and 1419 * mark it RW later, when the initial percpu area is freed. 1420 */ 1421 xen_initial_gdt = &per_cpu(gdt_page, 0); 1422 1423 xen_smp_init(); 1424 1425 #ifdef CONFIG_ACPI_NUMA 1426 /* 1427 * The pages we from Xen are not related to machine pages, so 1428 * any NUMA information the kernel tries to get from ACPI will 1429 * be meaningless. Prevent it from trying. 1430 */ 1431 disable_srat(); 1432 #endif 1433 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); 1434 1435 local_irq_disable(); 1436 1437 xen_raw_console_write("mapping kernel into physical memory\n"); 1438 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, 1439 xen_start_info->nr_pages); 1440 xen_reserve_special_pages(); 1441 1442 /* 1443 * We used to do this in xen_arch_setup, but that is too late 1444 * on AMD were early_cpu_init (run before ->arch_setup()) calls 1445 * early_amd_init which pokes 0xcf8 port. 1446 */ 1447 set_iopl.iopl = 1; 1448 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); 1449 if (rc != 0) 1450 xen_raw_printk("physdev_op failed %d\n", rc); 1451 1452 1453 if (xen_start_info->mod_start) { 1454 if (xen_start_info->flags & SIF_MOD_START_PFN) 1455 initrd_start = PFN_PHYS(xen_start_info->mod_start); 1456 else 1457 initrd_start = __pa(xen_start_info->mod_start); 1458 } 1459 1460 /* Poke various useful things into boot_params */ 1461 boot_params.hdr.type_of_loader = (9 << 4) | 0; 1462 boot_params.hdr.ramdisk_image = initrd_start; 1463 boot_params.hdr.ramdisk_size = xen_start_info->mod_len; 1464 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); 1465 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN; 1466 1467 if (!xen_initial_domain()) { 1468 if (pci_xen) 1469 x86_init.pci.arch_init = pci_xen_init; 1470 x86_platform.set_legacy_features = 1471 xen_domu_set_legacy_features; 1472 } else { 1473 const struct dom0_vga_console_info *info = 1474 (void *)((char *)xen_start_info + 1475 xen_start_info->console.dom0.info_off); 1476 struct xen_platform_op op = { 1477 .cmd = XENPF_firmware_info, 1478 .interface_version = XENPF_INTERFACE_VERSION, 1479 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS, 1480 }; 1481 1482 x86_platform.set_legacy_features = 1483 xen_dom0_set_legacy_features; 1484 xen_init_vga(info, xen_start_info->console.dom0.info_size, 1485 &boot_params.screen_info); 1486 xen_start_info->console.domU.mfn = 0; 1487 xen_start_info->console.domU.evtchn = 0; 1488 1489 if (HYPERVISOR_platform_op(&op) == 0) 1490 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags; 1491 1492 /* Make sure ACS will be enabled */ 1493 pci_request_acs(); 1494 1495 xen_acpi_sleep_register(); 1496 1497 xen_boot_params_init_edd(); 1498 1499 #ifdef CONFIG_ACPI 1500 /* 1501 * Disable selecting "Firmware First mode" for correctable 1502 * memory errors, as this is the duty of the hypervisor to 1503 * decide. 1504 */ 1505 acpi_disable_cmcff = 1; 1506 #endif 1507 } 1508 1509 xen_add_preferred_consoles(); 1510 1511 #ifdef CONFIG_PCI 1512 /* PCI BIOS service won't work from a PV guest. */ 1513 pci_probe &= ~PCI_PROBE_BIOS; 1514 #endif 1515 xen_raw_console_write("about to get started...\n"); 1516 1517 /* We need this for printk timestamps */ 1518 xen_setup_runstate_info(0); 1519 1520 xen_efi_init(&boot_params); 1521 1522 /* Start the world */ 1523 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */ 1524 x86_64_start_reservations((char *)__pa_symbol(&boot_params)); 1525 } 1526 1527 static int xen_cpu_up_prepare_pv(unsigned int cpu) 1528 { 1529 int rc; 1530 1531 if (per_cpu(xen_vcpu, cpu) == NULL) 1532 return -ENODEV; 1533 1534 xen_setup_timer(cpu); 1535 1536 rc = xen_smp_intr_init(cpu); 1537 if (rc) { 1538 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n", 1539 cpu, rc); 1540 return rc; 1541 } 1542 1543 rc = xen_smp_intr_init_pv(cpu); 1544 if (rc) { 1545 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n", 1546 cpu, rc); 1547 return rc; 1548 } 1549 1550 return 0; 1551 } 1552 1553 static int xen_cpu_dead_pv(unsigned int cpu) 1554 { 1555 xen_smp_intr_free(cpu); 1556 xen_smp_intr_free_pv(cpu); 1557 1558 xen_teardown_timer(cpu); 1559 1560 return 0; 1561 } 1562 1563 static uint32_t __init xen_platform_pv(void) 1564 { 1565 if (xen_pv_domain()) 1566 return xen_cpuid_base(); 1567 1568 return 0; 1569 } 1570 1571 const __initconst struct hypervisor_x86 x86_hyper_xen_pv = { 1572 .name = "Xen PV", 1573 .detect = xen_platform_pv, 1574 .type = X86_HYPER_XEN_PV, 1575 .runtime.pin_vcpu = xen_pin_vcpu, 1576 .ignore_nopv = true, 1577 }; 1578