1 /* 2 * Suspend support specific for i386/x86-64. 3 * 4 * Distribute under GPLv2 5 * 6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl> 7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz> 8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org> 9 */ 10 11 #include <linux/suspend.h> 12 #include <linux/export.h> 13 #include <linux/smp.h> 14 #include <linux/perf_event.h> 15 16 #include <asm/pgtable.h> 17 #include <asm/proto.h> 18 #include <asm/mtrr.h> 19 #include <asm/page.h> 20 #include <asm/mce.h> 21 #include <asm/xcr.h> 22 #include <asm/suspend.h> 23 #include <asm/debugreg.h> 24 #include <asm/fpu-internal.h> /* pcntxt_mask */ 25 #include <asm/cpu.h> 26 27 #ifdef CONFIG_X86_32 28 static struct saved_context saved_context; 29 30 unsigned long saved_context_ebx; 31 unsigned long saved_context_esp, saved_context_ebp; 32 unsigned long saved_context_esi, saved_context_edi; 33 unsigned long saved_context_eflags; 34 #else 35 /* CONFIG_X86_64 */ 36 struct saved_context saved_context; 37 #endif 38 39 /** 40 * __save_processor_state - save CPU registers before creating a 41 * hibernation image and before restoring the memory state from it 42 * @ctxt - structure to store the registers contents in 43 * 44 * NOTE: If there is a CPU register the modification of which by the 45 * boot kernel (ie. the kernel used for loading the hibernation image) 46 * might affect the operations of the restored target kernel (ie. the one 47 * saved in the hibernation image), then its contents must be saved by this 48 * function. In other words, if kernel A is hibernated and different 49 * kernel B is used for loading the hibernation image into memory, the 50 * kernel A's __save_processor_state() function must save all registers 51 * needed by kernel A, so that it can operate correctly after the resume 52 * regardless of what kernel B does in the meantime. 53 */ 54 static void __save_processor_state(struct saved_context *ctxt) 55 { 56 #ifdef CONFIG_X86_32 57 mtrr_save_fixed_ranges(NULL); 58 #endif 59 kernel_fpu_begin(); 60 61 /* 62 * descriptor tables 63 */ 64 #ifdef CONFIG_X86_32 65 store_gdt(&ctxt->gdt); 66 store_idt(&ctxt->idt); 67 #else 68 /* CONFIG_X86_64 */ 69 store_gdt((struct desc_ptr *)&ctxt->gdt_limit); 70 store_idt((struct desc_ptr *)&ctxt->idt_limit); 71 #endif 72 store_tr(ctxt->tr); 73 74 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */ 75 /* 76 * segment registers 77 */ 78 #ifdef CONFIG_X86_32 79 savesegment(es, ctxt->es); 80 savesegment(fs, ctxt->fs); 81 savesegment(gs, ctxt->gs); 82 savesegment(ss, ctxt->ss); 83 #else 84 /* CONFIG_X86_64 */ 85 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds)); 86 asm volatile ("movw %%es, %0" : "=m" (ctxt->es)); 87 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs)); 88 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs)); 89 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss)); 90 91 rdmsrl(MSR_FS_BASE, ctxt->fs_base); 92 rdmsrl(MSR_GS_BASE, ctxt->gs_base); 93 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); 94 mtrr_save_fixed_ranges(NULL); 95 96 rdmsrl(MSR_EFER, ctxt->efer); 97 #endif 98 99 /* 100 * control registers 101 */ 102 ctxt->cr0 = read_cr0(); 103 ctxt->cr2 = read_cr2(); 104 ctxt->cr3 = read_cr3(); 105 #ifdef CONFIG_X86_32 106 ctxt->cr4 = read_cr4_safe(); 107 #else 108 /* CONFIG_X86_64 */ 109 ctxt->cr4 = read_cr4(); 110 ctxt->cr8 = read_cr8(); 111 #endif 112 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, 113 &ctxt->misc_enable); 114 } 115 116 /* Needed by apm.c */ 117 void save_processor_state(void) 118 { 119 __save_processor_state(&saved_context); 120 x86_platform.save_sched_clock_state(); 121 } 122 #ifdef CONFIG_X86_32 123 EXPORT_SYMBOL(save_processor_state); 124 #endif 125 126 static void do_fpu_end(void) 127 { 128 /* 129 * Restore FPU regs if necessary. 130 */ 131 kernel_fpu_end(); 132 } 133 134 static void fix_processor_context(void) 135 { 136 int cpu = smp_processor_id(); 137 struct tss_struct *t = &per_cpu(init_tss, cpu); 138 139 set_tss_desc(cpu, t); /* 140 * This just modifies memory; should not be 141 * necessary. But... This is necessary, because 142 * 386 hardware has concept of busy TSS or some 143 * similar stupidity. 144 */ 145 146 #ifdef CONFIG_X86_64 147 get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9; 148 149 syscall_init(); /* This sets MSR_*STAR and related */ 150 #endif 151 load_TR_desc(); /* This does ltr */ 152 load_LDT(¤t->active_mm->context); /* This does lldt */ 153 } 154 155 /** 156 * __restore_processor_state - restore the contents of CPU registers saved 157 * by __save_processor_state() 158 * @ctxt - structure to load the registers contents from 159 */ 160 static void __restore_processor_state(struct saved_context *ctxt) 161 { 162 if (ctxt->misc_enable_saved) 163 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); 164 /* 165 * control registers 166 */ 167 /* cr4 was introduced in the Pentium CPU */ 168 #ifdef CONFIG_X86_32 169 if (ctxt->cr4) 170 write_cr4(ctxt->cr4); 171 #else 172 /* CONFIG X86_64 */ 173 wrmsrl(MSR_EFER, ctxt->efer); 174 write_cr8(ctxt->cr8); 175 write_cr4(ctxt->cr4); 176 #endif 177 write_cr3(ctxt->cr3); 178 write_cr2(ctxt->cr2); 179 write_cr0(ctxt->cr0); 180 181 /* 182 * now restore the descriptor tables to their proper values 183 * ltr is done i fix_processor_context(). 184 */ 185 #ifdef CONFIG_X86_32 186 load_gdt(&ctxt->gdt); 187 load_idt(&ctxt->idt); 188 #else 189 /* CONFIG_X86_64 */ 190 load_gdt((const struct desc_ptr *)&ctxt->gdt_limit); 191 load_idt((const struct desc_ptr *)&ctxt->idt_limit); 192 #endif 193 194 /* 195 * segment registers 196 */ 197 #ifdef CONFIG_X86_32 198 loadsegment(es, ctxt->es); 199 loadsegment(fs, ctxt->fs); 200 loadsegment(gs, ctxt->gs); 201 loadsegment(ss, ctxt->ss); 202 203 /* 204 * sysenter MSRs 205 */ 206 if (boot_cpu_has(X86_FEATURE_SEP)) 207 enable_sep_cpu(); 208 #else 209 /* CONFIG_X86_64 */ 210 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds)); 211 asm volatile ("movw %0, %%es" :: "r" (ctxt->es)); 212 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs)); 213 load_gs_index(ctxt->gs); 214 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss)); 215 216 wrmsrl(MSR_FS_BASE, ctxt->fs_base); 217 wrmsrl(MSR_GS_BASE, ctxt->gs_base); 218 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); 219 #endif 220 221 /* 222 * restore XCR0 for xsave capable cpu's. 223 */ 224 if (cpu_has_xsave) 225 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask); 226 227 fix_processor_context(); 228 229 do_fpu_end(); 230 x86_platform.restore_sched_clock_state(); 231 mtrr_bp_restore(); 232 perf_restore_debug_store(); 233 } 234 235 /* Needed by apm.c */ 236 void restore_processor_state(void) 237 { 238 __restore_processor_state(&saved_context); 239 } 240 #ifdef CONFIG_X86_32 241 EXPORT_SYMBOL(restore_processor_state); 242 #endif 243 244 /* 245 * When bsp_check() is called in hibernate and suspend, cpu hotplug 246 * is disabled already. So it's unnessary to handle race condition between 247 * cpumask query and cpu hotplug. 248 */ 249 static int bsp_check(void) 250 { 251 if (cpumask_first(cpu_online_mask) != 0) { 252 pr_warn("CPU0 is offline.\n"); 253 return -ENODEV; 254 } 255 256 return 0; 257 } 258 259 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action, 260 void *ptr) 261 { 262 int ret = 0; 263 264 switch (action) { 265 case PM_SUSPEND_PREPARE: 266 case PM_HIBERNATION_PREPARE: 267 ret = bsp_check(); 268 break; 269 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0 270 case PM_RESTORE_PREPARE: 271 /* 272 * When system resumes from hibernation, online CPU0 because 273 * 1. it's required for resume and 274 * 2. the CPU was online before hibernation 275 */ 276 if (!cpu_online(0)) 277 _debug_hotplug_cpu(0, 1); 278 break; 279 case PM_POST_RESTORE: 280 /* 281 * When a resume really happens, this code won't be called. 282 * 283 * This code is called only when user space hibernation software 284 * prepares for snapshot device during boot time. So we just 285 * call _debug_hotplug_cpu() to restore to CPU0's state prior to 286 * preparing the snapshot device. 287 * 288 * This works for normal boot case in our CPU0 hotplug debug 289 * mode, i.e. CPU0 is offline and user mode hibernation 290 * software initializes during boot time. 291 * 292 * If CPU0 is online and user application accesses snapshot 293 * device after boot time, this will offline CPU0 and user may 294 * see different CPU0 state before and after accessing 295 * the snapshot device. But hopefully this is not a case when 296 * user debugging CPU0 hotplug. Even if users hit this case, 297 * they can easily online CPU0 back. 298 * 299 * To simplify this debug code, we only consider normal boot 300 * case. Otherwise we need to remember CPU0's state and restore 301 * to that state and resolve racy conditions etc. 302 */ 303 _debug_hotplug_cpu(0, 0); 304 break; 305 #endif 306 default: 307 break; 308 } 309 return notifier_from_errno(ret); 310 } 311 312 static int __init bsp_pm_check_init(void) 313 { 314 /* 315 * Set this bsp_pm_callback as lower priority than 316 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called 317 * earlier to disable cpu hotplug before bsp online check. 318 */ 319 pm_notifier(bsp_pm_callback, -INT_MAX); 320 return 0; 321 } 322 323 core_initcall(bsp_pm_check_init); 324