1 /* 2 * Intel CE4100 platform specific setup code 3 * 4 * (C) Copyright 2010 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; version 2 9 * of the License. 10 */ 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/serial_reg.h> 16 #include <linux/serial_8250.h> 17 18 #include <asm/ce4100.h> 19 #include <asm/prom.h> 20 #include <asm/setup.h> 21 #include <asm/i8259.h> 22 #include <asm/io.h> 23 #include <asm/io_apic.h> 24 25 static int ce4100_i8042_detect(void) 26 { 27 return 0; 28 } 29 30 #ifdef CONFIG_SERIAL_8250 31 32 static unsigned int mem_serial_in(struct uart_port *p, int offset) 33 { 34 offset = offset << p->regshift; 35 return readl(p->membase + offset); 36 } 37 38 /* 39 * The UART Tx interrupts are not set under some conditions and therefore serial 40 * transmission hangs. This is a silicon issue and has not been root caused. The 41 * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT 42 * bit of LSR register in interrupt handler to see whether at least one of these 43 * two bits is set, if so then process the transmit request. If this workaround 44 * is not applied, then the serial transmission may hang. This workaround is for 45 * errata number 9 in Errata - B step. 46 */ 47 48 static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset) 49 { 50 unsigned int ret, ier, lsr; 51 52 if (offset == UART_IIR) { 53 offset = offset << p->regshift; 54 ret = readl(p->membase + offset); 55 if (ret & UART_IIR_NO_INT) { 56 /* see if the TX interrupt should have really set */ 57 ier = mem_serial_in(p, UART_IER); 58 /* see if the UART's XMIT interrupt is enabled */ 59 if (ier & UART_IER_THRI) { 60 lsr = mem_serial_in(p, UART_LSR); 61 /* now check to see if the UART should be 62 generating an interrupt (but isn't) */ 63 if (lsr & (UART_LSR_THRE | UART_LSR_TEMT)) 64 ret &= ~UART_IIR_NO_INT; 65 } 66 } 67 } else 68 ret = mem_serial_in(p, offset); 69 return ret; 70 } 71 72 static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value) 73 { 74 offset = offset << p->regshift; 75 writel(value, p->membase + offset); 76 } 77 78 static void ce4100_serial_fixup(int port, struct uart_port *up, 79 unsigned short *capabilites) 80 { 81 #ifdef CONFIG_EARLY_PRINTK 82 /* 83 * Over ride the legacy port configuration that comes from 84 * asm/serial.h. Using the ioport driver then switching to the 85 * PCI memmaped driver hangs the IOAPIC 86 */ 87 if (up->iotype != UPIO_MEM32) { 88 up->uartclk = 14745600; 89 up->mapbase = 0xdffe0200; 90 set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, 91 up->mapbase & PAGE_MASK); 92 up->membase = 93 (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE); 94 up->membase += up->mapbase & ~PAGE_MASK; 95 up->iotype = UPIO_MEM32; 96 up->regshift = 2; 97 } 98 #endif 99 up->iobase = 0; 100 up->serial_in = ce4100_mem_serial_in; 101 up->serial_out = ce4100_mem_serial_out; 102 103 *capabilites |= (1 << 12); 104 } 105 106 static __init void sdv_serial_fixup(void) 107 { 108 serial8250_set_isa_configurator(ce4100_serial_fixup); 109 } 110 111 #else 112 static inline void sdv_serial_fixup(void) {}; 113 #endif 114 115 static void __init sdv_arch_setup(void) 116 { 117 sdv_serial_fixup(); 118 } 119 120 #ifdef CONFIG_X86_IO_APIC 121 static void __cpuinit sdv_pci_init(void) 122 { 123 x86_of_pci_init(); 124 /* We can't set this earlier, because we need to calibrate the timer */ 125 legacy_pic = &null_legacy_pic; 126 } 127 #endif 128 129 /* 130 * CE4100 specific x86_init function overrides and early setup 131 * calls. 132 */ 133 void __init x86_ce4100_early_setup(void) 134 { 135 x86_init.oem.arch_setup = sdv_arch_setup; 136 x86_platform.i8042_detect = ce4100_i8042_detect; 137 x86_init.resources.probe_roms = x86_init_noop; 138 x86_init.mpparse.get_smp_config = x86_init_uint_noop; 139 x86_init.mpparse.find_smp_config = x86_init_noop; 140 x86_init.pci.init = ce4100_pci_init; 141 142 #ifdef CONFIG_X86_IO_APIC 143 x86_init.pci.init_irq = sdv_pci_init; 144 x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck; 145 #endif 146 } 147