1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Low-level direct PCI config space access via ECAM - common code between 4 * i386 and x86-64. 5 * 6 * This code does: 7 * - known chipset handling 8 * - ACPI decoding and validation 9 * 10 * Per-architecture code takes care of the mappings and accesses 11 * themselves. 12 */ 13 14 #define pr_fmt(fmt) "PCI: " fmt 15 16 #include <linux/acpi.h> 17 #include <linux/efi.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/bitmap.h> 21 #include <linux/dmi.h> 22 #include <linux/slab.h> 23 #include <linux/mutex.h> 24 #include <linux/rculist.h> 25 #include <asm/acpi.h> 26 #include <asm/e820/api.h> 27 #include <asm/msr.h> 28 #include <asm/pci_x86.h> 29 30 /* Indicate if the ECAM resources have been placed into the resource table */ 31 static bool pci_mmcfg_running_state; 32 static bool pci_mmcfg_arch_init_failed; 33 static DEFINE_MUTEX(pci_mmcfg_lock); 34 #define pci_mmcfg_lock_held() lock_is_held(&(pci_mmcfg_lock).dep_map) 35 36 LIST_HEAD(pci_mmcfg_list); 37 38 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) 39 { 40 if (cfg->res.parent) 41 release_resource(&cfg->res); 42 list_del(&cfg->list); 43 kfree(cfg); 44 } 45 46 static void __init free_all_mmcfg(void) 47 { 48 struct pci_mmcfg_region *cfg, *tmp; 49 50 pci_mmcfg_arch_free(); 51 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) 52 pci_mmconfig_remove(cfg); 53 } 54 55 static void list_add_sorted(struct pci_mmcfg_region *new) 56 { 57 struct pci_mmcfg_region *cfg; 58 59 /* keep list sorted by segment and starting bus number */ 60 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) { 61 if (cfg->segment > new->segment || 62 (cfg->segment == new->segment && 63 cfg->start_bus >= new->start_bus)) { 64 list_add_tail_rcu(&new->list, &cfg->list); 65 return; 66 } 67 } 68 list_add_tail_rcu(&new->list, &pci_mmcfg_list); 69 } 70 71 static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start, 72 int end, u64 addr) 73 { 74 struct pci_mmcfg_region *new; 75 struct resource *res; 76 77 if (addr == 0) 78 return NULL; 79 80 new = kzalloc_obj(*new); 81 if (!new) 82 return NULL; 83 84 new->address = addr; 85 new->segment = segment; 86 new->start_bus = start; 87 new->end_bus = end; 88 89 res = &new->res; 90 res->start = addr + PCI_MMCFG_BUS_OFFSET(start); 91 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1; 92 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 93 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN, 94 "PCI ECAM %04x [bus %02x-%02x]", segment, start, end); 95 res->name = new->name; 96 97 return new; 98 } 99 100 struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start, 101 int end, u64 addr) 102 { 103 struct pci_mmcfg_region *new; 104 105 new = pci_mmconfig_alloc(segment, start, end, addr); 106 if (!new) 107 return NULL; 108 109 mutex_lock(&pci_mmcfg_lock); 110 list_add_sorted(new); 111 mutex_unlock(&pci_mmcfg_lock); 112 113 pr_info("ECAM %pR (base %#lx) for domain %04x [bus %02x-%02x]\n", 114 &new->res, (unsigned long)addr, segment, start, end); 115 116 return new; 117 } 118 119 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus) 120 { 121 struct pci_mmcfg_region *cfg; 122 123 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) 124 if (cfg->segment == segment && 125 cfg->start_bus <= bus && bus <= cfg->end_bus) 126 return cfg; 127 128 return NULL; 129 } 130 131 static const char *__init pci_mmcfg_e7520(void) 132 { 133 u32 win; 134 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); 135 136 win = win & 0xf000; 137 if (win == 0x0000 || win == 0xf000) 138 return NULL; 139 140 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL) 141 return NULL; 142 143 return "Intel Corporation E7520 Memory Controller Hub"; 144 } 145 146 static const char *__init pci_mmcfg_intel_945(void) 147 { 148 u32 pciexbar, mask = 0, len = 0; 149 150 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); 151 152 /* Enable bit */ 153 if (!(pciexbar & 1)) 154 return NULL; 155 156 /* Size bits */ 157 switch ((pciexbar >> 1) & 3) { 158 case 0: 159 mask = 0xf0000000U; 160 len = 0x10000000U; 161 break; 162 case 1: 163 mask = 0xf8000000U; 164 len = 0x08000000U; 165 break; 166 case 2: 167 mask = 0xfc000000U; 168 len = 0x04000000U; 169 break; 170 default: 171 return NULL; 172 } 173 174 /* Errata #2, things break when not aligned on a 256Mb boundary */ 175 /* Can only happen in 64M/128M mode */ 176 177 if ((pciexbar & mask) & 0x0fffffffU) 178 return NULL; 179 180 /* Don't hit the APIC registers and their friends */ 181 if ((pciexbar & mask) >= 0xf0000000U) 182 return NULL; 183 184 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL) 185 return NULL; 186 187 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; 188 } 189 190 static const char *__init pci_mmcfg_amd_fam10h(void) 191 { 192 u32 address; 193 u64 base, msr; 194 int i; 195 unsigned segnbits = 0, busnbits, end_bus; 196 197 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) 198 return NULL; 199 200 address = MSR_FAM10H_MMIO_CONF_BASE; 201 if (rdmsrq_safe(address, &msr)) 202 return NULL; 203 204 /* ECAM is not enabled */ 205 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) 206 return NULL; 207 208 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); 209 210 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & 211 FAM10H_MMIO_CONF_BUSRANGE_MASK; 212 213 /* 214 * only handle bus 0 ? 215 * need to skip it 216 */ 217 if (!busnbits) 218 return NULL; 219 220 if (busnbits > 8) { 221 segnbits = busnbits - 8; 222 busnbits = 8; 223 } 224 225 end_bus = (1 << busnbits) - 1; 226 for (i = 0; i < (1 << segnbits); i++) 227 if (pci_mmconfig_add(i, 0, end_bus, 228 base + (1<<28) * i) == NULL) { 229 free_all_mmcfg(); 230 return NULL; 231 } 232 233 return "AMD Family 10h NB"; 234 } 235 236 static bool __initdata mcp55_checked; 237 static const char *__init pci_mmcfg_nvidia_mcp55(void) 238 { 239 int bus; 240 int mcp55_mmconf_found = 0; 241 242 static const u32 extcfg_regnum __initconst = 0x90; 243 static const u32 extcfg_regsize __initconst = 4; 244 static const u32 extcfg_enable_mask __initconst = 1 << 31; 245 static const u32 extcfg_start_mask __initconst = 0xff << 16; 246 static const int extcfg_start_shift __initconst = 16; 247 static const u32 extcfg_size_mask __initconst = 0x3 << 28; 248 static const int extcfg_size_shift __initconst = 28; 249 static const int extcfg_sizebus[] __initconst = { 250 0x100, 0x80, 0x40, 0x20 251 }; 252 static const u32 extcfg_base_mask[] __initconst = { 253 0x7ff8, 0x7ffc, 0x7ffe, 0x7fff 254 }; 255 static const int extcfg_base_lshift __initconst = 25; 256 257 /* 258 * do check if amd fam10h already took over 259 */ 260 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked) 261 return NULL; 262 263 mcp55_checked = true; 264 for (bus = 0; bus < 256; bus++) { 265 u64 base; 266 u32 l, extcfg; 267 u16 vendor, device; 268 int start, size_index, end; 269 270 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l); 271 vendor = l & 0xffff; 272 device = (l >> 16) & 0xffff; 273 274 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) 275 continue; 276 277 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum, 278 extcfg_regsize, &extcfg); 279 280 if (!(extcfg & extcfg_enable_mask)) 281 continue; 282 283 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift; 284 base = extcfg & extcfg_base_mask[size_index]; 285 /* base could > 4G */ 286 base <<= extcfg_base_lshift; 287 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift; 288 end = start + extcfg_sizebus[size_index] - 1; 289 if (pci_mmconfig_add(0, start, end, base) == NULL) 290 continue; 291 mcp55_mmconf_found++; 292 } 293 294 if (!mcp55_mmconf_found) 295 return NULL; 296 297 return "nVidia MCP55"; 298 } 299 300 struct pci_mmcfg_hostbridge_probe { 301 u32 bus; 302 u32 devfn; 303 u32 vendor; 304 u32 device; 305 const char *(*probe)(void); 306 }; 307 308 static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = { 309 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 310 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, 311 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 312 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, 313 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, 314 0x1200, pci_mmcfg_amd_fam10h }, 315 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, 316 0x1200, pci_mmcfg_amd_fam10h }, 317 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA, 318 0x0369, pci_mmcfg_nvidia_mcp55 }, 319 }; 320 321 static void __init pci_mmcfg_check_end_bus_number(void) 322 { 323 struct pci_mmcfg_region *cfg, *cfgx; 324 325 /* Fixup overlaps */ 326 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 327 if (cfg->end_bus < cfg->start_bus) 328 cfg->end_bus = 255; 329 330 /* Don't access the list head ! */ 331 if (cfg->list.next == &pci_mmcfg_list) 332 break; 333 334 cfgx = list_entry(cfg->list.next, typeof(*cfg), list); 335 if (cfg->end_bus >= cfgx->start_bus) 336 cfg->end_bus = cfgx->start_bus - 1; 337 } 338 } 339 340 static int __init pci_mmcfg_check_hostbridge(void) 341 { 342 u32 l; 343 u32 bus, devfn; 344 u16 vendor, device; 345 int i; 346 const char *name; 347 348 if (!raw_pci_ops) 349 return 0; 350 351 free_all_mmcfg(); 352 353 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) { 354 bus = pci_mmcfg_probes[i].bus; 355 devfn = pci_mmcfg_probes[i].devfn; 356 raw_pci_ops->read(0, bus, devfn, 0, 4, &l); 357 vendor = l & 0xffff; 358 device = (l >> 16) & 0xffff; 359 360 name = NULL; 361 if (pci_mmcfg_probes[i].vendor == vendor && 362 pci_mmcfg_probes[i].device == device) 363 name = pci_mmcfg_probes[i].probe(); 364 365 if (name) 366 pr_info("%s with ECAM support\n", name); 367 } 368 369 /* some end_bus_number is crazy, fix it */ 370 pci_mmcfg_check_end_bus_number(); 371 372 return !list_empty(&pci_mmcfg_list); 373 } 374 375 static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data) 376 { 377 struct resource *mcfg_res = data; 378 struct acpi_resource_address64 address; 379 acpi_status status; 380 381 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { 382 struct acpi_resource_fixed_memory32 *fixmem32 = 383 &res->data.fixed_memory32; 384 if (!fixmem32) 385 return AE_OK; 386 if ((mcfg_res->start >= fixmem32->address) && 387 (mcfg_res->end < (fixmem32->address + 388 fixmem32->address_length))) { 389 mcfg_res->flags = 1; 390 return AE_CTRL_TERMINATE; 391 } 392 } 393 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && 394 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) 395 return AE_OK; 396 397 status = acpi_resource_to_address64(res, &address); 398 if (ACPI_FAILURE(status) || 399 (address.address.address_length <= 0) || 400 (address.resource_type != ACPI_MEMORY_RANGE)) 401 return AE_OK; 402 403 if ((mcfg_res->start >= address.address.minimum) && 404 (mcfg_res->end < (address.address.minimum + address.address.address_length))) { 405 mcfg_res->flags = 1; 406 return AE_CTRL_TERMINATE; 407 } 408 return AE_OK; 409 } 410 411 static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl, 412 void *context, void **rv) 413 { 414 struct resource *mcfg_res = context; 415 416 acpi_walk_resources(handle, METHOD_NAME__CRS, 417 check_mcfg_resource, context); 418 419 if (mcfg_res->flags) 420 return AE_CTRL_TERMINATE; 421 422 return AE_OK; 423 } 424 425 static bool is_acpi_reserved(u64 start, u64 end, enum e820_type not_used) 426 { 427 struct resource mcfg_res; 428 429 mcfg_res.start = start; 430 mcfg_res.end = end - 1; 431 mcfg_res.flags = 0; 432 433 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); 434 435 if (!mcfg_res.flags) 436 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, 437 NULL); 438 439 return mcfg_res.flags; 440 } 441 442 static bool is_efi_mmio(struct resource *res) 443 { 444 #ifdef CONFIG_EFI 445 u64 start = res->start; 446 u64 end = res->start + resource_size(res); 447 efi_memory_desc_t *md; 448 u64 size, mmio_start, mmio_end; 449 450 for_each_efi_memory_desc(md) { 451 if (md->type == EFI_MEMORY_MAPPED_IO) { 452 size = md->num_pages << EFI_PAGE_SHIFT; 453 mmio_start = md->phys_addr; 454 mmio_end = mmio_start + size; 455 456 if (mmio_start <= start && end <= mmio_end) 457 return true; 458 } 459 } 460 #endif 461 462 return false; 463 } 464 465 typedef bool (*check_reserved_t)(u64 start, u64 end, enum e820_type type); 466 467 static bool __ref is_mmconf_reserved(check_reserved_t is_reserved, 468 struct pci_mmcfg_region *cfg, 469 struct device *dev, const char *method) 470 { 471 u64 addr = cfg->res.start; 472 u64 size = resource_size(&cfg->res); 473 u64 old_size = size; 474 int num_buses; 475 476 while (!is_reserved(addr, addr + size, E820_TYPE_RESERVED)) { 477 size >>= 1; 478 if (size < (16UL<<20)) 479 break; 480 } 481 482 if (size < (16UL<<20) && size != old_size) 483 return false; 484 485 if (dev) 486 dev_info(dev, "ECAM %pR reserved as %s\n", 487 &cfg->res, method); 488 else 489 pr_info("ECAM %pR reserved as %s\n", &cfg->res, method); 490 491 if (old_size != size) { 492 /* update end_bus */ 493 cfg->end_bus = cfg->start_bus + ((size>>20) - 1); 494 num_buses = cfg->end_bus - cfg->start_bus + 1; 495 cfg->res.end = cfg->res.start + 496 PCI_MMCFG_BUS_OFFSET(num_buses) - 1; 497 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN, 498 "PCI ECAM %04x [bus %02x-%02x]", 499 cfg->segment, cfg->start_bus, cfg->end_bus); 500 501 if (dev) 502 dev_info(dev, "ECAM %pR (base %#lx) (size reduced!)\n", 503 &cfg->res, (unsigned long) cfg->address); 504 else 505 pr_info("ECAM %pR (base %#lx) for %04x [bus%02x-%02x] (size reduced!)\n", 506 &cfg->res, (unsigned long) cfg->address, 507 cfg->segment, cfg->start_bus, cfg->end_bus); 508 } 509 510 return true; 511 } 512 513 static bool __ref pci_mmcfg_reserved(struct device *dev, 514 struct pci_mmcfg_region *cfg, int early) 515 { 516 struct resource *conflict; 517 518 if (early) { 519 520 /* 521 * Don't try to do this check unless configuration type 1 522 * is available. How about type 2? 523 */ 524 525 /* 526 * 946f2ee5c731 ("Check that MCFG points to an e820 527 * reserved area") added this E820 check in 2006 to work 528 * around BIOS defects. 529 * 530 * Per PCI Firmware r3.3, sec 4.1.2, ECAM space must be 531 * reserved by a PNP0C02 resource, but it need not be 532 * mentioned in E820. Before the ACPI interpreter is 533 * available, we can't check for PNP0C02 resources, so 534 * there's no reliable way to verify the region in this 535 * early check. Keep it only for the old machines that 536 * motivated 946f2ee5c731. 537 */ 538 if (dmi_get_bios_year() < 2016 && raw_pci_ops) 539 return is_mmconf_reserved(e820__mapped_all, cfg, dev, 540 "E820 entry"); 541 542 return true; 543 } 544 545 if (!acpi_disabled) { 546 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 547 "ACPI motherboard resource")) 548 return true; 549 550 if (dev) 551 dev_info(dev, FW_INFO "ECAM %pR not reserved in ACPI motherboard resources\n", 552 &cfg->res); 553 else 554 pr_info(FW_INFO "ECAM %pR not reserved in ACPI motherboard resources\n", 555 &cfg->res); 556 557 if (is_efi_mmio(&cfg->res)) { 558 pr_info("ECAM %pR is EfiMemoryMappedIO; assuming valid\n", 559 &cfg->res); 560 conflict = insert_resource_conflict(&iomem_resource, 561 &cfg->res); 562 if (conflict) 563 pr_warn("ECAM %pR conflicts with %s %pR\n", 564 &cfg->res, conflict->name, conflict); 565 else 566 pr_info("ECAM %pR reserved to work around lack of ACPI motherboard _CRS\n", 567 &cfg->res); 568 return true; 569 } 570 } 571 572 /* 573 * e820__mapped_all() is marked as __init. 574 * All entries from ACPI MCFG table have been checked at boot time. 575 * For MCFG information constructed from hotpluggable host bridge's 576 * _CBA method, just assume it's reserved. 577 */ 578 return pci_mmcfg_running_state; 579 } 580 581 static void __init pci_mmcfg_reject_broken(int early) 582 { 583 struct pci_mmcfg_region *cfg; 584 585 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 586 if (!pci_mmcfg_reserved(NULL, cfg, early)) { 587 pr_info("not using ECAM (%pR not reserved)\n", 588 &cfg->res); 589 free_all_mmcfg(); 590 return; 591 } 592 } 593 } 594 595 static bool __init acpi_mcfg_valid_entry(struct acpi_table_mcfg *mcfg, 596 struct acpi_mcfg_allocation *cfg) 597 { 598 if (cfg->address < 0xFFFFFFFF) 599 return true; 600 601 if (!strncmp(mcfg->header.oem_id, "SGI", 3)) 602 return true; 603 604 if ((mcfg->header.revision >= 1) && (dmi_get_bios_year() >= 2010)) 605 return true; 606 607 pr_err("ECAM at %#llx for %04x [bus %02x-%02x] is above 4GB, ignored\n", 608 cfg->address, cfg->pci_segment, cfg->start_bus_number, 609 cfg->end_bus_number); 610 return false; 611 } 612 613 static int __init pci_parse_mcfg(struct acpi_table_header *header) 614 { 615 struct acpi_table_mcfg *mcfg; 616 struct acpi_mcfg_allocation *cfg_table, *cfg; 617 unsigned long i; 618 int entries; 619 620 if (!header) 621 return -EINVAL; 622 623 mcfg = (struct acpi_table_mcfg *)header; 624 625 /* how many config structures do we have */ 626 free_all_mmcfg(); 627 entries = 0; 628 i = header->length - sizeof(struct acpi_table_mcfg); 629 while (i >= sizeof(struct acpi_mcfg_allocation)) { 630 entries++; 631 i -= sizeof(struct acpi_mcfg_allocation); 632 } 633 if (entries == 0) { 634 pr_err("MCFG has no entries\n"); 635 return -ENODEV; 636 } 637 638 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1]; 639 for (i = 0; i < entries; i++) { 640 cfg = &cfg_table[i]; 641 if (!acpi_mcfg_valid_entry(mcfg, cfg)) { 642 free_all_mmcfg(); 643 return -ENODEV; 644 } 645 646 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, 647 cfg->end_bus_number, cfg->address) == NULL) { 648 pr_warn("no memory for MCFG entries\n"); 649 free_all_mmcfg(); 650 return -ENOMEM; 651 } 652 } 653 654 return 0; 655 } 656 657 #ifdef CONFIG_ACPI_APEI 658 extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size, 659 void *data), void *data); 660 661 static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size, 662 void *data), void *data) 663 { 664 struct pci_mmcfg_region *cfg; 665 int rc; 666 667 if (list_empty(&pci_mmcfg_list)) 668 return 0; 669 670 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 671 rc = func(cfg->res.start, resource_size(&cfg->res), data); 672 if (rc) 673 return rc; 674 } 675 676 return 0; 677 } 678 #define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region) 679 #else 680 #define set_apei_filter() 681 #endif 682 683 static void __init __pci_mmcfg_init(int early) 684 { 685 pr_debug("%s(%s)\n", __func__, early ? "early" : "late"); 686 687 pci_mmcfg_reject_broken(early); 688 if (list_empty(&pci_mmcfg_list)) 689 return; 690 691 if (pcibios_last_bus < 0) { 692 const struct pci_mmcfg_region *cfg; 693 694 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 695 if (cfg->segment) 696 break; 697 pcibios_last_bus = cfg->end_bus; 698 } 699 } 700 701 if (pci_mmcfg_arch_init()) 702 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 703 else { 704 free_all_mmcfg(); 705 pci_mmcfg_arch_init_failed = true; 706 } 707 } 708 709 static int __initdata known_bridge; 710 711 void __init pci_mmcfg_early_init(void) 712 { 713 pr_debug("%s() pci_probe %#x\n", __func__, pci_probe); 714 715 if (pci_probe & PCI_PROBE_MMCONF) { 716 if (pci_mmcfg_check_hostbridge()) 717 known_bridge = 1; 718 else 719 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); 720 __pci_mmcfg_init(1); 721 722 set_apei_filter(); 723 } 724 } 725 726 void __init pci_mmcfg_late_init(void) 727 { 728 pr_debug("%s() pci_probe %#x\n", __func__, pci_probe); 729 730 /* ECAM disabled */ 731 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 732 return; 733 734 if (known_bridge) 735 return; 736 737 /* ECAM hasn't been enabled yet, try again */ 738 if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) { 739 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); 740 __pci_mmcfg_init(0); 741 } 742 } 743 744 static int __init pci_mmcfg_late_insert_resources(void) 745 { 746 struct pci_mmcfg_region *cfg; 747 748 pci_mmcfg_running_state = true; 749 750 pr_debug("%s() pci_probe %#x\n", __func__, pci_probe); 751 752 /* If we are not using ECAM, don't insert the resources. */ 753 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 754 return 1; 755 756 /* 757 * Attempt to insert the mmcfg resources but not with the busy flag 758 * marked so it won't cause request errors when __request_region is 759 * called. 760 */ 761 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 762 if (!cfg->res.parent) { 763 pr_debug("%s() insert %pR\n", __func__, &cfg->res); 764 insert_resource(&iomem_resource, &cfg->res); 765 } 766 } 767 768 return 0; 769 } 770 771 /* 772 * Perform ECAM resource insertion after PCI initialization to allow for 773 * misprogrammed MCFG tables that state larger sizes but actually conflict 774 * with other system resources. 775 */ 776 late_initcall(pci_mmcfg_late_insert_resources); 777 778 /* Add ECAM information for host bridges */ 779 int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, 780 phys_addr_t addr) 781 { 782 int rc; 783 struct resource *tmp = NULL; 784 struct pci_mmcfg_region *cfg; 785 786 dev_dbg(dev, "%s(%04x [bus %02x-%02x])\n", __func__, seg, start, end); 787 788 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed) 789 return -ENODEV; 790 791 if (start > end) 792 return -EINVAL; 793 794 mutex_lock(&pci_mmcfg_lock); 795 cfg = pci_mmconfig_lookup(seg, start); 796 if (cfg) { 797 if (cfg->end_bus < end) 798 dev_info(dev, FW_INFO "ECAM %pR for domain %04x [bus %02x-%02x] only partially covers this bridge\n", 799 &cfg->res, cfg->segment, cfg->start_bus, 800 cfg->end_bus); 801 mutex_unlock(&pci_mmcfg_lock); 802 return -EEXIST; 803 } 804 805 /* 806 * Don't move earlier; we must return -EEXIST, not -EINVAL, if 807 * pci_mmconfig_lookup() finds something 808 */ 809 if (!addr) { 810 mutex_unlock(&pci_mmcfg_lock); 811 return -EINVAL; 812 } 813 814 rc = -EBUSY; 815 cfg = pci_mmconfig_alloc(seg, start, end, addr); 816 if (cfg == NULL) { 817 dev_warn(dev, "fail to add ECAM (out of memory)\n"); 818 rc = -ENOMEM; 819 } else if (!pci_mmcfg_reserved(dev, cfg, 0)) { 820 dev_warn(dev, FW_BUG "ECAM %pR isn't reserved\n", 821 &cfg->res); 822 } else { 823 /* Insert resource if it's not in boot stage */ 824 if (pci_mmcfg_running_state) 825 tmp = insert_resource_conflict(&iomem_resource, 826 &cfg->res); 827 828 if (tmp) { 829 dev_warn(dev, "ECAM %pR conflicts with %s %pR\n", 830 &cfg->res, tmp->name, tmp); 831 } else if (pci_mmcfg_arch_map(cfg)) { 832 dev_warn(dev, "fail to map ECAM %pR\n", &cfg->res); 833 } else { 834 list_add_sorted(cfg); 835 dev_info(dev, "ECAM %pR (base %#lx)\n", 836 &cfg->res, (unsigned long)addr); 837 cfg = NULL; 838 rc = 0; 839 } 840 } 841 842 if (cfg) { 843 if (cfg->res.parent) 844 release_resource(&cfg->res); 845 kfree(cfg); 846 } 847 848 mutex_unlock(&pci_mmcfg_lock); 849 850 return rc; 851 } 852 853 /* Delete ECAM information for host bridges */ 854 int pci_mmconfig_delete(u16 seg, u8 start, u8 end) 855 { 856 struct pci_mmcfg_region *cfg; 857 858 mutex_lock(&pci_mmcfg_lock); 859 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) 860 if (cfg->segment == seg && cfg->start_bus == start && 861 cfg->end_bus == end) { 862 list_del_rcu(&cfg->list); 863 synchronize_rcu(); 864 pci_mmcfg_arch_unmap(cfg); 865 if (cfg->res.parent) 866 release_resource(&cfg->res); 867 mutex_unlock(&pci_mmcfg_lock); 868 kfree(cfg); 869 return 0; 870 } 871 mutex_unlock(&pci_mmcfg_lock); 872 873 return -ENOENT; 874 } 875