1 /* 2 * Low-Level PCI Support for PC -- Routing of Interrupts 3 * 4 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 5 */ 6 7 #include <linux/types.h> 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/init.h> 11 #include <linux/slab.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmi.h> 14 #include <linux/io.h> 15 #include <linux/smp.h> 16 #include <asm/io_apic.h> 17 #include <linux/irq.h> 18 #include <linux/acpi.h> 19 20 #include "pci.h" 21 22 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 23 #define PIRQ_VERSION 0x0100 24 25 static int broken_hp_bios_irq9; 26 static int acer_tm360_irqrouting; 27 28 static struct irq_routing_table *pirq_table; 29 30 static int pirq_enable_irq(struct pci_dev *dev); 31 32 /* 33 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 34 * Avoid using: 13, 14 and 15 (FP error and IDE). 35 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 36 */ 37 unsigned int pcibios_irq_mask = 0xfff8; 38 39 static int pirq_penalty[16] = { 40 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 41 0, 0, 0, 0, 1000, 100000, 100000, 100000 42 }; 43 44 struct irq_router { 45 char *name; 46 u16 vendor, device; 47 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 48 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, 49 int new); 50 }; 51 52 struct irq_router_handler { 53 u16 vendor; 54 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 55 }; 56 57 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL; 58 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL; 59 60 /* 61 * Check passed address for the PCI IRQ Routing Table signature 62 * and perform checksum verification. 63 */ 64 65 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr) 66 { 67 struct irq_routing_table *rt; 68 int i; 69 u8 sum; 70 71 rt = (struct irq_routing_table *) addr; 72 if (rt->signature != PIRQ_SIGNATURE || 73 rt->version != PIRQ_VERSION || 74 rt->size % 16 || 75 rt->size < sizeof(struct irq_routing_table)) 76 return NULL; 77 sum = 0; 78 for (i = 0; i < rt->size; i++) 79 sum += addr[i]; 80 if (!sum) { 81 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", 82 rt); 83 return rt; 84 } 85 return NULL; 86 } 87 88 89 90 /* 91 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 92 */ 93 94 static struct irq_routing_table * __init pirq_find_routing_table(void) 95 { 96 u8 *addr; 97 struct irq_routing_table *rt; 98 99 if (pirq_table_addr) { 100 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 101 if (rt) 102 return rt; 103 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 104 } 105 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 106 rt = pirq_check_routing_table(addr); 107 if (rt) 108 return rt; 109 } 110 return NULL; 111 } 112 113 /* 114 * If we have a IRQ routing table, use it to search for peer host 115 * bridges. It's a gross hack, but since there are no other known 116 * ways how to get a list of buses, we have to go this way. 117 */ 118 119 static void __init pirq_peer_trick(void) 120 { 121 struct irq_routing_table *rt = pirq_table; 122 u8 busmap[256]; 123 int i; 124 struct irq_info *e; 125 126 memset(busmap, 0, sizeof(busmap)); 127 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 128 e = &rt->slots[i]; 129 #ifdef DEBUG 130 { 131 int j; 132 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 133 for (j = 0; j < 4; j++) 134 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 135 DBG("\n"); 136 } 137 #endif 138 busmap[e->bus] = 1; 139 } 140 for (i = 1; i < 256; i++) { 141 int node; 142 if (!busmap[i] || pci_find_bus(0, i)) 143 continue; 144 node = get_mp_bus_to_node(i); 145 if (pci_scan_bus_on_node(i, &pci_root_ops, node)) 146 printk(KERN_INFO "PCI: Discovered primary peer " 147 "bus %02x [IRQ]\n", i); 148 } 149 pcibios_last_bus = -1; 150 } 151 152 /* 153 * Code for querying and setting of IRQ routes on various interrupt routers. 154 */ 155 156 void eisa_set_level_irq(unsigned int irq) 157 { 158 unsigned char mask = 1 << (irq & 7); 159 unsigned int port = 0x4d0 + (irq >> 3); 160 unsigned char val; 161 static u16 eisa_irq_mask; 162 163 if (irq >= 16 || (1 << irq) & eisa_irq_mask) 164 return; 165 166 eisa_irq_mask |= (1 << irq); 167 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 168 val = inb(port); 169 if (!(val & mask)) { 170 DBG(KERN_DEBUG " -> edge"); 171 outb(val | mask, port); 172 } 173 } 174 175 /* 176 * Common IRQ routing practice: nibbles in config space, 177 * offset by some magic constant. 178 */ 179 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 180 { 181 u8 x; 182 unsigned reg = offset + (nr >> 1); 183 184 pci_read_config_byte(router, reg, &x); 185 return (nr & 1) ? (x >> 4) : (x & 0xf); 186 } 187 188 static void write_config_nybble(struct pci_dev *router, unsigned offset, 189 unsigned nr, unsigned int val) 190 { 191 u8 x; 192 unsigned reg = offset + (nr >> 1); 193 194 pci_read_config_byte(router, reg, &x); 195 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 196 pci_write_config_byte(router, reg, x); 197 } 198 199 /* 200 * ALI pirq entries are damn ugly, and completely undocumented. 201 * This has been figured out from pirq tables, and it's not a pretty 202 * picture. 203 */ 204 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 205 { 206 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 207 208 WARN_ON_ONCE(pirq > 16); 209 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 210 } 211 212 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 213 { 214 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 215 unsigned int val = irqmap[irq]; 216 217 WARN_ON_ONCE(pirq > 16); 218 if (val) { 219 write_config_nybble(router, 0x48, pirq-1, val); 220 return 1; 221 } 222 return 0; 223 } 224 225 /* 226 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 227 * just a pointer to the config space. 228 */ 229 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 230 { 231 u8 x; 232 233 pci_read_config_byte(router, pirq, &x); 234 return (x < 16) ? x : 0; 235 } 236 237 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 238 { 239 pci_write_config_byte(router, pirq, irq); 240 return 1; 241 } 242 243 /* 244 * The VIA pirq rules are nibble-based, like ALI, 245 * but without the ugly irq number munging. 246 * However, PIRQD is in the upper instead of lower 4 bits. 247 */ 248 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 249 { 250 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 251 } 252 253 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 254 { 255 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 256 return 1; 257 } 258 259 /* 260 * The VIA pirq rules are nibble-based, like ALI, 261 * but without the ugly irq number munging. 262 * However, for 82C586, nibble map is different . 263 */ 264 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 265 { 266 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 267 268 WARN_ON_ONCE(pirq > 5); 269 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 270 } 271 272 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 273 { 274 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 275 276 WARN_ON_ONCE(pirq > 5); 277 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 278 return 1; 279 } 280 281 /* 282 * ITE 8330G pirq rules are nibble-based 283 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 284 * 2+3 are both mapped to irq 9 on my system 285 */ 286 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 287 { 288 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 289 290 WARN_ON_ONCE(pirq > 4); 291 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); 292 } 293 294 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 295 { 296 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 297 298 WARN_ON_ONCE(pirq > 4); 299 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 300 return 1; 301 } 302 303 /* 304 * OPTI: high four bits are nibble pointer.. 305 * I wonder what the low bits do? 306 */ 307 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 308 { 309 return read_config_nybble(router, 0xb8, pirq >> 4); 310 } 311 312 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 313 { 314 write_config_nybble(router, 0xb8, pirq >> 4, irq); 315 return 1; 316 } 317 318 /* 319 * Cyrix: nibble offset 0x5C 320 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 321 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 322 */ 323 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 324 { 325 return read_config_nybble(router, 0x5C, (pirq-1)^1); 326 } 327 328 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 329 { 330 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 331 return 1; 332 } 333 334 /* 335 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 336 * We have to deal with the following issues here: 337 * - vendors have different ideas about the meaning of link values 338 * - some onboard devices (integrated in the chipset) have special 339 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 340 * - different revision of the router have a different layout for 341 * the routing registers, particularly for the onchip devices 342 * 343 * For all routing registers the common thing is we have one byte 344 * per routeable link which is defined as: 345 * bit 7 IRQ mapping enabled (0) or disabled (1) 346 * bits [6:4] reserved (sometimes used for onchip devices) 347 * bits [3:0] IRQ to map to 348 * allowed: 3-7, 9-12, 14-15 349 * reserved: 0, 1, 2, 8, 13 350 * 351 * The config-space registers located at 0x41/0x42/0x43/0x44 are 352 * always used to route the normal PCI INT A/B/C/D respectively. 353 * Apparently there are systems implementing PCI routing table using 354 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 355 * We try our best to handle both link mappings. 356 * 357 * Currently (2003-05-21) it appears most SiS chipsets follow the 358 * definition of routing registers from the SiS-5595 southbridge. 359 * According to the SiS 5595 datasheets the revision id's of the 360 * router (ISA-bridge) should be 0x01 or 0xb0. 361 * 362 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 363 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 364 * They seem to work with the current routing code. However there is 365 * some concern because of the two USB-OHCI HCs (original SiS 5595 366 * had only one). YMMV. 367 * 368 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 369 * 370 * 0x61: IDEIRQ: 371 * bits [6:5] must be written 01 372 * bit 4 channel-select primary (0), secondary (1) 373 * 374 * 0x62: USBIRQ: 375 * bit 6 OHCI function disabled (0), enabled (1) 376 * 377 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 378 * 379 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 380 * 381 * We support USBIRQ (in addition to INTA-INTD) and keep the 382 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 383 * 384 * Currently the only reported exception is the new SiS 65x chipset 385 * which includes the SiS 69x southbridge. Here we have the 85C503 386 * router revision 0x04 and there are changes in the register layout 387 * mostly related to the different USB HCs with USB 2.0 support. 388 * 389 * Onchip routing for router rev-id 0x04 (try-and-error observation) 390 * 391 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 392 * bit 6-4 are probably unused, not like 5595 393 */ 394 395 #define PIRQ_SIS_IRQ_MASK 0x0f 396 #define PIRQ_SIS_IRQ_DISABLE 0x80 397 #define PIRQ_SIS_USB_ENABLE 0x40 398 399 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 400 { 401 u8 x; 402 int reg; 403 404 reg = pirq; 405 if (reg >= 0x01 && reg <= 0x04) 406 reg += 0x40; 407 pci_read_config_byte(router, reg, &x); 408 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); 409 } 410 411 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 412 { 413 u8 x; 414 int reg; 415 416 reg = pirq; 417 if (reg >= 0x01 && reg <= 0x04) 418 reg += 0x40; 419 pci_read_config_byte(router, reg, &x); 420 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); 421 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; 422 pci_write_config_byte(router, reg, x); 423 return 1; 424 } 425 426 427 /* 428 * VLSI: nibble offset 0x74 - educated guess due to routing table and 429 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 430 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 431 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 432 * for the busbridge to the docking station. 433 */ 434 435 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 436 { 437 WARN_ON_ONCE(pirq >= 9); 438 if (pirq > 8) { 439 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 440 return 0; 441 } 442 return read_config_nybble(router, 0x74, pirq-1); 443 } 444 445 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 446 { 447 WARN_ON_ONCE(pirq >= 9); 448 if (pirq > 8) { 449 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 450 return 0; 451 } 452 write_config_nybble(router, 0x74, pirq-1, irq); 453 return 1; 454 } 455 456 /* 457 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 458 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 459 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 460 * register is a straight binary coding of desired PIC IRQ (low nibble). 461 * 462 * The 'link' value in the PIRQ table is already in the correct format 463 * for the Index register. There are some special index values: 464 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 465 * and 0x03 for SMBus. 466 */ 467 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 468 { 469 outb(pirq, 0xc00); 470 return inb(0xc01) & 0xf; 471 } 472 473 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, 474 int pirq, int irq) 475 { 476 outb(pirq, 0xc00); 477 outb(irq, 0xc01); 478 return 1; 479 } 480 481 /* Support for AMD756 PCI IRQ Routing 482 * Jhon H. Caicedo <jhcaiced@osso.org.co> 483 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 484 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 485 * The AMD756 pirq rules are nibble-based 486 * offset 0x56 0-3 PIRQA 4-7 PIRQB 487 * offset 0x57 0-3 PIRQC 4-7 PIRQD 488 */ 489 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 490 { 491 u8 irq; 492 irq = 0; 493 if (pirq <= 4) 494 irq = read_config_nybble(router, 0x56, pirq - 1); 495 dev_info(&dev->dev, 496 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n", 497 dev->vendor, dev->device, pirq, irq); 498 return irq; 499 } 500 501 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 502 { 503 dev_info(&dev->dev, 504 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n", 505 dev->vendor, dev->device, pirq, irq); 506 if (pirq <= 4) 507 write_config_nybble(router, 0x56, pirq - 1, irq); 508 return 1; 509 } 510 511 /* 512 * PicoPower PT86C523 513 */ 514 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 515 { 516 outb(0x10 + ((pirq - 1) >> 1), 0x24); 517 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 518 } 519 520 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 521 int irq) 522 { 523 unsigned int x; 524 outb(0x10 + ((pirq - 1) >> 1), 0x24); 525 x = inb(0x26); 526 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 527 outb(x, 0x26); 528 return 1; 529 } 530 531 #ifdef CONFIG_PCI_BIOS 532 533 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 534 { 535 struct pci_dev *bridge; 536 int pin = pci_get_interrupt_pin(dev, &bridge); 537 return pcibios_set_irq_routing(bridge, pin, irq); 538 } 539 540 #endif 541 542 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 543 { 544 static struct pci_device_id __initdata pirq_440gx[] = { 545 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 546 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 547 { }, 548 }; 549 550 /* 440GX has a proprietary PIRQ router -- don't use it */ 551 if (pci_dev_present(pirq_440gx)) 552 return 0; 553 554 switch (device) { 555 case PCI_DEVICE_ID_INTEL_82371FB_0: 556 case PCI_DEVICE_ID_INTEL_82371SB_0: 557 case PCI_DEVICE_ID_INTEL_82371AB_0: 558 case PCI_DEVICE_ID_INTEL_82371MX: 559 case PCI_DEVICE_ID_INTEL_82443MX_0: 560 case PCI_DEVICE_ID_INTEL_82801AA_0: 561 case PCI_DEVICE_ID_INTEL_82801AB_0: 562 case PCI_DEVICE_ID_INTEL_82801BA_0: 563 case PCI_DEVICE_ID_INTEL_82801BA_10: 564 case PCI_DEVICE_ID_INTEL_82801CA_0: 565 case PCI_DEVICE_ID_INTEL_82801CA_12: 566 case PCI_DEVICE_ID_INTEL_82801DB_0: 567 case PCI_DEVICE_ID_INTEL_82801E_0: 568 case PCI_DEVICE_ID_INTEL_82801EB_0: 569 case PCI_DEVICE_ID_INTEL_ESB_1: 570 case PCI_DEVICE_ID_INTEL_ICH6_0: 571 case PCI_DEVICE_ID_INTEL_ICH6_1: 572 case PCI_DEVICE_ID_INTEL_ICH7_0: 573 case PCI_DEVICE_ID_INTEL_ICH7_1: 574 case PCI_DEVICE_ID_INTEL_ICH7_30: 575 case PCI_DEVICE_ID_INTEL_ICH7_31: 576 case PCI_DEVICE_ID_INTEL_ESB2_0: 577 case PCI_DEVICE_ID_INTEL_ICH8_0: 578 case PCI_DEVICE_ID_INTEL_ICH8_1: 579 case PCI_DEVICE_ID_INTEL_ICH8_2: 580 case PCI_DEVICE_ID_INTEL_ICH8_3: 581 case PCI_DEVICE_ID_INTEL_ICH8_4: 582 case PCI_DEVICE_ID_INTEL_ICH9_0: 583 case PCI_DEVICE_ID_INTEL_ICH9_1: 584 case PCI_DEVICE_ID_INTEL_ICH9_2: 585 case PCI_DEVICE_ID_INTEL_ICH9_3: 586 case PCI_DEVICE_ID_INTEL_ICH9_4: 587 case PCI_DEVICE_ID_INTEL_ICH9_5: 588 case PCI_DEVICE_ID_INTEL_TOLAPAI_0: 589 case PCI_DEVICE_ID_INTEL_ICH10_0: 590 case PCI_DEVICE_ID_INTEL_ICH10_1: 591 case PCI_DEVICE_ID_INTEL_ICH10_2: 592 case PCI_DEVICE_ID_INTEL_ICH10_3: 593 r->name = "PIIX/ICH"; 594 r->get = pirq_piix_get; 595 r->set = pirq_piix_set; 596 return 1; 597 } 598 599 if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) && 600 (device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) { 601 r->name = "PIIX/ICH"; 602 r->get = pirq_piix_get; 603 r->set = pirq_piix_set; 604 return 1; 605 } 606 607 return 0; 608 } 609 610 static __init int via_router_probe(struct irq_router *r, 611 struct pci_dev *router, u16 device) 612 { 613 /* FIXME: We should move some of the quirk fixup stuff here */ 614 615 /* 616 * workarounds for some buggy BIOSes 617 */ 618 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 619 switch (router->device) { 620 case PCI_DEVICE_ID_VIA_82C686: 621 /* 622 * Asus k7m bios wrongly reports 82C686A 623 * as 586-compatible 624 */ 625 device = PCI_DEVICE_ID_VIA_82C686; 626 break; 627 case PCI_DEVICE_ID_VIA_8235: 628 /** 629 * Asus a7v-x bios wrongly reports 8235 630 * as 586-compatible 631 */ 632 device = PCI_DEVICE_ID_VIA_8235; 633 break; 634 case PCI_DEVICE_ID_VIA_8237: 635 /** 636 * Asus a7v600 bios wrongly reports 8237 637 * as 586-compatible 638 */ 639 device = PCI_DEVICE_ID_VIA_8237; 640 break; 641 } 642 } 643 644 switch (device) { 645 case PCI_DEVICE_ID_VIA_82C586_0: 646 r->name = "VIA"; 647 r->get = pirq_via586_get; 648 r->set = pirq_via586_set; 649 return 1; 650 case PCI_DEVICE_ID_VIA_82C596: 651 case PCI_DEVICE_ID_VIA_82C686: 652 case PCI_DEVICE_ID_VIA_8231: 653 case PCI_DEVICE_ID_VIA_8233A: 654 case PCI_DEVICE_ID_VIA_8235: 655 case PCI_DEVICE_ID_VIA_8237: 656 /* FIXME: add new ones for 8233/5 */ 657 r->name = "VIA"; 658 r->get = pirq_via_get; 659 r->set = pirq_via_set; 660 return 1; 661 } 662 return 0; 663 } 664 665 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 666 { 667 switch (device) { 668 case PCI_DEVICE_ID_VLSI_82C534: 669 r->name = "VLSI 82C534"; 670 r->get = pirq_vlsi_get; 671 r->set = pirq_vlsi_set; 672 return 1; 673 } 674 return 0; 675 } 676 677 678 static __init int serverworks_router_probe(struct irq_router *r, 679 struct pci_dev *router, u16 device) 680 { 681 switch (device) { 682 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 683 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 684 r->name = "ServerWorks"; 685 r->get = pirq_serverworks_get; 686 r->set = pirq_serverworks_set; 687 return 1; 688 } 689 return 0; 690 } 691 692 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 693 { 694 if (device != PCI_DEVICE_ID_SI_503) 695 return 0; 696 697 r->name = "SIS"; 698 r->get = pirq_sis_get; 699 r->set = pirq_sis_set; 700 return 1; 701 } 702 703 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 704 { 705 switch (device) { 706 case PCI_DEVICE_ID_CYRIX_5520: 707 r->name = "NatSemi"; 708 r->get = pirq_cyrix_get; 709 r->set = pirq_cyrix_set; 710 return 1; 711 } 712 return 0; 713 } 714 715 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 716 { 717 switch (device) { 718 case PCI_DEVICE_ID_OPTI_82C700: 719 r->name = "OPTI"; 720 r->get = pirq_opti_get; 721 r->set = pirq_opti_set; 722 return 1; 723 } 724 return 0; 725 } 726 727 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 728 { 729 switch (device) { 730 case PCI_DEVICE_ID_ITE_IT8330G_0: 731 r->name = "ITE"; 732 r->get = pirq_ite_get; 733 r->set = pirq_ite_set; 734 return 1; 735 } 736 return 0; 737 } 738 739 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 740 { 741 switch (device) { 742 case PCI_DEVICE_ID_AL_M1533: 743 case PCI_DEVICE_ID_AL_M1563: 744 r->name = "ALI"; 745 r->get = pirq_ali_get; 746 r->set = pirq_ali_set; 747 return 1; 748 } 749 return 0; 750 } 751 752 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 753 { 754 switch (device) { 755 case PCI_DEVICE_ID_AMD_VIPER_740B: 756 r->name = "AMD756"; 757 break; 758 case PCI_DEVICE_ID_AMD_VIPER_7413: 759 r->name = "AMD766"; 760 break; 761 case PCI_DEVICE_ID_AMD_VIPER_7443: 762 r->name = "AMD768"; 763 break; 764 default: 765 return 0; 766 } 767 r->get = pirq_amd756_get; 768 r->set = pirq_amd756_set; 769 return 1; 770 } 771 772 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 773 { 774 switch (device) { 775 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 776 r->name = "PicoPower PT86C523"; 777 r->get = pirq_pico_get; 778 r->set = pirq_pico_set; 779 return 1; 780 781 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 782 r->name = "PicoPower PT86C523 rev. BB+"; 783 r->get = pirq_pico_get; 784 r->set = pirq_pico_set; 785 return 1; 786 } 787 return 0; 788 } 789 790 static __initdata struct irq_router_handler pirq_routers[] = { 791 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 792 { PCI_VENDOR_ID_AL, ali_router_probe }, 793 { PCI_VENDOR_ID_ITE, ite_router_probe }, 794 { PCI_VENDOR_ID_VIA, via_router_probe }, 795 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 796 { PCI_VENDOR_ID_SI, sis_router_probe }, 797 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 798 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 799 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 800 { PCI_VENDOR_ID_AMD, amd_router_probe }, 801 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 802 /* Someone with docs needs to add the ATI Radeon IGP */ 803 { 0, NULL } 804 }; 805 static struct irq_router pirq_router; 806 static struct pci_dev *pirq_router_dev; 807 808 809 /* 810 * FIXME: should we have an option to say "generic for 811 * chipset" ? 812 */ 813 814 static void __init pirq_find_router(struct irq_router *r) 815 { 816 struct irq_routing_table *rt = pirq_table; 817 struct irq_router_handler *h; 818 819 #ifdef CONFIG_PCI_BIOS 820 if (!rt->signature) { 821 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 822 r->set = pirq_bios_set; 823 r->name = "BIOS"; 824 return; 825 } 826 #endif 827 828 /* Default unless a driver reloads it */ 829 r->name = "default"; 830 r->get = NULL; 831 r->set = NULL; 832 833 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n", 834 rt->rtr_vendor, rt->rtr_device); 835 836 pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn); 837 if (!pirq_router_dev) { 838 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 839 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 840 return; 841 } 842 843 for (h = pirq_routers; h->vendor; h++) { 844 /* First look for a router match */ 845 if (rt->rtr_vendor == h->vendor && 846 h->probe(r, pirq_router_dev, rt->rtr_device)) 847 break; 848 /* Fall back to a device match */ 849 if (pirq_router_dev->vendor == h->vendor && 850 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 851 break; 852 } 853 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n", 854 pirq_router.name, 855 pirq_router_dev->vendor, pirq_router_dev->device); 856 857 /* The device remains referenced for the kernel lifetime */ 858 } 859 860 static struct irq_info *pirq_get_info(struct pci_dev *dev) 861 { 862 struct irq_routing_table *rt = pirq_table; 863 int entries = (rt->size - sizeof(struct irq_routing_table)) / 864 sizeof(struct irq_info); 865 struct irq_info *info; 866 867 for (info = rt->slots; entries--; info++) 868 if (info->bus == dev->bus->number && 869 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 870 return info; 871 return NULL; 872 } 873 874 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 875 { 876 u8 pin; 877 struct irq_info *info; 878 int i, pirq, newirq; 879 int irq = 0; 880 u32 mask; 881 struct irq_router *r = &pirq_router; 882 struct pci_dev *dev2 = NULL; 883 char *msg = NULL; 884 885 /* Find IRQ pin */ 886 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 887 if (!pin) { 888 dev_dbg(&dev->dev, "no interrupt pin\n"); 889 return 0; 890 } 891 pin = pin - 1; 892 893 /* Find IRQ routing entry */ 894 895 if (!pirq_table) 896 return 0; 897 898 info = pirq_get_info(dev); 899 if (!info) { 900 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n", 901 'A' + pin); 902 return 0; 903 } 904 pirq = info->irq[pin].link; 905 mask = info->irq[pin].bitmap; 906 if (!pirq) { 907 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin); 908 return 0; 909 } 910 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x", 911 'A' + pin, pirq, mask, pirq_table->exclusive_irqs); 912 mask &= pcibios_irq_mask; 913 914 /* Work around broken HP Pavilion Notebooks which assign USB to 915 IRQ 9 even though it is actually wired to IRQ 11 */ 916 917 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 918 dev->irq = 11; 919 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 920 r->set(pirq_router_dev, dev, pirq, 11); 921 } 922 923 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 924 if (acer_tm360_irqrouting && dev->irq == 11 && 925 dev->vendor == PCI_VENDOR_ID_O2) { 926 pirq = 0x68; 927 mask = 0x400; 928 dev->irq = r->get(pirq_router_dev, dev, pirq); 929 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 930 } 931 932 /* 933 * Find the best IRQ to assign: use the one 934 * reported by the device if possible. 935 */ 936 newirq = dev->irq; 937 if (newirq && !((1 << newirq) & mask)) { 938 if (pci_probe & PCI_USE_PIRQ_MASK) 939 newirq = 0; 940 else 941 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask " 942 "%#x; try pci=usepirqmask\n", newirq, mask); 943 } 944 if (!newirq && assign) { 945 for (i = 0; i < 16; i++) { 946 if (!(mask & (1 << i))) 947 continue; 948 if (pirq_penalty[i] < pirq_penalty[newirq] && 949 can_request_irq(i, IRQF_SHARED)) 950 newirq = i; 951 } 952 } 953 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin, newirq); 954 955 /* Check if it is hardcoded */ 956 if ((pirq & 0xf0) == 0xf0) { 957 irq = pirq & 0xf; 958 msg = "hardcoded"; 959 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 960 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 961 msg = "found"; 962 eisa_set_level_irq(irq); 963 } else if (newirq && r->set && 964 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 965 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 966 eisa_set_level_irq(newirq); 967 msg = "assigned"; 968 irq = newirq; 969 } 970 } 971 972 if (!irq) { 973 if (newirq && mask == (1 << newirq)) { 974 msg = "guessed"; 975 irq = newirq; 976 } else { 977 dev_dbg(&dev->dev, "can't route interrupt\n"); 978 return 0; 979 } 980 } 981 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin, irq); 982 983 /* Update IRQ for all devices with the same pirq value */ 984 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) { 985 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 986 if (!pin) 987 continue; 988 pin--; 989 info = pirq_get_info(dev2); 990 if (!info) 991 continue; 992 if (info->irq[pin].link == pirq) { 993 /* 994 * We refuse to override the dev->irq 995 * information. Give a warning! 996 */ 997 if (dev2->irq && dev2->irq != irq && \ 998 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 999 ((1 << dev2->irq) & mask))) { 1000 #ifndef CONFIG_PCI_MSI 1001 dev_info(&dev2->dev, "IRQ routing conflict: " 1002 "have IRQ %d, want IRQ %d\n", 1003 dev2->irq, irq); 1004 #endif 1005 continue; 1006 } 1007 dev2->irq = irq; 1008 pirq_penalty[irq]++; 1009 if (dev != dev2) 1010 dev_info(&dev->dev, "sharing IRQ %d with %s\n", 1011 irq, pci_name(dev2)); 1012 } 1013 } 1014 return 1; 1015 } 1016 1017 static void __init pcibios_fixup_irqs(void) 1018 { 1019 struct pci_dev *dev = NULL; 1020 u8 pin; 1021 1022 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1023 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 1024 /* 1025 * If the BIOS has set an out of range IRQ number, just 1026 * ignore it. Also keep track of which IRQ's are 1027 * already in use. 1028 */ 1029 if (dev->irq >= 16) { 1030 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq); 1031 dev->irq = 0; 1032 } 1033 /* 1034 * If the IRQ is already assigned to a PCI device, 1035 * ignore its ISA use penalty 1036 */ 1037 if (pirq_penalty[dev->irq] >= 100 && 1038 pirq_penalty[dev->irq] < 100000) 1039 pirq_penalty[dev->irq] = 0; 1040 pirq_penalty[dev->irq]++; 1041 } 1042 1043 dev = NULL; 1044 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 1045 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1046 #ifdef CONFIG_X86_IO_APIC 1047 /* 1048 * Recalculate IRQ numbers if we use the I/O APIC. 1049 */ 1050 if (io_apic_assign_pci_irqs) { 1051 int irq; 1052 1053 if (!pin) 1054 continue; 1055 1056 /* 1057 * interrupt pins are numbered starting from 1 1058 */ 1059 pin--; 1060 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1061 PCI_SLOT(dev->devfn), pin); 1062 /* 1063 * Busses behind bridges are typically not listed in the 1064 * MP-table. In this case we have to look up the IRQ 1065 * based on the parent bus, parent slot, and pin number. 1066 * The SMP code detects such bridged busses itself so we 1067 * should get into this branch reliably. 1068 */ 1069 if (irq < 0 && dev->bus->parent) { 1070 /* go back to the bridge */ 1071 struct pci_dev *bridge = dev->bus->self; 1072 int bus; 1073 1074 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 1075 bus = bridge->bus->number; 1076 irq = IO_APIC_get_PCI_irq_vector(bus, 1077 PCI_SLOT(bridge->devfn), pin); 1078 if (irq >= 0) 1079 dev_warn(&dev->dev, 1080 "using bridge %s INT %c to " 1081 "get IRQ %d\n", 1082 pci_name(bridge), 1083 'A' + pin, irq); 1084 } 1085 if (irq >= 0) { 1086 dev_info(&dev->dev, 1087 "PCI->APIC IRQ transform: INT %c " 1088 "-> IRQ %d\n", 1089 'A' + pin, irq); 1090 dev->irq = irq; 1091 } 1092 } 1093 #endif 1094 /* 1095 * Still no IRQ? Try to lookup one... 1096 */ 1097 if (pin && !dev->irq) 1098 pcibios_lookup_irq(dev, 0); 1099 } 1100 } 1101 1102 /* 1103 * Work around broken HP Pavilion Notebooks which assign USB to 1104 * IRQ 9 even though it is actually wired to IRQ 11 1105 */ 1106 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1107 { 1108 if (!broken_hp_bios_irq9) { 1109 broken_hp_bios_irq9 = 1; 1110 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1111 d->ident); 1112 } 1113 return 0; 1114 } 1115 1116 /* 1117 * Work around broken Acer TravelMate 360 Notebooks which assign 1118 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1119 */ 1120 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1121 { 1122 if (!acer_tm360_irqrouting) { 1123 acer_tm360_irqrouting = 1; 1124 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1125 d->ident); 1126 } 1127 return 0; 1128 } 1129 1130 static struct dmi_system_id __initdata pciirq_dmi_table[] = { 1131 { 1132 .callback = fix_broken_hp_bios_irq9, 1133 .ident = "HP Pavilion N5400 Series Laptop", 1134 .matches = { 1135 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1136 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1137 DMI_MATCH(DMI_PRODUCT_VERSION, 1138 "HP Pavilion Notebook Model GE"), 1139 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1140 }, 1141 }, 1142 { 1143 .callback = fix_acer_tm360_irqrouting, 1144 .ident = "Acer TravelMate 36x Laptop", 1145 .matches = { 1146 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1147 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1148 }, 1149 }, 1150 { } 1151 }; 1152 1153 int __init pcibios_irq_init(void) 1154 { 1155 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1156 1157 if (pcibios_enable_irq || raw_pci_ops == NULL) 1158 return 0; 1159 1160 dmi_check_system(pciirq_dmi_table); 1161 1162 pirq_table = pirq_find_routing_table(); 1163 1164 #ifdef CONFIG_PCI_BIOS 1165 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) 1166 pirq_table = pcibios_get_irq_routing_table(); 1167 #endif 1168 if (pirq_table) { 1169 pirq_peer_trick(); 1170 pirq_find_router(&pirq_router); 1171 if (pirq_table->exclusive_irqs) { 1172 int i; 1173 for (i = 0; i < 16; i++) 1174 if (!(pirq_table->exclusive_irqs & (1 << i))) 1175 pirq_penalty[i] += 100; 1176 } 1177 /* 1178 * If we're using the I/O APIC, avoid using the PCI IRQ 1179 * routing table 1180 */ 1181 if (io_apic_assign_pci_irqs) 1182 pirq_table = NULL; 1183 } 1184 1185 pcibios_enable_irq = pirq_enable_irq; 1186 1187 pcibios_fixup_irqs(); 1188 return 0; 1189 } 1190 1191 static void pirq_penalize_isa_irq(int irq, int active) 1192 { 1193 /* 1194 * If any ISAPnP device reports an IRQ in its list of possible 1195 * IRQ's, we try to avoid assigning it to PCI devices. 1196 */ 1197 if (irq < 16) { 1198 if (active) 1199 pirq_penalty[irq] += 1000; 1200 else 1201 pirq_penalty[irq] += 100; 1202 } 1203 } 1204 1205 void pcibios_penalize_isa_irq(int irq, int active) 1206 { 1207 #ifdef CONFIG_ACPI 1208 if (!acpi_noirq) 1209 acpi_penalize_isa_irq(irq, active); 1210 else 1211 #endif 1212 pirq_penalize_isa_irq(irq, active); 1213 } 1214 1215 static int pirq_enable_irq(struct pci_dev *dev) 1216 { 1217 u8 pin; 1218 struct pci_dev *temp_dev; 1219 1220 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1221 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) { 1222 char *msg = ""; 1223 1224 pin--; /* interrupt pins are numbered starting from 1 */ 1225 1226 if (io_apic_assign_pci_irqs) { 1227 int irq; 1228 1229 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin); 1230 /* 1231 * Busses behind bridges are typically not listed in the MP-table. 1232 * In this case we have to look up the IRQ based on the parent bus, 1233 * parent slot, and pin number. The SMP code detects such bridged 1234 * busses itself so we should get into this branch reliably. 1235 */ 1236 temp_dev = dev; 1237 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1238 struct pci_dev *bridge = dev->bus->self; 1239 1240 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 1241 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1242 PCI_SLOT(bridge->devfn), pin); 1243 if (irq >= 0) 1244 dev_warn(&dev->dev, "using bridge %s " 1245 "INT %c to get IRQ %d\n", 1246 pci_name(bridge), 'A' + pin, 1247 irq); 1248 dev = bridge; 1249 } 1250 dev = temp_dev; 1251 if (irq >= 0) { 1252 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1253 "INT %c -> IRQ %d\n", 'A' + pin, irq); 1254 dev->irq = irq; 1255 return 0; 1256 } else 1257 msg = "; probably buggy MP table"; 1258 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1259 msg = ""; 1260 else 1261 msg = "; please try using pci=biosirq"; 1262 1263 /* 1264 * With IDE legacy devices the IRQ lookup failure is not 1265 * a problem.. 1266 */ 1267 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && 1268 !(dev->class & 0x5)) 1269 return 0; 1270 1271 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n", 1272 'A' + pin, msg); 1273 } 1274 return 0; 1275 } 1276