xref: /linux/arch/x86/pci/common.c (revision 5d4a2e29fba5b2bef95b96a46b338ec4d76fa4fd)
1 /*
2  *	Low-Level PCI Support for PC
3  *
4  *	(c) 1999--2000 Martin Mares <mj@ucw.cz>
5  */
6 
7 #include <linux/sched.h>
8 #include <linux/pci.h>
9 #include <linux/ioport.h>
10 #include <linux/init.h>
11 #include <linux/dmi.h>
12 #include <linux/slab.h>
13 
14 #include <asm/acpi.h>
15 #include <asm/segment.h>
16 #include <asm/io.h>
17 #include <asm/smp.h>
18 #include <asm/pci_x86.h>
19 
20 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
21 				PCI_PROBE_MMCONF;
22 
23 unsigned int pci_early_dump_regs;
24 static int pci_bf_sort;
25 int pci_routeirq;
26 int noioapicquirk;
27 #ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
28 int noioapicreroute = 0;
29 #else
30 int noioapicreroute = 1;
31 #endif
32 int pcibios_last_bus = -1;
33 unsigned long pirq_table_addr;
34 struct pci_bus *pci_root_bus;
35 struct pci_raw_ops *raw_pci_ops;
36 struct pci_raw_ops *raw_pci_ext_ops;
37 
38 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
39 						int reg, int len, u32 *val)
40 {
41 	if (domain == 0 && reg < 256 && raw_pci_ops)
42 		return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
43 	if (raw_pci_ext_ops)
44 		return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
45 	return -EINVAL;
46 }
47 
48 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
49 						int reg, int len, u32 val)
50 {
51 	if (domain == 0 && reg < 256 && raw_pci_ops)
52 		return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
53 	if (raw_pci_ext_ops)
54 		return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
55 	return -EINVAL;
56 }
57 
58 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
59 {
60 	return raw_pci_read(pci_domain_nr(bus), bus->number,
61 				 devfn, where, size, value);
62 }
63 
64 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
65 {
66 	return raw_pci_write(pci_domain_nr(bus), bus->number,
67 				  devfn, where, size, value);
68 }
69 
70 struct pci_ops pci_root_ops = {
71 	.read = pci_read,
72 	.write = pci_write,
73 };
74 
75 /*
76  * This interrupt-safe spinlock protects all accesses to PCI
77  * configuration space.
78  */
79 DEFINE_RAW_SPINLOCK(pci_config_lock);
80 
81 static int __devinit can_skip_ioresource_align(const struct dmi_system_id *d)
82 {
83 	pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
84 	printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
85 	return 0;
86 }
87 
88 static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __devinitconst = {
89 /*
90  * Systems where PCI IO resource ISA alignment can be skipped
91  * when the ISA enable bit in the bridge control is not set
92  */
93 	{
94 		.callback = can_skip_ioresource_align,
95 		.ident = "IBM System x3800",
96 		.matches = {
97 			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
98 			DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
99 		},
100 	},
101 	{
102 		.callback = can_skip_ioresource_align,
103 		.ident = "IBM System x3850",
104 		.matches = {
105 			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
106 			DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
107 		},
108 	},
109 	{
110 		.callback = can_skip_ioresource_align,
111 		.ident = "IBM System x3950",
112 		.matches = {
113 			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
114 			DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
115 		},
116 	},
117 	{}
118 };
119 
120 void __init dmi_check_skip_isa_align(void)
121 {
122 	dmi_check_system(can_skip_pciprobe_dmi_table);
123 }
124 
125 static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
126 {
127 	struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
128 
129 	if (pci_probe & PCI_NOASSIGN_ROMS) {
130 		if (rom_r->parent)
131 			return;
132 		if (rom_r->start) {
133 			/* we deal with BIOS assigned ROM later */
134 			return;
135 		}
136 		rom_r->start = rom_r->end = rom_r->flags = 0;
137 	}
138 }
139 
140 /*
141  *  Called after each bus is probed, but before its children
142  *  are examined.
143  */
144 
145 void __devinit pcibios_fixup_bus(struct pci_bus *b)
146 {
147 	struct pci_dev *dev;
148 
149 	/* root bus? */
150 	if (!b->parent)
151 		x86_pci_root_bus_res_quirks(b);
152 	pci_read_bridge_bases(b);
153 	list_for_each_entry(dev, &b->devices, bus_list)
154 		pcibios_fixup_device_resources(dev);
155 }
156 
157 /*
158  * Only use DMI information to set this if nothing was passed
159  * on the kernel command line (which was parsed earlier).
160  */
161 
162 static int __devinit set_bf_sort(const struct dmi_system_id *d)
163 {
164 	if (pci_bf_sort == pci_bf_sort_default) {
165 		pci_bf_sort = pci_dmi_bf;
166 		printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
167 	}
168 	return 0;
169 }
170 
171 /*
172  * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
173  */
174 #ifdef __i386__
175 static int __devinit assign_all_busses(const struct dmi_system_id *d)
176 {
177 	pci_probe |= PCI_ASSIGN_ALL_BUSSES;
178 	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
179 			" (pci=assign-busses)\n", d->ident);
180 	return 0;
181 }
182 #endif
183 
184 static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
185 #ifdef __i386__
186 /*
187  * Laptops which need pci=assign-busses to see Cardbus cards
188  */
189 	{
190 		.callback = assign_all_busses,
191 		.ident = "Samsung X20 Laptop",
192 		.matches = {
193 			DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
194 			DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
195 		},
196 	},
197 #endif		/* __i386__ */
198 	{
199 		.callback = set_bf_sort,
200 		.ident = "Dell PowerEdge 1950",
201 		.matches = {
202 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
203 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
204 		},
205 	},
206 	{
207 		.callback = set_bf_sort,
208 		.ident = "Dell PowerEdge 1955",
209 		.matches = {
210 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
211 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
212 		},
213 	},
214 	{
215 		.callback = set_bf_sort,
216 		.ident = "Dell PowerEdge 2900",
217 		.matches = {
218 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
219 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
220 		},
221 	},
222 	{
223 		.callback = set_bf_sort,
224 		.ident = "Dell PowerEdge 2950",
225 		.matches = {
226 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
227 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
228 		},
229 	},
230 	{
231 		.callback = set_bf_sort,
232 		.ident = "Dell PowerEdge R900",
233 		.matches = {
234 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
235 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
236 		},
237 	},
238 	{
239 		.callback = set_bf_sort,
240 		.ident = "HP ProLiant BL20p G3",
241 		.matches = {
242 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
243 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
244 		},
245 	},
246 	{
247 		.callback = set_bf_sort,
248 		.ident = "HP ProLiant BL20p G4",
249 		.matches = {
250 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
251 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
252 		},
253 	},
254 	{
255 		.callback = set_bf_sort,
256 		.ident = "HP ProLiant BL30p G1",
257 		.matches = {
258 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
259 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
260 		},
261 	},
262 	{
263 		.callback = set_bf_sort,
264 		.ident = "HP ProLiant BL25p G1",
265 		.matches = {
266 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
267 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
268 		},
269 	},
270 	{
271 		.callback = set_bf_sort,
272 		.ident = "HP ProLiant BL35p G1",
273 		.matches = {
274 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
275 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
276 		},
277 	},
278 	{
279 		.callback = set_bf_sort,
280 		.ident = "HP ProLiant BL45p G1",
281 		.matches = {
282 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
283 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
284 		},
285 	},
286 	{
287 		.callback = set_bf_sort,
288 		.ident = "HP ProLiant BL45p G2",
289 		.matches = {
290 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
291 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
292 		},
293 	},
294 	{
295 		.callback = set_bf_sort,
296 		.ident = "HP ProLiant BL460c G1",
297 		.matches = {
298 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
299 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
300 		},
301 	},
302 	{
303 		.callback = set_bf_sort,
304 		.ident = "HP ProLiant BL465c G1",
305 		.matches = {
306 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
307 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
308 		},
309 	},
310 	{
311 		.callback = set_bf_sort,
312 		.ident = "HP ProLiant BL480c G1",
313 		.matches = {
314 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
315 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
316 		},
317 	},
318 	{
319 		.callback = set_bf_sort,
320 		.ident = "HP ProLiant BL685c G1",
321 		.matches = {
322 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
323 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
324 		},
325 	},
326 	{
327 		.callback = set_bf_sort,
328 		.ident = "HP ProLiant DL360",
329 		.matches = {
330 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
331 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
332 		},
333 	},
334 	{
335 		.callback = set_bf_sort,
336 		.ident = "HP ProLiant DL380",
337 		.matches = {
338 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
339 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
340 		},
341 	},
342 #ifdef __i386__
343 	{
344 		.callback = assign_all_busses,
345 		.ident = "Compaq EVO N800c",
346 		.matches = {
347 			DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
348 			DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
349 		},
350 	},
351 #endif
352 	{
353 		.callback = set_bf_sort,
354 		.ident = "HP ProLiant DL385 G2",
355 		.matches = {
356 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
357 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
358 		},
359 	},
360 	{
361 		.callback = set_bf_sort,
362 		.ident = "HP ProLiant DL585 G2",
363 		.matches = {
364 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
365 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
366 		},
367 	},
368 	{}
369 };
370 
371 void __init dmi_check_pciprobe(void)
372 {
373 	dmi_check_system(pciprobe_dmi_table);
374 }
375 
376 struct pci_bus * __devinit pcibios_scan_root(int busnum)
377 {
378 	struct pci_bus *bus = NULL;
379 	struct pci_sysdata *sd;
380 
381 	while ((bus = pci_find_next_bus(bus)) != NULL) {
382 		if (bus->number == busnum) {
383 			/* Already scanned */
384 			return bus;
385 		}
386 	}
387 
388 	/* Allocate per-root-bus (not per bus) arch-specific data.
389 	 * TODO: leak; this memory is never freed.
390 	 * It's arguable whether it's worth the trouble to care.
391 	 */
392 	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
393 	if (!sd) {
394 		printk(KERN_ERR "PCI: OOM, not probing PCI bus %02x\n", busnum);
395 		return NULL;
396 	}
397 
398 	sd->node = get_mp_bus_to_node(busnum);
399 
400 	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
401 	bus = pci_scan_bus_parented(NULL, busnum, &pci_root_ops, sd);
402 	if (!bus)
403 		kfree(sd);
404 
405 	return bus;
406 }
407 
408 int __init pcibios_init(void)
409 {
410 	struct cpuinfo_x86 *c = &boot_cpu_data;
411 
412 	if (!raw_pci_ops) {
413 		printk(KERN_WARNING "PCI: System does not support PCI\n");
414 		return 0;
415 	}
416 
417 	/*
418 	 * Set PCI cacheline size to that of the CPU if the CPU has reported it.
419 	 * (For older CPUs that don't support cpuid, we se it to 32 bytes
420 	 * It's also good for 386/486s (which actually have 16)
421 	 * as quite a few PCI devices do not support smaller values.
422 	 */
423 	if (c->x86_clflush_size > 0) {
424 		pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
425 		printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
426 			pci_dfl_cache_line_size << 2);
427 	} else {
428  		pci_dfl_cache_line_size = 32 >> 2;
429 		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
430 	}
431 
432 	pcibios_resource_survey();
433 
434 	if (pci_bf_sort >= pci_force_bf)
435 		pci_sort_breadthfirst();
436 	return 0;
437 }
438 
439 char * __devinit  pcibios_setup(char *str)
440 {
441 	if (!strcmp(str, "off")) {
442 		pci_probe = 0;
443 		return NULL;
444 	} else if (!strcmp(str, "bfsort")) {
445 		pci_bf_sort = pci_force_bf;
446 		return NULL;
447 	} else if (!strcmp(str, "nobfsort")) {
448 		pci_bf_sort = pci_force_nobf;
449 		return NULL;
450 	}
451 #ifdef CONFIG_PCI_BIOS
452 	else if (!strcmp(str, "bios")) {
453 		pci_probe = PCI_PROBE_BIOS;
454 		return NULL;
455 	} else if (!strcmp(str, "nobios")) {
456 		pci_probe &= ~PCI_PROBE_BIOS;
457 		return NULL;
458 	} else if (!strcmp(str, "biosirq")) {
459 		pci_probe |= PCI_BIOS_IRQ_SCAN;
460 		return NULL;
461 	} else if (!strncmp(str, "pirqaddr=", 9)) {
462 		pirq_table_addr = simple_strtoul(str+9, NULL, 0);
463 		return NULL;
464 	}
465 #endif
466 #ifdef CONFIG_PCI_DIRECT
467 	else if (!strcmp(str, "conf1")) {
468 		pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
469 		return NULL;
470 	}
471 	else if (!strcmp(str, "conf2")) {
472 		pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
473 		return NULL;
474 	}
475 #endif
476 #ifdef CONFIG_PCI_MMCONFIG
477 	else if (!strcmp(str, "nommconf")) {
478 		pci_probe &= ~PCI_PROBE_MMCONF;
479 		return NULL;
480 	}
481 	else if (!strcmp(str, "check_enable_amd_mmconf")) {
482 		pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
483 		return NULL;
484 	}
485 #endif
486 	else if (!strcmp(str, "noacpi")) {
487 		acpi_noirq_set();
488 		return NULL;
489 	}
490 	else if (!strcmp(str, "noearly")) {
491 		pci_probe |= PCI_PROBE_NOEARLY;
492 		return NULL;
493 	}
494 #ifndef CONFIG_X86_VISWS
495 	else if (!strcmp(str, "usepirqmask")) {
496 		pci_probe |= PCI_USE_PIRQ_MASK;
497 		return NULL;
498 	} else if (!strncmp(str, "irqmask=", 8)) {
499 		pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
500 		return NULL;
501 	} else if (!strncmp(str, "lastbus=", 8)) {
502 		pcibios_last_bus = simple_strtol(str+8, NULL, 0);
503 		return NULL;
504 	}
505 #endif
506 	else if (!strcmp(str, "rom")) {
507 		pci_probe |= PCI_ASSIGN_ROMS;
508 		return NULL;
509 	} else if (!strcmp(str, "norom")) {
510 		pci_probe |= PCI_NOASSIGN_ROMS;
511 		return NULL;
512 	} else if (!strcmp(str, "assign-busses")) {
513 		pci_probe |= PCI_ASSIGN_ALL_BUSSES;
514 		return NULL;
515 	} else if (!strcmp(str, "use_crs")) {
516 		pci_probe |= PCI_USE__CRS;
517 		return NULL;
518 	} else if (!strcmp(str, "nocrs")) {
519 		pci_probe |= PCI_ROOT_NO_CRS;
520 		return NULL;
521 	} else if (!strcmp(str, "earlydump")) {
522 		pci_early_dump_regs = 1;
523 		return NULL;
524 	} else if (!strcmp(str, "routeirq")) {
525 		pci_routeirq = 1;
526 		return NULL;
527 	} else if (!strcmp(str, "skip_isa_align")) {
528 		pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
529 		return NULL;
530 	} else if (!strcmp(str, "noioapicquirk")) {
531 		noioapicquirk = 1;
532 		return NULL;
533 	} else if (!strcmp(str, "ioapicreroute")) {
534 		if (noioapicreroute != -1)
535 			noioapicreroute = 0;
536 		return NULL;
537 	} else if (!strcmp(str, "noioapicreroute")) {
538 		if (noioapicreroute != -1)
539 			noioapicreroute = 1;
540 		return NULL;
541 	}
542 	return str;
543 }
544 
545 unsigned int pcibios_assign_all_busses(void)
546 {
547 	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
548 }
549 
550 int pcibios_enable_device(struct pci_dev *dev, int mask)
551 {
552 	int err;
553 
554 	if ((err = pci_enable_resources(dev, mask)) < 0)
555 		return err;
556 
557 	if (!pci_dev_msi_enabled(dev))
558 		return pcibios_enable_irq(dev);
559 	return 0;
560 }
561 
562 void pcibios_disable_device (struct pci_dev *dev)
563 {
564 	if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
565 		pcibios_disable_irq(dev);
566 }
567 
568 int pci_ext_cfg_avail(struct pci_dev *dev)
569 {
570 	if (raw_pci_ext_ops)
571 		return 1;
572 	else
573 		return 0;
574 }
575 
576 struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node)
577 {
578 	struct pci_bus *bus = NULL;
579 	struct pci_sysdata *sd;
580 
581 	/*
582 	 * Allocate per-root-bus (not per bus) arch-specific data.
583 	 * TODO: leak; this memory is never freed.
584 	 * It's arguable whether it's worth the trouble to care.
585 	 */
586 	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
587 	if (!sd) {
588 		printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busno);
589 		return NULL;
590 	}
591 	sd->node = node;
592 	bus = pci_scan_bus(busno, ops, sd);
593 	if (!bus)
594 		kfree(sd);
595 
596 	return bus;
597 }
598 
599 struct pci_bus * __devinit pci_scan_bus_with_sysdata(int busno)
600 {
601 	return pci_scan_bus_on_node(busno, &pci_root_ops, -1);
602 }
603 
604 /*
605  * NUMA info for PCI busses
606  *
607  * Early arch code is responsible for filling in reasonable values here.
608  * A node id of "-1" means "use current node".  In other words, if a bus
609  * has a -1 node id, it's not tightly coupled to any particular chunk
610  * of memory (as is the case on some Nehalem systems).
611  */
612 #ifdef CONFIG_NUMA
613 
614 #define BUS_NR 256
615 
616 #ifdef CONFIG_X86_64
617 
618 static int mp_bus_to_node[BUS_NR] = {
619 	[0 ... BUS_NR - 1] = -1
620 };
621 
622 void set_mp_bus_to_node(int busnum, int node)
623 {
624 	if (busnum >= 0 &&  busnum < BUS_NR)
625 		mp_bus_to_node[busnum] = node;
626 }
627 
628 int get_mp_bus_to_node(int busnum)
629 {
630 	int node = -1;
631 
632 	if (busnum < 0 || busnum > (BUS_NR - 1))
633 		return node;
634 
635 	node = mp_bus_to_node[busnum];
636 
637 	/*
638 	 * let numa_node_id to decide it later in dma_alloc_pages
639 	 * if there is no ram on that node
640 	 */
641 	if (node != -1 && !node_online(node))
642 		node = -1;
643 
644 	return node;
645 }
646 
647 #else /* CONFIG_X86_32 */
648 
649 static int mp_bus_to_node[BUS_NR] = {
650 	[0 ... BUS_NR - 1] = -1
651 };
652 
653 void set_mp_bus_to_node(int busnum, int node)
654 {
655 	if (busnum >= 0 &&  busnum < BUS_NR)
656 	mp_bus_to_node[busnum] = (unsigned char) node;
657 }
658 
659 int get_mp_bus_to_node(int busnum)
660 {
661 	int node;
662 
663 	if (busnum < 0 || busnum > (BUS_NR - 1))
664 		return 0;
665 	node = mp_bus_to_node[busnum];
666 	return node;
667 }
668 
669 #endif /* CONFIG_X86_32 */
670 
671 #endif /* CONFIG_NUMA */
672