xref: /linux/arch/x86/pci/common.c (revision 2b8232ce512105e28453f301d1510de8363bccd1)
1 /*
2  *	Low-Level PCI Support for PC
3  *
4  *	(c) 1999--2000 Martin Mares <mj@ucw.cz>
5  */
6 
7 #include <linux/sched.h>
8 #include <linux/pci.h>
9 #include <linux/ioport.h>
10 #include <linux/init.h>
11 #include <linux/dmi.h>
12 
13 #include <asm/acpi.h>
14 #include <asm/segment.h>
15 #include <asm/io.h>
16 #include <asm/smp.h>
17 
18 #include "pci.h"
19 
20 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
21 				PCI_PROBE_MMCONF;
22 
23 static int pci_bf_sort;
24 int pci_routeirq;
25 int pcibios_last_bus = -1;
26 unsigned long pirq_table_addr;
27 struct pci_bus *pci_root_bus;
28 struct pci_raw_ops *raw_pci_ops;
29 
30 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
31 {
32 	return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
33 				 devfn, where, size, value);
34 }
35 
36 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
37 {
38 	return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
39 				  devfn, where, size, value);
40 }
41 
42 struct pci_ops pci_root_ops = {
43 	.read = pci_read,
44 	.write = pci_write,
45 };
46 
47 /*
48  * legacy, numa, and acpi all want to call pcibios_scan_root
49  * from their initcalls. This flag prevents that.
50  */
51 int pcibios_scanned;
52 
53 /*
54  * This interrupt-safe spinlock protects all accesses to PCI
55  * configuration space.
56  */
57 DEFINE_SPINLOCK(pci_config_lock);
58 
59 /*
60  * Several buggy motherboards address only 16 devices and mirror
61  * them to next 16 IDs. We try to detect this `feature' on all
62  * primary buses (those containing host bridges as they are
63  * expected to be unique) and remove the ghost devices.
64  */
65 
66 static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
67 {
68 	struct list_head *ln, *mn;
69 	struct pci_dev *d, *e;
70 	int mirror = PCI_DEVFN(16,0);
71 	int seen_host_bridge = 0;
72 	int i;
73 
74 	DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
75 	list_for_each(ln, &b->devices) {
76 		d = pci_dev_b(ln);
77 		if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
78 			seen_host_bridge++;
79 		for (mn=ln->next; mn != &b->devices; mn=mn->next) {
80 			e = pci_dev_b(mn);
81 			if (e->devfn != d->devfn + mirror ||
82 			    e->vendor != d->vendor ||
83 			    e->device != d->device ||
84 			    e->class != d->class)
85 				continue;
86 			for(i=0; i<PCI_NUM_RESOURCES; i++)
87 				if (e->resource[i].start != d->resource[i].start ||
88 				    e->resource[i].end != d->resource[i].end ||
89 				    e->resource[i].flags != d->resource[i].flags)
90 					continue;
91 			break;
92 		}
93 		if (mn == &b->devices)
94 			return;
95 	}
96 	if (!seen_host_bridge)
97 		return;
98 	printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
99 
100 	ln = &b->devices;
101 	while (ln->next != &b->devices) {
102 		d = pci_dev_b(ln->next);
103 		if (d->devfn >= mirror) {
104 			list_del(&d->global_list);
105 			list_del(&d->bus_list);
106 			kfree(d);
107 		} else
108 			ln = ln->next;
109 	}
110 }
111 
112 /*
113  *  Called after each bus is probed, but before its children
114  *  are examined.
115  */
116 
117 void __devinit  pcibios_fixup_bus(struct pci_bus *b)
118 {
119 	pcibios_fixup_ghosts(b);
120 	pci_read_bridge_bases(b);
121 }
122 
123 /*
124  * Only use DMI information to set this if nothing was passed
125  * on the kernel command line (which was parsed earlier).
126  */
127 
128 static int __devinit set_bf_sort(const struct dmi_system_id *d)
129 {
130 	if (pci_bf_sort == pci_bf_sort_default) {
131 		pci_bf_sort = pci_dmi_bf;
132 		printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
133 	}
134 	return 0;
135 }
136 
137 /*
138  * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
139  */
140 #ifdef __i386__
141 static int __devinit assign_all_busses(const struct dmi_system_id *d)
142 {
143 	pci_probe |= PCI_ASSIGN_ALL_BUSSES;
144 	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
145 			" (pci=assign-busses)\n", d->ident);
146 	return 0;
147 }
148 #endif
149 
150 static struct dmi_system_id __devinitdata pciprobe_dmi_table[] = {
151 #ifdef __i386__
152 /*
153  * Laptops which need pci=assign-busses to see Cardbus cards
154  */
155 	{
156 		.callback = assign_all_busses,
157 		.ident = "Samsung X20 Laptop",
158 		.matches = {
159 			DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
160 			DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
161 		},
162 	},
163 #endif		/* __i386__ */
164 	{
165 		.callback = set_bf_sort,
166 		.ident = "Dell PowerEdge 1950",
167 		.matches = {
168 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
169 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
170 		},
171 	},
172 	{
173 		.callback = set_bf_sort,
174 		.ident = "Dell PowerEdge 1955",
175 		.matches = {
176 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
177 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
178 		},
179 	},
180 	{
181 		.callback = set_bf_sort,
182 		.ident = "Dell PowerEdge 2900",
183 		.matches = {
184 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
185 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
186 		},
187 	},
188 	{
189 		.callback = set_bf_sort,
190 		.ident = "Dell PowerEdge 2950",
191 		.matches = {
192 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
193 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
194 		},
195 	},
196 	{
197 		.callback = set_bf_sort,
198 		.ident = "Dell PowerEdge R900",
199 		.matches = {
200 			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
201 			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
202 		},
203 	},
204 	{
205 		.callback = set_bf_sort,
206 		.ident = "HP ProLiant BL20p G3",
207 		.matches = {
208 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
209 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
210 		},
211 	},
212 	{
213 		.callback = set_bf_sort,
214 		.ident = "HP ProLiant BL20p G4",
215 		.matches = {
216 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
217 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
218 		},
219 	},
220 	{
221 		.callback = set_bf_sort,
222 		.ident = "HP ProLiant BL30p G1",
223 		.matches = {
224 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
225 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
226 		},
227 	},
228 	{
229 		.callback = set_bf_sort,
230 		.ident = "HP ProLiant BL25p G1",
231 		.matches = {
232 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
233 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
234 		},
235 	},
236 	{
237 		.callback = set_bf_sort,
238 		.ident = "HP ProLiant BL35p G1",
239 		.matches = {
240 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
241 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
242 		},
243 	},
244 	{
245 		.callback = set_bf_sort,
246 		.ident = "HP ProLiant BL45p G1",
247 		.matches = {
248 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
249 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
250 		},
251 	},
252 	{
253 		.callback = set_bf_sort,
254 		.ident = "HP ProLiant BL45p G2",
255 		.matches = {
256 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
257 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
258 		},
259 	},
260 	{
261 		.callback = set_bf_sort,
262 		.ident = "HP ProLiant BL460c G1",
263 		.matches = {
264 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
265 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
266 		},
267 	},
268 	{
269 		.callback = set_bf_sort,
270 		.ident = "HP ProLiant BL465c G1",
271 		.matches = {
272 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
273 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
274 		},
275 	},
276 	{
277 		.callback = set_bf_sort,
278 		.ident = "HP ProLiant BL480c G1",
279 		.matches = {
280 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
281 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
282 		},
283 	},
284 	{
285 		.callback = set_bf_sort,
286 		.ident = "HP ProLiant BL685c G1",
287 		.matches = {
288 			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
289 			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
290 		},
291 	},
292 #ifdef __i386__
293 	{
294 		.callback = assign_all_busses,
295 		.ident = "Compaq EVO N800c",
296 		.matches = {
297 			DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
298 			DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
299 		},
300 	},
301 #endif
302 	{}
303 };
304 
305 struct pci_bus * __devinit pcibios_scan_root(int busnum)
306 {
307 	struct pci_bus *bus = NULL;
308 	struct pci_sysdata *sd;
309 
310 	dmi_check_system(pciprobe_dmi_table);
311 
312 	while ((bus = pci_find_next_bus(bus)) != NULL) {
313 		if (bus->number == busnum) {
314 			/* Already scanned */
315 			return bus;
316 		}
317 	}
318 
319 	/* Allocate per-root-bus (not per bus) arch-specific data.
320 	 * TODO: leak; this memory is never freed.
321 	 * It's arguable whether it's worth the trouble to care.
322 	 */
323 	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
324 	if (!sd) {
325 		printk(KERN_ERR "PCI: OOM, not probing PCI bus %02x\n", busnum);
326 		return NULL;
327 	}
328 
329 	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
330 
331 	return pci_scan_bus_parented(NULL, busnum, &pci_root_ops, sd);
332 }
333 
334 extern u8 pci_cache_line_size;
335 
336 static int __init pcibios_init(void)
337 {
338 	struct cpuinfo_x86 *c = &boot_cpu_data;
339 
340 	if (!raw_pci_ops) {
341 		printk(KERN_WARNING "PCI: System does not support PCI\n");
342 		return 0;
343 	}
344 
345 	/*
346 	 * Assume PCI cacheline size of 32 bytes for all x86s except K7/K8
347 	 * and P4. It's also good for 386/486s (which actually have 16)
348 	 * as quite a few PCI devices do not support smaller values.
349 	 */
350 	pci_cache_line_size = 32 >> 2;
351 	if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
352 		pci_cache_line_size = 64 >> 2;	/* K7 & K8 */
353 	else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
354 		pci_cache_line_size = 128 >> 2;	/* P4 */
355 
356 	pcibios_resource_survey();
357 
358 	if (pci_bf_sort >= pci_force_bf)
359 		pci_sort_breadthfirst();
360 #ifdef CONFIG_PCI_BIOS
361 	if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
362 		pcibios_sort();
363 #endif
364 	return 0;
365 }
366 
367 subsys_initcall(pcibios_init);
368 
369 char * __devinit  pcibios_setup(char *str)
370 {
371 	if (!strcmp(str, "off")) {
372 		pci_probe = 0;
373 		return NULL;
374 	} else if (!strcmp(str, "bfsort")) {
375 		pci_bf_sort = pci_force_bf;
376 		return NULL;
377 	} else if (!strcmp(str, "nobfsort")) {
378 		pci_bf_sort = pci_force_nobf;
379 		return NULL;
380 	}
381 #ifdef CONFIG_PCI_BIOS
382 	else if (!strcmp(str, "bios")) {
383 		pci_probe = PCI_PROBE_BIOS;
384 		return NULL;
385 	} else if (!strcmp(str, "nobios")) {
386 		pci_probe &= ~PCI_PROBE_BIOS;
387 		return NULL;
388 	} else if (!strcmp(str, "nosort")) {
389 		pci_probe |= PCI_NO_SORT;
390 		return NULL;
391 	} else if (!strcmp(str, "biosirq")) {
392 		pci_probe |= PCI_BIOS_IRQ_SCAN;
393 		return NULL;
394 	} else if (!strncmp(str, "pirqaddr=", 9)) {
395 		pirq_table_addr = simple_strtoul(str+9, NULL, 0);
396 		return NULL;
397 	}
398 #endif
399 #ifdef CONFIG_PCI_DIRECT
400 	else if (!strcmp(str, "conf1")) {
401 		pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
402 		return NULL;
403 	}
404 	else if (!strcmp(str, "conf2")) {
405 		pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
406 		return NULL;
407 	}
408 #endif
409 #ifdef CONFIG_PCI_MMCONFIG
410 	else if (!strcmp(str, "nommconf")) {
411 		pci_probe &= ~PCI_PROBE_MMCONF;
412 		return NULL;
413 	}
414 #endif
415 	else if (!strcmp(str, "noacpi")) {
416 		acpi_noirq_set();
417 		return NULL;
418 	}
419 	else if (!strcmp(str, "noearly")) {
420 		pci_probe |= PCI_PROBE_NOEARLY;
421 		return NULL;
422 	}
423 #ifndef CONFIG_X86_VISWS
424 	else if (!strcmp(str, "usepirqmask")) {
425 		pci_probe |= PCI_USE_PIRQ_MASK;
426 		return NULL;
427 	} else if (!strncmp(str, "irqmask=", 8)) {
428 		pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
429 		return NULL;
430 	} else if (!strncmp(str, "lastbus=", 8)) {
431 		pcibios_last_bus = simple_strtol(str+8, NULL, 0);
432 		return NULL;
433 	}
434 #endif
435 	else if (!strcmp(str, "rom")) {
436 		pci_probe |= PCI_ASSIGN_ROMS;
437 		return NULL;
438 	} else if (!strcmp(str, "assign-busses")) {
439 		pci_probe |= PCI_ASSIGN_ALL_BUSSES;
440 		return NULL;
441 	} else if (!strcmp(str, "use_crs")) {
442 		pci_probe |= PCI_USE__CRS;
443 		return NULL;
444 	} else if (!strcmp(str, "routeirq")) {
445 		pci_routeirq = 1;
446 		return NULL;
447 	}
448 	return str;
449 }
450 
451 unsigned int pcibios_assign_all_busses(void)
452 {
453 	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
454 }
455 
456 int pcibios_enable_device(struct pci_dev *dev, int mask)
457 {
458 	int err;
459 
460 	if ((err = pcibios_enable_resources(dev, mask)) < 0)
461 		return err;
462 
463 	if (!dev->msi_enabled)
464 		return pcibios_enable_irq(dev);
465 	return 0;
466 }
467 
468 void pcibios_disable_device (struct pci_dev *dev)
469 {
470 	if (!dev->msi_enabled && pcibios_disable_irq)
471 		pcibios_disable_irq(dev);
472 }
473 
474 struct pci_bus *pci_scan_bus_with_sysdata(int busno)
475 {
476 	struct pci_bus *bus = NULL;
477 	struct pci_sysdata *sd;
478 
479 	/*
480 	 * Allocate per-root-bus (not per bus) arch-specific data.
481 	 * TODO: leak; this memory is never freed.
482 	 * It's arguable whether it's worth the trouble to care.
483 	 */
484 	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
485 	if (!sd) {
486 		printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busno);
487 		return NULL;
488 	}
489 	sd->node = -1;
490 	bus = pci_scan_bus(busno, &pci_root_ops, sd);
491 	if (!bus)
492 		kfree(sd);
493 
494 	return bus;
495 }
496