1 #include <linux/init.h> 2 #include <linux/pci.h> 3 #include <linux/topology.h> 4 #include <linux/cpu.h> 5 #include <linux/range.h> 6 7 #include <asm/amd_nb.h> 8 #include <asm/pci_x86.h> 9 10 #include <asm/pci-direct.h> 11 12 #include "bus_numa.h" 13 14 /* 15 * This discovers the pcibus <-> node mapping on AMD K8. 16 * also get peer root bus resource for io,mmio 17 */ 18 19 struct pci_hostbridge_probe { 20 u32 bus; 21 u32 slot; 22 u32 vendor; 23 u32 device; 24 }; 25 26 static struct pci_hostbridge_probe pci_probes[] __initdata = { 27 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 }, 28 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 }, 29 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 }, 30 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 }, 31 }; 32 33 #define RANGE_NUM 16 34 35 static struct pci_root_info __init *find_pci_root_info(int node, int link) 36 { 37 struct pci_root_info *info; 38 39 /* find the position */ 40 list_for_each_entry(info, &pci_root_infos, list) 41 if (info->node == node && info->link == link) 42 return info; 43 44 return NULL; 45 } 46 47 static void __init set_mp_bus_range_to_node(int min_bus, int max_bus, int node) 48 { 49 #ifdef CONFIG_NUMA 50 int j; 51 52 for (j = min_bus; j <= max_bus; j++) 53 set_mp_bus_to_node(j, node); 54 #endif 55 } 56 /** 57 * early_fill_mp_bus_to_node() 58 * called before pcibios_scan_root and pci_scan_bus 59 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number 60 * Registers found in the K8 northbridge 61 */ 62 static int __init early_fill_mp_bus_info(void) 63 { 64 int i; 65 unsigned bus; 66 unsigned slot; 67 int node; 68 int link; 69 int def_node; 70 int def_link; 71 struct pci_root_info *info; 72 u32 reg; 73 u64 start; 74 u64 end; 75 struct range range[RANGE_NUM]; 76 u64 val; 77 u32 address; 78 bool found; 79 struct resource fam10h_mmconf_res, *fam10h_mmconf; 80 u64 fam10h_mmconf_start; 81 u64 fam10h_mmconf_end; 82 83 if (!early_pci_allowed()) 84 return -1; 85 86 found = false; 87 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) { 88 u32 id; 89 u16 device; 90 u16 vendor; 91 92 bus = pci_probes[i].bus; 93 slot = pci_probes[i].slot; 94 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID); 95 96 vendor = id & 0xffff; 97 device = (id>>16) & 0xffff; 98 if (pci_probes[i].vendor == vendor && 99 pci_probes[i].device == device) { 100 found = true; 101 break; 102 } 103 } 104 105 if (!found) 106 return 0; 107 108 for (i = 0; i < 4; i++) { 109 int min_bus; 110 int max_bus; 111 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2)); 112 113 /* Check if that register is enabled for bus range */ 114 if ((reg & 7) != 3) 115 continue; 116 117 min_bus = (reg >> 16) & 0xff; 118 max_bus = (reg >> 24) & 0xff; 119 node = (reg >> 4) & 0x07; 120 set_mp_bus_range_to_node(min_bus, max_bus, node); 121 link = (reg >> 8) & 0x03; 122 123 info = alloc_pci_root_info(min_bus, max_bus, node, link); 124 sprintf(info->name, "PCI Bus #%02x", min_bus); 125 } 126 127 /* get the default node and link for left over res */ 128 reg = read_pci_config(bus, slot, 0, 0x60); 129 def_node = (reg >> 8) & 0x07; 130 reg = read_pci_config(bus, slot, 0, 0x64); 131 def_link = (reg >> 8) & 0x03; 132 133 memset(range, 0, sizeof(range)); 134 add_range(range, RANGE_NUM, 0, 0, 0xffff + 1); 135 /* io port resource */ 136 for (i = 0; i < 4; i++) { 137 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3)); 138 if (!(reg & 3)) 139 continue; 140 141 start = reg & 0xfff000; 142 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3)); 143 node = reg & 0x07; 144 link = (reg >> 4) & 0x03; 145 end = (reg & 0xfff000) | 0xfff; 146 147 info = find_pci_root_info(node, link); 148 if (!info) 149 continue; /* not found */ 150 151 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n", 152 node, link, start, end); 153 154 /* kernel only handle 16 bit only */ 155 if (end > 0xffff) 156 end = 0xffff; 157 update_res(info, start, end, IORESOURCE_IO, 1); 158 subtract_range(range, RANGE_NUM, start, end + 1); 159 } 160 /* add left over io port range to def node/link, [0, 0xffff] */ 161 /* find the position */ 162 info = find_pci_root_info(def_node, def_link); 163 if (info) { 164 for (i = 0; i < RANGE_NUM; i++) { 165 if (!range[i].end) 166 continue; 167 168 update_res(info, range[i].start, range[i].end - 1, 169 IORESOURCE_IO, 1); 170 } 171 } 172 173 memset(range, 0, sizeof(range)); 174 /* 0xfd00000000-0xffffffffff for HT */ 175 end = cap_resource((0xfdULL<<32) - 1); 176 end++; 177 add_range(range, RANGE_NUM, 0, 0, end); 178 179 /* need to take out [0, TOM) for RAM*/ 180 address = MSR_K8_TOP_MEM1; 181 rdmsrl(address, val); 182 end = (val & 0xffffff800000ULL); 183 printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20); 184 if (end < (1ULL<<32)) 185 subtract_range(range, RANGE_NUM, 0, end); 186 187 /* get mmconfig */ 188 fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res); 189 /* need to take out mmconf range */ 190 if (fam10h_mmconf) { 191 printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf); 192 fam10h_mmconf_start = fam10h_mmconf->start; 193 fam10h_mmconf_end = fam10h_mmconf->end; 194 subtract_range(range, RANGE_NUM, fam10h_mmconf_start, 195 fam10h_mmconf_end + 1); 196 } else { 197 fam10h_mmconf_start = 0; 198 fam10h_mmconf_end = 0; 199 } 200 201 /* mmio resource */ 202 for (i = 0; i < 8; i++) { 203 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3)); 204 if (!(reg & 3)) 205 continue; 206 207 start = reg & 0xffffff00; /* 39:16 on 31:8*/ 208 start <<= 8; 209 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3)); 210 node = reg & 0x07; 211 link = (reg >> 4) & 0x03; 212 end = (reg & 0xffffff00); 213 end <<= 8; 214 end |= 0xffff; 215 216 info = find_pci_root_info(node, link); 217 218 if (!info) 219 continue; 220 221 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]", 222 node, link, start, end); 223 /* 224 * some sick allocation would have range overlap with fam10h 225 * mmconf range, so need to update start and end. 226 */ 227 if (fam10h_mmconf_end) { 228 int changed = 0; 229 u64 endx = 0; 230 if (start >= fam10h_mmconf_start && 231 start <= fam10h_mmconf_end) { 232 start = fam10h_mmconf_end + 1; 233 changed = 1; 234 } 235 236 if (end >= fam10h_mmconf_start && 237 end <= fam10h_mmconf_end) { 238 end = fam10h_mmconf_start - 1; 239 changed = 1; 240 } 241 242 if (start < fam10h_mmconf_start && 243 end > fam10h_mmconf_end) { 244 /* we got a hole */ 245 endx = fam10h_mmconf_start - 1; 246 update_res(info, start, endx, IORESOURCE_MEM, 0); 247 subtract_range(range, RANGE_NUM, start, 248 endx + 1); 249 printk(KERN_CONT " ==> [%llx, %llx]", start, endx); 250 start = fam10h_mmconf_end + 1; 251 changed = 1; 252 } 253 if (changed) { 254 if (start <= end) { 255 printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end); 256 } else { 257 printk(KERN_CONT "%s\n", endx?"":" ==> none"); 258 continue; 259 } 260 } 261 } 262 263 update_res(info, cap_resource(start), cap_resource(end), 264 IORESOURCE_MEM, 1); 265 subtract_range(range, RANGE_NUM, start, end + 1); 266 printk(KERN_CONT "\n"); 267 } 268 269 /* need to take out [4G, TOM2) for RAM*/ 270 /* SYS_CFG */ 271 address = MSR_K8_SYSCFG; 272 rdmsrl(address, val); 273 /* TOP_MEM2 is enabled? */ 274 if (val & (1<<21)) { 275 /* TOP_MEM2 */ 276 address = MSR_K8_TOP_MEM2; 277 rdmsrl(address, val); 278 end = (val & 0xffffff800000ULL); 279 printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20); 280 subtract_range(range, RANGE_NUM, 1ULL<<32, end); 281 } 282 283 /* 284 * add left over mmio range to def node/link ? 285 * that is tricky, just record range in from start_min to 4G 286 */ 287 info = find_pci_root_info(def_node, def_link); 288 if (info) { 289 for (i = 0; i < RANGE_NUM; i++) { 290 if (!range[i].end) 291 continue; 292 293 update_res(info, cap_resource(range[i].start), 294 cap_resource(range[i].end - 1), 295 IORESOURCE_MEM, 1); 296 } 297 } 298 299 list_for_each_entry(info, &pci_root_infos, list) { 300 int busnum; 301 struct pci_root_res *root_res; 302 303 busnum = info->bus_min; 304 printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n", 305 info->bus_min, info->bus_max, info->node, info->link); 306 list_for_each_entry(root_res, &info->resources, list) 307 printk(KERN_DEBUG "bus: %02x %pR\n", 308 busnum, &root_res->res); 309 } 310 311 return 0; 312 } 313 314 #define ENABLE_CF8_EXT_CFG (1ULL << 46) 315 316 static void __cpuinit enable_pci_io_ecs(void *unused) 317 { 318 u64 reg; 319 rdmsrl(MSR_AMD64_NB_CFG, reg); 320 if (!(reg & ENABLE_CF8_EXT_CFG)) { 321 reg |= ENABLE_CF8_EXT_CFG; 322 wrmsrl(MSR_AMD64_NB_CFG, reg); 323 } 324 } 325 326 static int __cpuinit amd_cpu_notify(struct notifier_block *self, 327 unsigned long action, void *hcpu) 328 { 329 int cpu = (long)hcpu; 330 switch (action) { 331 case CPU_ONLINE: 332 case CPU_ONLINE_FROZEN: 333 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0); 334 break; 335 default: 336 break; 337 } 338 return NOTIFY_OK; 339 } 340 341 static struct notifier_block __cpuinitdata amd_cpu_notifier = { 342 .notifier_call = amd_cpu_notify, 343 }; 344 345 static void __init pci_enable_pci_io_ecs(void) 346 { 347 #ifdef CONFIG_AMD_NB 348 unsigned int i, n; 349 350 for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) { 351 u8 bus = amd_nb_bus_dev_ranges[i].bus; 352 u8 slot = amd_nb_bus_dev_ranges[i].dev_base; 353 u8 limit = amd_nb_bus_dev_ranges[i].dev_limit; 354 355 for (; slot < limit; ++slot) { 356 u32 val = read_pci_config(bus, slot, 3, 0); 357 358 if (!early_is_amd_nb(val)) 359 continue; 360 361 val = read_pci_config(bus, slot, 3, 0x8c); 362 if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) { 363 val |= ENABLE_CF8_EXT_CFG >> 32; 364 write_pci_config(bus, slot, 3, 0x8c, val); 365 } 366 ++n; 367 } 368 } 369 #endif 370 } 371 372 static int __init pci_io_ecs_init(void) 373 { 374 int cpu; 375 376 /* assume all cpus from fam10h have IO ECS */ 377 if (boot_cpu_data.x86 < 0x10) 378 return 0; 379 380 /* Try the PCI method first. */ 381 if (early_pci_allowed()) 382 pci_enable_pci_io_ecs(); 383 384 register_cpu_notifier(&amd_cpu_notifier); 385 for_each_online_cpu(cpu) 386 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE, 387 (void *)(long)cpu); 388 pci_probe |= PCI_HAS_IO_ECS; 389 390 return 0; 391 } 392 393 static int __init amd_postcore_init(void) 394 { 395 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 396 return 0; 397 398 early_fill_mp_bus_info(); 399 pci_io_ecs_init(); 400 401 return 0; 402 } 403 404 postcore_initcall(amd_postcore_init); 405