1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BPF JIT compiler 4 * 5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com) 6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com 7 */ 8 #include <linux/netdevice.h> 9 #include <linux/filter.h> 10 #include <linux/if_vlan.h> 11 #include <linux/bpf.h> 12 #include <linux/memory.h> 13 #include <linux/sort.h> 14 #include <asm/extable.h> 15 #include <asm/ftrace.h> 16 #include <asm/set_memory.h> 17 #include <asm/nospec-branch.h> 18 #include <asm/text-patching.h> 19 #include <asm/unwind.h> 20 #include <asm/cfi.h> 21 22 static bool all_callee_regs_used[4] = {true, true, true, true}; 23 24 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len) 25 { 26 if (len == 1) 27 *ptr = bytes; 28 else if (len == 2) 29 *(u16 *)ptr = bytes; 30 else { 31 *(u32 *)ptr = bytes; 32 barrier(); 33 } 34 return ptr + len; 35 } 36 37 #define EMIT(bytes, len) \ 38 do { prog = emit_code(prog, bytes, len); } while (0) 39 40 #define EMIT1(b1) EMIT(b1, 1) 41 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2) 42 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3) 43 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4) 44 45 #define EMIT1_off32(b1, off) \ 46 do { EMIT1(b1); EMIT(off, 4); } while (0) 47 #define EMIT2_off32(b1, b2, off) \ 48 do { EMIT2(b1, b2); EMIT(off, 4); } while (0) 49 #define EMIT3_off32(b1, b2, b3, off) \ 50 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0) 51 #define EMIT4_off32(b1, b2, b3, b4, off) \ 52 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0) 53 54 #ifdef CONFIG_X86_KERNEL_IBT 55 #define EMIT_ENDBR() EMIT(gen_endbr(), 4) 56 #define EMIT_ENDBR_POISON() EMIT(gen_endbr_poison(), 4) 57 #else 58 #define EMIT_ENDBR() 59 #define EMIT_ENDBR_POISON() 60 #endif 61 62 static bool is_imm8(int value) 63 { 64 return value <= 127 && value >= -128; 65 } 66 67 /* 68 * Let us limit the positive offset to be <= 123. 69 * This is to ensure eventual jit convergence For the following patterns: 70 * ... 71 * pass4, final_proglen=4391: 72 * ... 73 * 20e: 48 85 ff test rdi,rdi 74 * 211: 74 7d je 0x290 75 * 213: 48 8b 77 00 mov rsi,QWORD PTR [rdi+0x0] 76 * ... 77 * 289: 48 85 ff test rdi,rdi 78 * 28c: 74 17 je 0x2a5 79 * 28e: e9 7f ff ff ff jmp 0x212 80 * 293: bf 03 00 00 00 mov edi,0x3 81 * Note that insn at 0x211 is 2-byte cond jump insn for offset 0x7d (-125) 82 * and insn at 0x28e is 5-byte jmp insn with offset -129. 83 * 84 * pass5, final_proglen=4392: 85 * ... 86 * 20e: 48 85 ff test rdi,rdi 87 * 211: 0f 84 80 00 00 00 je 0x297 88 * 217: 48 8b 77 00 mov rsi,QWORD PTR [rdi+0x0] 89 * ... 90 * 28d: 48 85 ff test rdi,rdi 91 * 290: 74 1a je 0x2ac 92 * 292: eb 84 jmp 0x218 93 * 294: bf 03 00 00 00 mov edi,0x3 94 * Note that insn at 0x211 is 6-byte cond jump insn now since its offset 95 * becomes 0x80 based on previous round (0x293 - 0x213 = 0x80). 96 * At the same time, insn at 0x292 is a 2-byte insn since its offset is 97 * -124. 98 * 99 * pass6 will repeat the same code as in pass4 and this will prevent 100 * eventual convergence. 101 * 102 * To fix this issue, we need to break je (2->6 bytes) <-> jmp (5->2 bytes) 103 * cycle in the above. In the above example je offset <= 0x7c should work. 104 * 105 * For other cases, je <-> je needs offset <= 0x7b to avoid no convergence 106 * issue. For jmp <-> je and jmp <-> jmp cases, jmp offset <= 0x7c should 107 * avoid no convergence issue. 108 * 109 * Overall, let us limit the positive offset for 8bit cond/uncond jmp insn 110 * to maximum 123 (0x7b). This way, the jit pass can eventually converge. 111 */ 112 static bool is_imm8_jmp_offset(int value) 113 { 114 return value <= 123 && value >= -128; 115 } 116 117 static bool is_simm32(s64 value) 118 { 119 return value == (s64)(s32)value; 120 } 121 122 static bool is_uimm32(u64 value) 123 { 124 return value == (u64)(u32)value; 125 } 126 127 /* mov dst, src */ 128 #define EMIT_mov(DST, SRC) \ 129 do { \ 130 if (DST != SRC) \ 131 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \ 132 } while (0) 133 134 static int bpf_size_to_x86_bytes(int bpf_size) 135 { 136 if (bpf_size == BPF_W) 137 return 4; 138 else if (bpf_size == BPF_H) 139 return 2; 140 else if (bpf_size == BPF_B) 141 return 1; 142 else if (bpf_size == BPF_DW) 143 return 4; /* imm32 */ 144 else 145 return 0; 146 } 147 148 /* 149 * List of x86 cond jumps opcodes (. + s8) 150 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32) 151 */ 152 #define X86_JB 0x72 153 #define X86_JAE 0x73 154 #define X86_JE 0x74 155 #define X86_JNE 0x75 156 #define X86_JBE 0x76 157 #define X86_JA 0x77 158 #define X86_JL 0x7C 159 #define X86_JGE 0x7D 160 #define X86_JLE 0x7E 161 #define X86_JG 0x7F 162 163 /* Pick a register outside of BPF range for JIT internal work */ 164 #define AUX_REG (MAX_BPF_JIT_REG + 1) 165 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2) 166 #define X86_REG_R12 (MAX_BPF_JIT_REG + 3) 167 168 /* 169 * The following table maps BPF registers to x86-64 registers. 170 * 171 * x86-64 register R12 is unused, since if used as base address 172 * register in load/store instructions, it always needs an 173 * extra byte of encoding and is callee saved. 174 * 175 * x86-64 register R9 is not used by BPF programs, but can be used by BPF 176 * trampoline. x86-64 register R10 is used for blinding (if enabled). 177 */ 178 static const int reg2hex[] = { 179 [BPF_REG_0] = 0, /* RAX */ 180 [BPF_REG_1] = 7, /* RDI */ 181 [BPF_REG_2] = 6, /* RSI */ 182 [BPF_REG_3] = 2, /* RDX */ 183 [BPF_REG_4] = 1, /* RCX */ 184 [BPF_REG_5] = 0, /* R8 */ 185 [BPF_REG_6] = 3, /* RBX callee saved */ 186 [BPF_REG_7] = 5, /* R13 callee saved */ 187 [BPF_REG_8] = 6, /* R14 callee saved */ 188 [BPF_REG_9] = 7, /* R15 callee saved */ 189 [BPF_REG_FP] = 5, /* RBP readonly */ 190 [BPF_REG_AX] = 2, /* R10 temp register */ 191 [AUX_REG] = 3, /* R11 temp register */ 192 [X86_REG_R9] = 1, /* R9 register, 6th function argument */ 193 [X86_REG_R12] = 4, /* R12 callee saved */ 194 }; 195 196 static const int reg2pt_regs[] = { 197 [BPF_REG_0] = offsetof(struct pt_regs, ax), 198 [BPF_REG_1] = offsetof(struct pt_regs, di), 199 [BPF_REG_2] = offsetof(struct pt_regs, si), 200 [BPF_REG_3] = offsetof(struct pt_regs, dx), 201 [BPF_REG_4] = offsetof(struct pt_regs, cx), 202 [BPF_REG_5] = offsetof(struct pt_regs, r8), 203 [BPF_REG_6] = offsetof(struct pt_regs, bx), 204 [BPF_REG_7] = offsetof(struct pt_regs, r13), 205 [BPF_REG_8] = offsetof(struct pt_regs, r14), 206 [BPF_REG_9] = offsetof(struct pt_regs, r15), 207 }; 208 209 /* 210 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15 211 * which need extra byte of encoding. 212 * rax,rcx,...,rbp have simpler encoding 213 */ 214 static bool is_ereg(u32 reg) 215 { 216 return (1 << reg) & (BIT(BPF_REG_5) | 217 BIT(AUX_REG) | 218 BIT(BPF_REG_7) | 219 BIT(BPF_REG_8) | 220 BIT(BPF_REG_9) | 221 BIT(X86_REG_R9) | 222 BIT(X86_REG_R12) | 223 BIT(BPF_REG_AX)); 224 } 225 226 /* 227 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64 228 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte 229 * of encoding. al,cl,dl,bl have simpler encoding. 230 */ 231 static bool is_ereg_8l(u32 reg) 232 { 233 return is_ereg(reg) || 234 (1 << reg) & (BIT(BPF_REG_1) | 235 BIT(BPF_REG_2) | 236 BIT(BPF_REG_FP)); 237 } 238 239 static bool is_axreg(u32 reg) 240 { 241 return reg == BPF_REG_0; 242 } 243 244 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */ 245 static u8 add_1mod(u8 byte, u32 reg) 246 { 247 if (is_ereg(reg)) 248 byte |= 1; 249 return byte; 250 } 251 252 static u8 add_2mod(u8 byte, u32 r1, u32 r2) 253 { 254 if (is_ereg(r1)) 255 byte |= 1; 256 if (is_ereg(r2)) 257 byte |= 4; 258 return byte; 259 } 260 261 static u8 add_3mod(u8 byte, u32 r1, u32 r2, u32 index) 262 { 263 if (is_ereg(r1)) 264 byte |= 1; 265 if (is_ereg(index)) 266 byte |= 2; 267 if (is_ereg(r2)) 268 byte |= 4; 269 return byte; 270 } 271 272 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */ 273 static u8 add_1reg(u8 byte, u32 dst_reg) 274 { 275 return byte + reg2hex[dst_reg]; 276 } 277 278 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */ 279 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg) 280 { 281 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3); 282 } 283 284 /* Some 1-byte opcodes for binary ALU operations */ 285 static u8 simple_alu_opcodes[] = { 286 [BPF_ADD] = 0x01, 287 [BPF_SUB] = 0x29, 288 [BPF_AND] = 0x21, 289 [BPF_OR] = 0x09, 290 [BPF_XOR] = 0x31, 291 [BPF_LSH] = 0xE0, 292 [BPF_RSH] = 0xE8, 293 [BPF_ARSH] = 0xF8, 294 }; 295 296 static void jit_fill_hole(void *area, unsigned int size) 297 { 298 /* Fill whole space with INT3 instructions */ 299 memset(area, 0xcc, size); 300 } 301 302 int bpf_arch_text_invalidate(void *dst, size_t len) 303 { 304 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len)); 305 } 306 307 struct jit_context { 308 int cleanup_addr; /* Epilogue code offset */ 309 310 /* 311 * Program specific offsets of labels in the code; these rely on the 312 * JIT doing at least 2 passes, recording the position on the first 313 * pass, only to generate the correct offset on the second pass. 314 */ 315 int tail_call_direct_label; 316 int tail_call_indirect_label; 317 }; 318 319 /* Maximum number of bytes emitted while JITing one eBPF insn */ 320 #define BPF_MAX_INSN_SIZE 128 321 #define BPF_INSN_SAFETY 64 322 323 /* Number of bytes emit_patch() needs to generate instructions */ 324 #define X86_PATCH_SIZE 5 325 /* Number of bytes that will be skipped on tailcall */ 326 #define X86_TAIL_CALL_OFFSET (12 + ENDBR_INSN_SIZE) 327 328 static void push_r9(u8 **pprog) 329 { 330 u8 *prog = *pprog; 331 332 EMIT2(0x41, 0x51); /* push r9 */ 333 *pprog = prog; 334 } 335 336 static void pop_r9(u8 **pprog) 337 { 338 u8 *prog = *pprog; 339 340 EMIT2(0x41, 0x59); /* pop r9 */ 341 *pprog = prog; 342 } 343 344 static void push_r12(u8 **pprog) 345 { 346 u8 *prog = *pprog; 347 348 EMIT2(0x41, 0x54); /* push r12 */ 349 *pprog = prog; 350 } 351 352 static void push_callee_regs(u8 **pprog, bool *callee_regs_used) 353 { 354 u8 *prog = *pprog; 355 356 if (callee_regs_used[0]) 357 EMIT1(0x53); /* push rbx */ 358 if (callee_regs_used[1]) 359 EMIT2(0x41, 0x55); /* push r13 */ 360 if (callee_regs_used[2]) 361 EMIT2(0x41, 0x56); /* push r14 */ 362 if (callee_regs_used[3]) 363 EMIT2(0x41, 0x57); /* push r15 */ 364 *pprog = prog; 365 } 366 367 static void pop_r12(u8 **pprog) 368 { 369 u8 *prog = *pprog; 370 371 EMIT2(0x41, 0x5C); /* pop r12 */ 372 *pprog = prog; 373 } 374 375 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used) 376 { 377 u8 *prog = *pprog; 378 379 if (callee_regs_used[3]) 380 EMIT2(0x41, 0x5F); /* pop r15 */ 381 if (callee_regs_used[2]) 382 EMIT2(0x41, 0x5E); /* pop r14 */ 383 if (callee_regs_used[1]) 384 EMIT2(0x41, 0x5D); /* pop r13 */ 385 if (callee_regs_used[0]) 386 EMIT1(0x5B); /* pop rbx */ 387 *pprog = prog; 388 } 389 390 static void emit_nops(u8 **pprog, int len) 391 { 392 u8 *prog = *pprog; 393 int i, noplen; 394 395 while (len > 0) { 396 noplen = len; 397 398 if (noplen > ASM_NOP_MAX) 399 noplen = ASM_NOP_MAX; 400 401 for (i = 0; i < noplen; i++) 402 EMIT1(x86_nops[noplen][i]); 403 len -= noplen; 404 } 405 406 *pprog = prog; 407 } 408 409 /* 410 * Emit the various CFI preambles, see asm/cfi.h and the comments about FineIBT 411 * in arch/x86/kernel/alternative.c 412 */ 413 static int emit_call(u8 **prog, void *func, void *ip); 414 415 static void emit_fineibt(u8 **pprog, u8 *ip, u32 hash, int arity) 416 { 417 u8 *prog = *pprog; 418 419 EMIT_ENDBR(); 420 EMIT3_off32(0x41, 0x81, 0xea, hash); /* subl $hash, %r10d */ 421 if (cfi_bhi) { 422 emit_call(&prog, __bhi_args[arity], ip + 11); 423 } else { 424 EMIT2(0x75, 0xf9); /* jne.d8 .-7 */ 425 EMIT3(0x0f, 0x1f, 0x00); /* nop3 */ 426 } 427 EMIT_ENDBR_POISON(); 428 429 *pprog = prog; 430 } 431 432 static void emit_kcfi(u8 **pprog, u32 hash) 433 { 434 u8 *prog = *pprog; 435 436 EMIT1_off32(0xb8, hash); /* movl $hash, %eax */ 437 #ifdef CONFIG_CALL_PADDING 438 EMIT1(0x90); 439 EMIT1(0x90); 440 EMIT1(0x90); 441 EMIT1(0x90); 442 EMIT1(0x90); 443 EMIT1(0x90); 444 EMIT1(0x90); 445 EMIT1(0x90); 446 EMIT1(0x90); 447 EMIT1(0x90); 448 EMIT1(0x90); 449 #endif 450 EMIT_ENDBR(); 451 452 *pprog = prog; 453 } 454 455 static void emit_cfi(u8 **pprog, u8 *ip, u32 hash, int arity) 456 { 457 u8 *prog = *pprog; 458 459 switch (cfi_mode) { 460 case CFI_FINEIBT: 461 emit_fineibt(&prog, ip, hash, arity); 462 break; 463 464 case CFI_KCFI: 465 emit_kcfi(&prog, hash); 466 break; 467 468 default: 469 EMIT_ENDBR(); 470 break; 471 } 472 473 *pprog = prog; 474 } 475 476 static void emit_prologue_tail_call(u8 **pprog, bool is_subprog) 477 { 478 u8 *prog = *pprog; 479 480 if (!is_subprog) { 481 /* cmp rax, MAX_TAIL_CALL_CNT */ 482 EMIT4(0x48, 0x83, 0xF8, MAX_TAIL_CALL_CNT); 483 EMIT2(X86_JA, 6); /* ja 6 */ 484 /* rax is tail_call_cnt if <= MAX_TAIL_CALL_CNT. 485 * case1: entry of main prog. 486 * case2: tail callee of main prog. 487 */ 488 EMIT1(0x50); /* push rax */ 489 /* Make rax as tail_call_cnt_ptr. */ 490 EMIT3(0x48, 0x89, 0xE0); /* mov rax, rsp */ 491 EMIT2(0xEB, 1); /* jmp 1 */ 492 /* rax is tail_call_cnt_ptr if > MAX_TAIL_CALL_CNT. 493 * case: tail callee of subprog. 494 */ 495 EMIT1(0x50); /* push rax */ 496 /* push tail_call_cnt_ptr */ 497 EMIT1(0x50); /* push rax */ 498 } else { /* is_subprog */ 499 /* rax is tail_call_cnt_ptr. */ 500 EMIT1(0x50); /* push rax */ 501 EMIT1(0x50); /* push rax */ 502 } 503 504 *pprog = prog; 505 } 506 507 /* 508 * Emit x86-64 prologue code for BPF program. 509 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes 510 * while jumping to another program 511 */ 512 static void emit_prologue(u8 **pprog, u8 *ip, u32 stack_depth, bool ebpf_from_cbpf, 513 bool tail_call_reachable, bool is_subprog, 514 bool is_exception_cb) 515 { 516 u8 *prog = *pprog; 517 518 if (is_subprog) { 519 emit_cfi(&prog, ip, cfi_bpf_subprog_hash, 5); 520 } else { 521 emit_cfi(&prog, ip, cfi_bpf_hash, 1); 522 } 523 /* BPF trampoline can be made to work without these nops, 524 * but let's waste 5 bytes for now and optimize later 525 */ 526 emit_nops(&prog, X86_PATCH_SIZE); 527 if (!ebpf_from_cbpf) { 528 if (tail_call_reachable && !is_subprog) 529 /* When it's the entry of the whole tailcall context, 530 * zeroing rax means initialising tail_call_cnt. 531 */ 532 EMIT3(0x48, 0x31, 0xC0); /* xor rax, rax */ 533 else 534 /* Keep the same instruction layout. */ 535 emit_nops(&prog, 3); /* nop3 */ 536 } 537 /* Exception callback receives FP as third parameter */ 538 if (is_exception_cb) { 539 EMIT3(0x48, 0x89, 0xF4); /* mov rsp, rsi */ 540 EMIT3(0x48, 0x89, 0xD5); /* mov rbp, rdx */ 541 /* The main frame must have exception_boundary as true, so we 542 * first restore those callee-saved regs from stack, before 543 * reusing the stack frame. 544 */ 545 pop_callee_regs(&prog, all_callee_regs_used); 546 pop_r12(&prog); 547 /* Reset the stack frame. */ 548 EMIT3(0x48, 0x89, 0xEC); /* mov rsp, rbp */ 549 } else { 550 EMIT1(0x55); /* push rbp */ 551 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 552 } 553 554 /* X86_TAIL_CALL_OFFSET is here */ 555 EMIT_ENDBR(); 556 557 /* sub rsp, rounded_stack_depth */ 558 if (stack_depth) 559 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8)); 560 if (tail_call_reachable) 561 emit_prologue_tail_call(&prog, is_subprog); 562 *pprog = prog; 563 } 564 565 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode) 566 { 567 u8 *prog = *pprog; 568 s64 offset; 569 570 offset = func - (ip + X86_PATCH_SIZE); 571 if (!is_simm32(offset)) { 572 pr_err("Target call %p is out of range\n", func); 573 return -ERANGE; 574 } 575 EMIT1_off32(opcode, offset); 576 *pprog = prog; 577 return 0; 578 } 579 580 static int emit_call(u8 **pprog, void *func, void *ip) 581 { 582 return emit_patch(pprog, func, ip, 0xE8); 583 } 584 585 static int emit_rsb_call(u8 **pprog, void *func, void *ip) 586 { 587 OPTIMIZER_HIDE_VAR(func); 588 ip += x86_call_depth_emit_accounting(pprog, func, ip); 589 return emit_patch(pprog, func, ip, 0xE8); 590 } 591 592 static int emit_jump(u8 **pprog, void *func, void *ip) 593 { 594 return emit_patch(pprog, func, ip, 0xE9); 595 } 596 597 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 598 void *old_addr, void *new_addr) 599 { 600 const u8 *nop_insn = x86_nops[5]; 601 u8 old_insn[X86_PATCH_SIZE]; 602 u8 new_insn[X86_PATCH_SIZE]; 603 u8 *prog; 604 int ret; 605 606 memcpy(old_insn, nop_insn, X86_PATCH_SIZE); 607 if (old_addr) { 608 prog = old_insn; 609 ret = t == BPF_MOD_CALL ? 610 emit_call(&prog, old_addr, ip) : 611 emit_jump(&prog, old_addr, ip); 612 if (ret) 613 return ret; 614 } 615 616 memcpy(new_insn, nop_insn, X86_PATCH_SIZE); 617 if (new_addr) { 618 prog = new_insn; 619 ret = t == BPF_MOD_CALL ? 620 emit_call(&prog, new_addr, ip) : 621 emit_jump(&prog, new_addr, ip); 622 if (ret) 623 return ret; 624 } 625 626 ret = -EBUSY; 627 mutex_lock(&text_mutex); 628 if (memcmp(ip, old_insn, X86_PATCH_SIZE)) 629 goto out; 630 ret = 1; 631 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) { 632 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL); 633 ret = 0; 634 } 635 out: 636 mutex_unlock(&text_mutex); 637 return ret; 638 } 639 640 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 641 void *old_addr, void *new_addr) 642 { 643 if (!is_kernel_text((long)ip) && 644 !is_bpf_text_address((long)ip)) 645 /* BPF poking in modules is not supported */ 646 return -EINVAL; 647 648 /* 649 * See emit_prologue(), for IBT builds the trampoline hook is preceded 650 * with an ENDBR instruction. 651 */ 652 if (is_endbr(ip)) 653 ip += ENDBR_INSN_SIZE; 654 655 return __bpf_arch_text_poke(ip, t, old_addr, new_addr); 656 } 657 658 #define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8) 659 660 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip) 661 { 662 u8 *prog = *pprog; 663 664 if (cpu_feature_enabled(X86_FEATURE_INDIRECT_THUNK_ITS)) { 665 OPTIMIZER_HIDE_VAR(reg); 666 emit_jump(&prog, its_static_thunk(reg), ip); 667 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 668 EMIT_LFENCE(); 669 EMIT2(0xFF, 0xE0 + reg); 670 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) { 671 OPTIMIZER_HIDE_VAR(reg); 672 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH)) 673 emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip); 674 else 675 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip); 676 } else { 677 EMIT2(0xFF, 0xE0 + reg); /* jmp *%\reg */ 678 if (IS_ENABLED(CONFIG_MITIGATION_RETPOLINE) || IS_ENABLED(CONFIG_MITIGATION_SLS)) 679 EMIT1(0xCC); /* int3 */ 680 } 681 682 *pprog = prog; 683 } 684 685 static void emit_return(u8 **pprog, u8 *ip) 686 { 687 u8 *prog = *pprog; 688 689 if (cpu_wants_rethunk()) { 690 emit_jump(&prog, x86_return_thunk, ip); 691 } else { 692 EMIT1(0xC3); /* ret */ 693 if (IS_ENABLED(CONFIG_MITIGATION_SLS)) 694 EMIT1(0xCC); /* int3 */ 695 } 696 697 *pprog = prog; 698 } 699 700 #define BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack) (-16 - round_up(stack, 8)) 701 702 /* 703 * Generate the following code: 704 * 705 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ... 706 * if (index >= array->map.max_entries) 707 * goto out; 708 * if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT) 709 * goto out; 710 * prog = array->ptrs[index]; 711 * if (prog == NULL) 712 * goto out; 713 * goto *(prog->bpf_func + prologue_size); 714 * out: 715 */ 716 static void emit_bpf_tail_call_indirect(struct bpf_prog *bpf_prog, 717 u8 **pprog, bool *callee_regs_used, 718 u32 stack_depth, u8 *ip, 719 struct jit_context *ctx) 720 { 721 int tcc_ptr_off = BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack_depth); 722 u8 *prog = *pprog, *start = *pprog; 723 int offset; 724 725 /* 726 * rdi - pointer to ctx 727 * rsi - pointer to bpf_array 728 * rdx - index in bpf_array 729 */ 730 731 /* 732 * if (index >= array->map.max_entries) 733 * goto out; 734 */ 735 EMIT2(0x89, 0xD2); /* mov edx, edx */ 736 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */ 737 offsetof(struct bpf_array, map.max_entries)); 738 739 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 740 EMIT2(X86_JBE, offset); /* jbe out */ 741 742 /* 743 * if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT) 744 * goto out; 745 */ 746 EMIT3_off32(0x48, 0x8B, 0x85, tcc_ptr_off); /* mov rax, qword ptr [rbp - tcc_ptr_off] */ 747 EMIT4(0x48, 0x83, 0x38, MAX_TAIL_CALL_CNT); /* cmp qword ptr [rax], MAX_TAIL_CALL_CNT */ 748 749 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 750 EMIT2(X86_JAE, offset); /* jae out */ 751 752 /* prog = array->ptrs[index]; */ 753 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */ 754 offsetof(struct bpf_array, ptrs)); 755 756 /* 757 * if (prog == NULL) 758 * goto out; 759 */ 760 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */ 761 762 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 763 EMIT2(X86_JE, offset); /* je out */ 764 765 /* Inc tail_call_cnt if the slot is populated. */ 766 EMIT4(0x48, 0x83, 0x00, 0x01); /* add qword ptr [rax], 1 */ 767 768 if (bpf_prog->aux->exception_boundary) { 769 pop_callee_regs(&prog, all_callee_regs_used); 770 pop_r12(&prog); 771 } else { 772 pop_callee_regs(&prog, callee_regs_used); 773 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena)) 774 pop_r12(&prog); 775 } 776 777 /* Pop tail_call_cnt_ptr. */ 778 EMIT1(0x58); /* pop rax */ 779 /* Pop tail_call_cnt, if it's main prog. 780 * Pop tail_call_cnt_ptr, if it's subprog. 781 */ 782 EMIT1(0x58); /* pop rax */ 783 if (stack_depth) 784 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */ 785 round_up(stack_depth, 8)); 786 787 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */ 788 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */ 789 offsetof(struct bpf_prog, bpf_func)); 790 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */ 791 X86_TAIL_CALL_OFFSET); 792 /* 793 * Now we're ready to jump into next BPF program 794 * rdi == ctx (1st arg) 795 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET 796 */ 797 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start)); 798 799 /* out: */ 800 ctx->tail_call_indirect_label = prog - start; 801 *pprog = prog; 802 } 803 804 static void emit_bpf_tail_call_direct(struct bpf_prog *bpf_prog, 805 struct bpf_jit_poke_descriptor *poke, 806 u8 **pprog, u8 *ip, 807 bool *callee_regs_used, u32 stack_depth, 808 struct jit_context *ctx) 809 { 810 int tcc_ptr_off = BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack_depth); 811 u8 *prog = *pprog, *start = *pprog; 812 int offset; 813 814 /* 815 * if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT) 816 * goto out; 817 */ 818 EMIT3_off32(0x48, 0x8B, 0x85, tcc_ptr_off); /* mov rax, qword ptr [rbp - tcc_ptr_off] */ 819 EMIT4(0x48, 0x83, 0x38, MAX_TAIL_CALL_CNT); /* cmp qword ptr [rax], MAX_TAIL_CALL_CNT */ 820 821 offset = ctx->tail_call_direct_label - (prog + 2 - start); 822 EMIT2(X86_JAE, offset); /* jae out */ 823 824 poke->tailcall_bypass = ip + (prog - start); 825 poke->adj_off = X86_TAIL_CALL_OFFSET; 826 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE; 827 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE; 828 829 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE, 830 poke->tailcall_bypass); 831 832 /* Inc tail_call_cnt if the slot is populated. */ 833 EMIT4(0x48, 0x83, 0x00, 0x01); /* add qword ptr [rax], 1 */ 834 835 if (bpf_prog->aux->exception_boundary) { 836 pop_callee_regs(&prog, all_callee_regs_used); 837 pop_r12(&prog); 838 } else { 839 pop_callee_regs(&prog, callee_regs_used); 840 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena)) 841 pop_r12(&prog); 842 } 843 844 /* Pop tail_call_cnt_ptr. */ 845 EMIT1(0x58); /* pop rax */ 846 /* Pop tail_call_cnt, if it's main prog. 847 * Pop tail_call_cnt_ptr, if it's subprog. 848 */ 849 EMIT1(0x58); /* pop rax */ 850 if (stack_depth) 851 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8)); 852 853 emit_nops(&prog, X86_PATCH_SIZE); 854 855 /* out: */ 856 ctx->tail_call_direct_label = prog - start; 857 858 *pprog = prog; 859 } 860 861 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog) 862 { 863 struct bpf_jit_poke_descriptor *poke; 864 struct bpf_array *array; 865 struct bpf_prog *target; 866 int i, ret; 867 868 for (i = 0; i < prog->aux->size_poke_tab; i++) { 869 poke = &prog->aux->poke_tab[i]; 870 if (poke->aux && poke->aux != prog->aux) 871 continue; 872 873 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable)); 874 875 if (poke->reason != BPF_POKE_REASON_TAIL_CALL) 876 continue; 877 878 array = container_of(poke->tail_call.map, struct bpf_array, map); 879 mutex_lock(&array->aux->poke_mutex); 880 target = array->ptrs[poke->tail_call.key]; 881 if (target) { 882 ret = __bpf_arch_text_poke(poke->tailcall_target, 883 BPF_MOD_JUMP, NULL, 884 (u8 *)target->bpf_func + 885 poke->adj_off); 886 BUG_ON(ret < 0); 887 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 888 BPF_MOD_JUMP, 889 (u8 *)poke->tailcall_target + 890 X86_PATCH_SIZE, NULL); 891 BUG_ON(ret < 0); 892 } 893 WRITE_ONCE(poke->tailcall_target_stable, true); 894 mutex_unlock(&array->aux->poke_mutex); 895 } 896 } 897 898 static void emit_mov_imm32(u8 **pprog, bool sign_propagate, 899 u32 dst_reg, const u32 imm32) 900 { 901 u8 *prog = *pprog; 902 u8 b1, b2, b3; 903 904 /* 905 * Optimization: if imm32 is positive, use 'mov %eax, imm32' 906 * (which zero-extends imm32) to save 2 bytes. 907 */ 908 if (sign_propagate && (s32)imm32 < 0) { 909 /* 'mov %rax, imm32' sign extends imm32 */ 910 b1 = add_1mod(0x48, dst_reg); 911 b2 = 0xC7; 912 b3 = 0xC0; 913 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32); 914 goto done; 915 } 916 917 /* 918 * Optimization: if imm32 is zero, use 'xor %eax, %eax' 919 * to save 3 bytes. 920 */ 921 if (imm32 == 0) { 922 if (is_ereg(dst_reg)) 923 EMIT1(add_2mod(0x40, dst_reg, dst_reg)); 924 b2 = 0x31; /* xor */ 925 b3 = 0xC0; 926 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg)); 927 goto done; 928 } 929 930 /* mov %eax, imm32 */ 931 if (is_ereg(dst_reg)) 932 EMIT1(add_1mod(0x40, dst_reg)); 933 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32); 934 done: 935 *pprog = prog; 936 } 937 938 static void emit_mov_imm64(u8 **pprog, u32 dst_reg, 939 const u32 imm32_hi, const u32 imm32_lo) 940 { 941 u64 imm64 = ((u64)imm32_hi << 32) | (u32)imm32_lo; 942 u8 *prog = *pprog; 943 944 if (is_uimm32(imm64)) { 945 /* 946 * For emitting plain u32, where sign bit must not be 947 * propagated LLVM tends to load imm64 over mov32 948 * directly, so save couple of bytes by just doing 949 * 'mov %eax, imm32' instead. 950 */ 951 emit_mov_imm32(&prog, false, dst_reg, imm32_lo); 952 } else if (is_simm32(imm64)) { 953 emit_mov_imm32(&prog, true, dst_reg, imm32_lo); 954 } else { 955 /* movabsq rax, imm64 */ 956 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg)); 957 EMIT(imm32_lo, 4); 958 EMIT(imm32_hi, 4); 959 } 960 961 *pprog = prog; 962 } 963 964 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg) 965 { 966 u8 *prog = *pprog; 967 968 if (is64) { 969 /* mov dst, src */ 970 EMIT_mov(dst_reg, src_reg); 971 } else { 972 /* mov32 dst, src */ 973 if (is_ereg(dst_reg) || is_ereg(src_reg)) 974 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 975 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg)); 976 } 977 978 *pprog = prog; 979 } 980 981 static void emit_movsx_reg(u8 **pprog, int num_bits, bool is64, u32 dst_reg, 982 u32 src_reg) 983 { 984 u8 *prog = *pprog; 985 986 if (is64) { 987 /* movs[b,w,l]q dst, src */ 988 if (num_bits == 8) 989 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbe, 990 add_2reg(0xC0, src_reg, dst_reg)); 991 else if (num_bits == 16) 992 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbf, 993 add_2reg(0xC0, src_reg, dst_reg)); 994 else if (num_bits == 32) 995 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x63, 996 add_2reg(0xC0, src_reg, dst_reg)); 997 } else { 998 /* movs[b,w]l dst, src */ 999 if (num_bits == 8) { 1000 EMIT4(add_2mod(0x40, src_reg, dst_reg), 0x0f, 0xbe, 1001 add_2reg(0xC0, src_reg, dst_reg)); 1002 } else if (num_bits == 16) { 1003 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1004 EMIT1(add_2mod(0x40, src_reg, dst_reg)); 1005 EMIT3(add_2mod(0x0f, src_reg, dst_reg), 0xbf, 1006 add_2reg(0xC0, src_reg, dst_reg)); 1007 } 1008 } 1009 1010 *pprog = prog; 1011 } 1012 1013 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */ 1014 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off) 1015 { 1016 u8 *prog = *pprog; 1017 1018 if (is_imm8(off)) { 1019 /* 1-byte signed displacement. 1020 * 1021 * If off == 0 we could skip this and save one extra byte, but 1022 * special case of x86 R13 which always needs an offset is not 1023 * worth the hassle 1024 */ 1025 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off); 1026 } else { 1027 /* 4-byte signed displacement */ 1028 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off); 1029 } 1030 *pprog = prog; 1031 } 1032 1033 static void emit_insn_suffix_SIB(u8 **pprog, u32 ptr_reg, u32 val_reg, u32 index_reg, int off) 1034 { 1035 u8 *prog = *pprog; 1036 1037 if (is_imm8(off)) { 1038 EMIT3(add_2reg(0x44, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off); 1039 } else { 1040 EMIT2_off32(add_2reg(0x84, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off); 1041 } 1042 *pprog = prog; 1043 } 1044 1045 /* 1046 * Emit a REX byte if it will be necessary to address these registers 1047 */ 1048 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64) 1049 { 1050 u8 *prog = *pprog; 1051 1052 if (is64) 1053 EMIT1(add_2mod(0x48, dst_reg, src_reg)); 1054 else if (is_ereg(dst_reg) || is_ereg(src_reg)) 1055 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 1056 *pprog = prog; 1057 } 1058 1059 /* 1060 * Similar version of maybe_emit_mod() for a single register 1061 */ 1062 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64) 1063 { 1064 u8 *prog = *pprog; 1065 1066 if (is64) 1067 EMIT1(add_1mod(0x48, reg)); 1068 else if (is_ereg(reg)) 1069 EMIT1(add_1mod(0x40, reg)); 1070 *pprog = prog; 1071 } 1072 1073 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 1074 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1075 { 1076 u8 *prog = *pprog; 1077 1078 switch (size) { 1079 case BPF_B: 1080 /* Emit 'movzx rax, byte ptr [rax + off]' */ 1081 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6); 1082 break; 1083 case BPF_H: 1084 /* Emit 'movzx rax, word ptr [rax + off]' */ 1085 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7); 1086 break; 1087 case BPF_W: 1088 /* Emit 'mov eax, dword ptr [rax+0x14]' */ 1089 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1090 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B); 1091 else 1092 EMIT1(0x8B); 1093 break; 1094 case BPF_DW: 1095 /* Emit 'mov rax, qword ptr [rax+0x14]' */ 1096 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B); 1097 break; 1098 } 1099 emit_insn_suffix(&prog, src_reg, dst_reg, off); 1100 *pprog = prog; 1101 } 1102 1103 /* LDSX: dst_reg = *(s8*)(src_reg + off) */ 1104 static void emit_ldsx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1105 { 1106 u8 *prog = *pprog; 1107 1108 switch (size) { 1109 case BPF_B: 1110 /* Emit 'movsx rax, byte ptr [rax + off]' */ 1111 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBE); 1112 break; 1113 case BPF_H: 1114 /* Emit 'movsx rax, word ptr [rax + off]' */ 1115 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBF); 1116 break; 1117 case BPF_W: 1118 /* Emit 'movsx rax, dword ptr [rax+0x14]' */ 1119 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x63); 1120 break; 1121 } 1122 emit_insn_suffix(&prog, src_reg, dst_reg, off); 1123 *pprog = prog; 1124 } 1125 1126 static void emit_ldx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1127 { 1128 u8 *prog = *pprog; 1129 1130 switch (size) { 1131 case BPF_B: 1132 /* movzx rax, byte ptr [rax + r12 + off] */ 1133 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB6); 1134 break; 1135 case BPF_H: 1136 /* movzx rax, word ptr [rax + r12 + off] */ 1137 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB7); 1138 break; 1139 case BPF_W: 1140 /* mov eax, dword ptr [rax + r12 + off] */ 1141 EMIT2(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x8B); 1142 break; 1143 case BPF_DW: 1144 /* mov rax, qword ptr [rax + r12 + off] */ 1145 EMIT2(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x8B); 1146 break; 1147 } 1148 emit_insn_suffix_SIB(&prog, src_reg, dst_reg, index_reg, off); 1149 *pprog = prog; 1150 } 1151 1152 static void emit_ldx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1153 { 1154 emit_ldx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off); 1155 } 1156 1157 /* STX: *(u8*)(dst_reg + off) = src_reg */ 1158 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1159 { 1160 u8 *prog = *pprog; 1161 1162 switch (size) { 1163 case BPF_B: 1164 /* Emit 'mov byte ptr [rax + off], al' */ 1165 if (is_ereg(dst_reg) || is_ereg_8l(src_reg)) 1166 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */ 1167 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88); 1168 else 1169 EMIT1(0x88); 1170 break; 1171 case BPF_H: 1172 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1173 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89); 1174 else 1175 EMIT2(0x66, 0x89); 1176 break; 1177 case BPF_W: 1178 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1179 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89); 1180 else 1181 EMIT1(0x89); 1182 break; 1183 case BPF_DW: 1184 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89); 1185 break; 1186 } 1187 emit_insn_suffix(&prog, dst_reg, src_reg, off); 1188 *pprog = prog; 1189 } 1190 1191 /* STX: *(u8*)(dst_reg + index_reg + off) = src_reg */ 1192 static void emit_stx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1193 { 1194 u8 *prog = *pprog; 1195 1196 switch (size) { 1197 case BPF_B: 1198 /* mov byte ptr [rax + r12 + off], al */ 1199 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x88); 1200 break; 1201 case BPF_H: 1202 /* mov word ptr [rax + r12 + off], ax */ 1203 EMIT3(0x66, add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89); 1204 break; 1205 case BPF_W: 1206 /* mov dword ptr [rax + r12 + 1], eax */ 1207 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89); 1208 break; 1209 case BPF_DW: 1210 /* mov qword ptr [rax + r12 + 1], rax */ 1211 EMIT2(add_3mod(0x48, dst_reg, src_reg, index_reg), 0x89); 1212 break; 1213 } 1214 emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off); 1215 *pprog = prog; 1216 } 1217 1218 static void emit_stx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1219 { 1220 emit_stx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off); 1221 } 1222 1223 /* ST: *(u8*)(dst_reg + index_reg + off) = imm32 */ 1224 static void emit_st_index(u8 **pprog, u32 size, u32 dst_reg, u32 index_reg, int off, int imm) 1225 { 1226 u8 *prog = *pprog; 1227 1228 switch (size) { 1229 case BPF_B: 1230 /* mov byte ptr [rax + r12 + off], imm8 */ 1231 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC6); 1232 break; 1233 case BPF_H: 1234 /* mov word ptr [rax + r12 + off], imm16 */ 1235 EMIT3(0x66, add_3mod(0x40, dst_reg, 0, index_reg), 0xC7); 1236 break; 1237 case BPF_W: 1238 /* mov dword ptr [rax + r12 + 1], imm32 */ 1239 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC7); 1240 break; 1241 case BPF_DW: 1242 /* mov qword ptr [rax + r12 + 1], imm32 */ 1243 EMIT2(add_3mod(0x48, dst_reg, 0, index_reg), 0xC7); 1244 break; 1245 } 1246 emit_insn_suffix_SIB(&prog, dst_reg, 0, index_reg, off); 1247 EMIT(imm, bpf_size_to_x86_bytes(size)); 1248 *pprog = prog; 1249 } 1250 1251 static void emit_st_r12(u8 **pprog, u32 size, u32 dst_reg, int off, int imm) 1252 { 1253 emit_st_index(pprog, size, dst_reg, X86_REG_R12, off, imm); 1254 } 1255 1256 static int emit_atomic_rmw(u8 **pprog, u32 atomic_op, 1257 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size) 1258 { 1259 u8 *prog = *pprog; 1260 1261 EMIT1(0xF0); /* lock prefix */ 1262 1263 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW); 1264 1265 /* emit opcode */ 1266 switch (atomic_op) { 1267 case BPF_ADD: 1268 case BPF_AND: 1269 case BPF_OR: 1270 case BPF_XOR: 1271 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */ 1272 EMIT1(simple_alu_opcodes[atomic_op]); 1273 break; 1274 case BPF_ADD | BPF_FETCH: 1275 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */ 1276 EMIT2(0x0F, 0xC1); 1277 break; 1278 case BPF_XCHG: 1279 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 1280 EMIT1(0x87); 1281 break; 1282 case BPF_CMPXCHG: 1283 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 1284 EMIT2(0x0F, 0xB1); 1285 break; 1286 default: 1287 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 1288 return -EFAULT; 1289 } 1290 1291 emit_insn_suffix(&prog, dst_reg, src_reg, off); 1292 1293 *pprog = prog; 1294 return 0; 1295 } 1296 1297 static int emit_atomic_rmw_index(u8 **pprog, u32 atomic_op, u32 size, 1298 u32 dst_reg, u32 src_reg, u32 index_reg, 1299 int off) 1300 { 1301 u8 *prog = *pprog; 1302 1303 EMIT1(0xF0); /* lock prefix */ 1304 switch (size) { 1305 case BPF_W: 1306 EMIT1(add_3mod(0x40, dst_reg, src_reg, index_reg)); 1307 break; 1308 case BPF_DW: 1309 EMIT1(add_3mod(0x48, dst_reg, src_reg, index_reg)); 1310 break; 1311 default: 1312 pr_err("bpf_jit: 1- and 2-byte RMW atomics are not supported\n"); 1313 return -EFAULT; 1314 } 1315 1316 /* emit opcode */ 1317 switch (atomic_op) { 1318 case BPF_ADD: 1319 case BPF_AND: 1320 case BPF_OR: 1321 case BPF_XOR: 1322 /* lock *(u32/u64*)(dst_reg + idx_reg + off) <op>= src_reg */ 1323 EMIT1(simple_alu_opcodes[atomic_op]); 1324 break; 1325 case BPF_ADD | BPF_FETCH: 1326 /* src_reg = atomic_fetch_add(dst_reg + idx_reg + off, src_reg); */ 1327 EMIT2(0x0F, 0xC1); 1328 break; 1329 case BPF_XCHG: 1330 /* src_reg = atomic_xchg(dst_reg + idx_reg + off, src_reg); */ 1331 EMIT1(0x87); 1332 break; 1333 case BPF_CMPXCHG: 1334 /* r0 = atomic_cmpxchg(dst_reg + idx_reg + off, r0, src_reg); */ 1335 EMIT2(0x0F, 0xB1); 1336 break; 1337 default: 1338 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 1339 return -EFAULT; 1340 } 1341 emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off); 1342 *pprog = prog; 1343 return 0; 1344 } 1345 1346 static int emit_atomic_ld_st(u8 **pprog, u32 atomic_op, u32 dst_reg, 1347 u32 src_reg, s16 off, u8 bpf_size) 1348 { 1349 switch (atomic_op) { 1350 case BPF_LOAD_ACQ: 1351 /* dst_reg = smp_load_acquire(src_reg + off16) */ 1352 emit_ldx(pprog, bpf_size, dst_reg, src_reg, off); 1353 break; 1354 case BPF_STORE_REL: 1355 /* smp_store_release(dst_reg + off16, src_reg) */ 1356 emit_stx(pprog, bpf_size, dst_reg, src_reg, off); 1357 break; 1358 default: 1359 pr_err("bpf_jit: unknown atomic load/store opcode %02x\n", 1360 atomic_op); 1361 return -EFAULT; 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int emit_atomic_ld_st_index(u8 **pprog, u32 atomic_op, u32 size, 1368 u32 dst_reg, u32 src_reg, u32 index_reg, 1369 int off) 1370 { 1371 switch (atomic_op) { 1372 case BPF_LOAD_ACQ: 1373 /* dst_reg = smp_load_acquire(src_reg + idx_reg + off16) */ 1374 emit_ldx_index(pprog, size, dst_reg, src_reg, index_reg, off); 1375 break; 1376 case BPF_STORE_REL: 1377 /* smp_store_release(dst_reg + idx_reg + off16, src_reg) */ 1378 emit_stx_index(pprog, size, dst_reg, src_reg, index_reg, off); 1379 break; 1380 default: 1381 pr_err("bpf_jit: unknown atomic load/store opcode %02x\n", 1382 atomic_op); 1383 return -EFAULT; 1384 } 1385 1386 return 0; 1387 } 1388 1389 #define DONT_CLEAR 1 1390 1391 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs) 1392 { 1393 u32 reg = x->fixup >> 8; 1394 1395 /* jump over faulting load and clear dest register */ 1396 if (reg != DONT_CLEAR) 1397 *(unsigned long *)((void *)regs + reg) = 0; 1398 regs->ip += x->fixup & 0xff; 1399 return true; 1400 } 1401 1402 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt, 1403 bool *regs_used) 1404 { 1405 int i; 1406 1407 for (i = 1; i <= insn_cnt; i++, insn++) { 1408 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) 1409 regs_used[0] = true; 1410 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) 1411 regs_used[1] = true; 1412 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) 1413 regs_used[2] = true; 1414 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) 1415 regs_used[3] = true; 1416 } 1417 } 1418 1419 /* emit the 3-byte VEX prefix 1420 * 1421 * r: same as rex.r, extra bit for ModRM reg field 1422 * x: same as rex.x, extra bit for SIB index field 1423 * b: same as rex.b, extra bit for ModRM r/m, or SIB base 1424 * m: opcode map select, encoding escape bytes e.g. 0x0f38 1425 * w: same as rex.w (32 bit or 64 bit) or opcode specific 1426 * src_reg2: additional source reg (encoded as BPF reg) 1427 * l: vector length (128 bit or 256 bit) or reserved 1428 * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3) 1429 */ 1430 static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m, 1431 bool w, u8 src_reg2, bool l, u8 pp) 1432 { 1433 u8 *prog = *pprog; 1434 const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */ 1435 u8 b1, b2; 1436 u8 vvvv = reg2hex[src_reg2]; 1437 1438 /* reg2hex gives only the lower 3 bit of vvvv */ 1439 if (is_ereg(src_reg2)) 1440 vvvv |= 1 << 3; 1441 1442 /* 1443 * 2nd byte of 3-byte VEX prefix 1444 * ~ means bit inverted encoding 1445 * 1446 * 7 0 1447 * +---+---+---+---+---+---+---+---+ 1448 * |~R |~X |~B | m | 1449 * +---+---+---+---+---+---+---+---+ 1450 */ 1451 b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f); 1452 /* 1453 * 3rd byte of 3-byte VEX prefix 1454 * 1455 * 7 0 1456 * +---+---+---+---+---+---+---+---+ 1457 * | W | ~vvvv | L | pp | 1458 * +---+---+---+---+---+---+---+---+ 1459 */ 1460 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3); 1461 1462 EMIT3(b0, b1, b2); 1463 *pprog = prog; 1464 } 1465 1466 /* emit BMI2 shift instruction */ 1467 static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op) 1468 { 1469 u8 *prog = *pprog; 1470 bool r = is_ereg(dst_reg); 1471 u8 m = 2; /* escape code 0f38 */ 1472 1473 emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op); 1474 EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg)); 1475 *pprog = prog; 1476 } 1477 1478 static void emit_priv_frame_ptr(u8 **pprog, void __percpu *priv_frame_ptr) 1479 { 1480 u8 *prog = *pprog; 1481 1482 /* movabs r9, priv_frame_ptr */ 1483 emit_mov_imm64(&prog, X86_REG_R9, (__force long) priv_frame_ptr >> 32, 1484 (u32) (__force long) priv_frame_ptr); 1485 1486 #ifdef CONFIG_SMP 1487 /* add <r9>, gs:[<off>] */ 1488 EMIT2(0x65, 0x4c); 1489 EMIT3(0x03, 0x0c, 0x25); 1490 EMIT((u32)(unsigned long)&this_cpu_off, 4); 1491 #endif 1492 1493 *pprog = prog; 1494 } 1495 1496 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp))) 1497 1498 #define __LOAD_TCC_PTR(off) \ 1499 EMIT3_off32(0x48, 0x8B, 0x85, off) 1500 /* mov rax, qword ptr [rbp - rounded_stack_depth - 16] */ 1501 #define LOAD_TAIL_CALL_CNT_PTR(stack) \ 1502 __LOAD_TCC_PTR(BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack)) 1503 1504 /* Memory size/value to protect private stack overflow/underflow */ 1505 #define PRIV_STACK_GUARD_SZ 8 1506 #define PRIV_STACK_GUARD_VAL 0xEB9F12345678eb9fULL 1507 1508 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image, 1509 int oldproglen, struct jit_context *ctx, bool jmp_padding) 1510 { 1511 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable; 1512 struct bpf_insn *insn = bpf_prog->insnsi; 1513 bool callee_regs_used[4] = {}; 1514 int insn_cnt = bpf_prog->len; 1515 bool seen_exit = false; 1516 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY]; 1517 void __percpu *priv_frame_ptr = NULL; 1518 u64 arena_vm_start, user_vm_start; 1519 void __percpu *priv_stack_ptr; 1520 int i, excnt = 0; 1521 int ilen, proglen = 0; 1522 u8 *prog = temp; 1523 u32 stack_depth; 1524 int err; 1525 1526 stack_depth = bpf_prog->aux->stack_depth; 1527 priv_stack_ptr = bpf_prog->aux->priv_stack_ptr; 1528 if (priv_stack_ptr) { 1529 priv_frame_ptr = priv_stack_ptr + PRIV_STACK_GUARD_SZ + round_up(stack_depth, 8); 1530 stack_depth = 0; 1531 } 1532 1533 arena_vm_start = bpf_arena_get_kern_vm_start(bpf_prog->aux->arena); 1534 user_vm_start = bpf_arena_get_user_vm_start(bpf_prog->aux->arena); 1535 1536 detect_reg_usage(insn, insn_cnt, callee_regs_used); 1537 1538 emit_prologue(&prog, image, stack_depth, 1539 bpf_prog_was_classic(bpf_prog), tail_call_reachable, 1540 bpf_is_subprog(bpf_prog), bpf_prog->aux->exception_cb); 1541 /* Exception callback will clobber callee regs for its own use, and 1542 * restore the original callee regs from main prog's stack frame. 1543 */ 1544 if (bpf_prog->aux->exception_boundary) { 1545 /* We also need to save r12, which is not mapped to any BPF 1546 * register, as we throw after entry into the kernel, which may 1547 * overwrite r12. 1548 */ 1549 push_r12(&prog); 1550 push_callee_regs(&prog, all_callee_regs_used); 1551 } else { 1552 if (arena_vm_start) 1553 push_r12(&prog); 1554 push_callee_regs(&prog, callee_regs_used); 1555 } 1556 if (arena_vm_start) 1557 emit_mov_imm64(&prog, X86_REG_R12, 1558 arena_vm_start >> 32, (u32) arena_vm_start); 1559 1560 if (priv_frame_ptr) 1561 emit_priv_frame_ptr(&prog, priv_frame_ptr); 1562 1563 ilen = prog - temp; 1564 if (rw_image) 1565 memcpy(rw_image + proglen, temp, ilen); 1566 proglen += ilen; 1567 addrs[0] = proglen; 1568 prog = temp; 1569 1570 for (i = 1; i <= insn_cnt; i++, insn++) { 1571 const s32 imm32 = insn->imm; 1572 u32 dst_reg = insn->dst_reg; 1573 u32 src_reg = insn->src_reg; 1574 u8 b2 = 0, b3 = 0; 1575 u8 *start_of_ldx; 1576 s64 jmp_offset; 1577 s16 insn_off; 1578 u8 jmp_cond; 1579 u8 *func; 1580 int nops; 1581 1582 if (priv_frame_ptr) { 1583 if (src_reg == BPF_REG_FP) 1584 src_reg = X86_REG_R9; 1585 1586 if (dst_reg == BPF_REG_FP) 1587 dst_reg = X86_REG_R9; 1588 } 1589 1590 switch (insn->code) { 1591 /* ALU */ 1592 case BPF_ALU | BPF_ADD | BPF_X: 1593 case BPF_ALU | BPF_SUB | BPF_X: 1594 case BPF_ALU | BPF_AND | BPF_X: 1595 case BPF_ALU | BPF_OR | BPF_X: 1596 case BPF_ALU | BPF_XOR | BPF_X: 1597 case BPF_ALU64 | BPF_ADD | BPF_X: 1598 case BPF_ALU64 | BPF_SUB | BPF_X: 1599 case BPF_ALU64 | BPF_AND | BPF_X: 1600 case BPF_ALU64 | BPF_OR | BPF_X: 1601 case BPF_ALU64 | BPF_XOR | BPF_X: 1602 maybe_emit_mod(&prog, dst_reg, src_reg, 1603 BPF_CLASS(insn->code) == BPF_ALU64); 1604 b2 = simple_alu_opcodes[BPF_OP(insn->code)]; 1605 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg)); 1606 break; 1607 1608 case BPF_ALU64 | BPF_MOV | BPF_X: 1609 if (insn_is_cast_user(insn)) { 1610 if (dst_reg != src_reg) 1611 /* 32-bit mov */ 1612 emit_mov_reg(&prog, false, dst_reg, src_reg); 1613 /* shl dst_reg, 32 */ 1614 maybe_emit_1mod(&prog, dst_reg, true); 1615 EMIT3(0xC1, add_1reg(0xE0, dst_reg), 32); 1616 1617 /* or dst_reg, user_vm_start */ 1618 maybe_emit_1mod(&prog, dst_reg, true); 1619 if (is_axreg(dst_reg)) 1620 EMIT1_off32(0x0D, user_vm_start >> 32); 1621 else 1622 EMIT2_off32(0x81, add_1reg(0xC8, dst_reg), user_vm_start >> 32); 1623 1624 /* rol dst_reg, 32 */ 1625 maybe_emit_1mod(&prog, dst_reg, true); 1626 EMIT3(0xC1, add_1reg(0xC0, dst_reg), 32); 1627 1628 /* xor r11, r11 */ 1629 EMIT3(0x4D, 0x31, 0xDB); 1630 1631 /* test dst_reg32, dst_reg32; check if lower 32-bit are zero */ 1632 maybe_emit_mod(&prog, dst_reg, dst_reg, false); 1633 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 1634 1635 /* cmove r11, dst_reg; if so, set dst_reg to zero */ 1636 /* WARNING: Intel swapped src/dst register encoding in CMOVcc !!! */ 1637 maybe_emit_mod(&prog, AUX_REG, dst_reg, true); 1638 EMIT3(0x0F, 0x44, add_2reg(0xC0, AUX_REG, dst_reg)); 1639 break; 1640 } else if (insn_is_mov_percpu_addr(insn)) { 1641 /* mov <dst>, <src> (if necessary) */ 1642 EMIT_mov(dst_reg, src_reg); 1643 #ifdef CONFIG_SMP 1644 /* add <dst>, gs:[<off>] */ 1645 EMIT2(0x65, add_1mod(0x48, dst_reg)); 1646 EMIT3(0x03, add_2reg(0x04, 0, dst_reg), 0x25); 1647 EMIT((u32)(unsigned long)&this_cpu_off, 4); 1648 #endif 1649 break; 1650 } 1651 fallthrough; 1652 case BPF_ALU | BPF_MOV | BPF_X: 1653 if (insn->off == 0) 1654 emit_mov_reg(&prog, 1655 BPF_CLASS(insn->code) == BPF_ALU64, 1656 dst_reg, src_reg); 1657 else 1658 emit_movsx_reg(&prog, insn->off, 1659 BPF_CLASS(insn->code) == BPF_ALU64, 1660 dst_reg, src_reg); 1661 break; 1662 1663 /* neg dst */ 1664 case BPF_ALU | BPF_NEG: 1665 case BPF_ALU64 | BPF_NEG: 1666 maybe_emit_1mod(&prog, dst_reg, 1667 BPF_CLASS(insn->code) == BPF_ALU64); 1668 EMIT2(0xF7, add_1reg(0xD8, dst_reg)); 1669 break; 1670 1671 case BPF_ALU | BPF_ADD | BPF_K: 1672 case BPF_ALU | BPF_SUB | BPF_K: 1673 case BPF_ALU | BPF_AND | BPF_K: 1674 case BPF_ALU | BPF_OR | BPF_K: 1675 case BPF_ALU | BPF_XOR | BPF_K: 1676 case BPF_ALU64 | BPF_ADD | BPF_K: 1677 case BPF_ALU64 | BPF_SUB | BPF_K: 1678 case BPF_ALU64 | BPF_AND | BPF_K: 1679 case BPF_ALU64 | BPF_OR | BPF_K: 1680 case BPF_ALU64 | BPF_XOR | BPF_K: 1681 maybe_emit_1mod(&prog, dst_reg, 1682 BPF_CLASS(insn->code) == BPF_ALU64); 1683 1684 /* 1685 * b3 holds 'normal' opcode, b2 short form only valid 1686 * in case dst is eax/rax. 1687 */ 1688 switch (BPF_OP(insn->code)) { 1689 case BPF_ADD: 1690 b3 = 0xC0; 1691 b2 = 0x05; 1692 break; 1693 case BPF_SUB: 1694 b3 = 0xE8; 1695 b2 = 0x2D; 1696 break; 1697 case BPF_AND: 1698 b3 = 0xE0; 1699 b2 = 0x25; 1700 break; 1701 case BPF_OR: 1702 b3 = 0xC8; 1703 b2 = 0x0D; 1704 break; 1705 case BPF_XOR: 1706 b3 = 0xF0; 1707 b2 = 0x35; 1708 break; 1709 } 1710 1711 if (is_imm8(imm32)) 1712 EMIT3(0x83, add_1reg(b3, dst_reg), imm32); 1713 else if (is_axreg(dst_reg)) 1714 EMIT1_off32(b2, imm32); 1715 else 1716 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32); 1717 break; 1718 1719 case BPF_ALU64 | BPF_MOV | BPF_K: 1720 case BPF_ALU | BPF_MOV | BPF_K: 1721 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64, 1722 dst_reg, imm32); 1723 break; 1724 1725 case BPF_LD | BPF_IMM | BPF_DW: 1726 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm); 1727 insn++; 1728 i++; 1729 break; 1730 1731 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */ 1732 case BPF_ALU | BPF_MOD | BPF_X: 1733 case BPF_ALU | BPF_DIV | BPF_X: 1734 case BPF_ALU | BPF_MOD | BPF_K: 1735 case BPF_ALU | BPF_DIV | BPF_K: 1736 case BPF_ALU64 | BPF_MOD | BPF_X: 1737 case BPF_ALU64 | BPF_DIV | BPF_X: 1738 case BPF_ALU64 | BPF_MOD | BPF_K: 1739 case BPF_ALU64 | BPF_DIV | BPF_K: { 1740 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64; 1741 1742 if (dst_reg != BPF_REG_0) 1743 EMIT1(0x50); /* push rax */ 1744 if (dst_reg != BPF_REG_3) 1745 EMIT1(0x52); /* push rdx */ 1746 1747 if (BPF_SRC(insn->code) == BPF_X) { 1748 if (src_reg == BPF_REG_0 || 1749 src_reg == BPF_REG_3) { 1750 /* mov r11, src_reg */ 1751 EMIT_mov(AUX_REG, src_reg); 1752 src_reg = AUX_REG; 1753 } 1754 } else { 1755 /* mov r11, imm32 */ 1756 EMIT3_off32(0x49, 0xC7, 0xC3, imm32); 1757 src_reg = AUX_REG; 1758 } 1759 1760 if (dst_reg != BPF_REG_0) 1761 /* mov rax, dst_reg */ 1762 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg); 1763 1764 if (insn->off == 0) { 1765 /* 1766 * xor edx, edx 1767 * equivalent to 'xor rdx, rdx', but one byte less 1768 */ 1769 EMIT2(0x31, 0xd2); 1770 1771 /* div src_reg */ 1772 maybe_emit_1mod(&prog, src_reg, is64); 1773 EMIT2(0xF7, add_1reg(0xF0, src_reg)); 1774 } else { 1775 if (BPF_CLASS(insn->code) == BPF_ALU) 1776 EMIT1(0x99); /* cdq */ 1777 else 1778 EMIT2(0x48, 0x99); /* cqo */ 1779 1780 /* idiv src_reg */ 1781 maybe_emit_1mod(&prog, src_reg, is64); 1782 EMIT2(0xF7, add_1reg(0xF8, src_reg)); 1783 } 1784 1785 if (BPF_OP(insn->code) == BPF_MOD && 1786 dst_reg != BPF_REG_3) 1787 /* mov dst_reg, rdx */ 1788 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3); 1789 else if (BPF_OP(insn->code) == BPF_DIV && 1790 dst_reg != BPF_REG_0) 1791 /* mov dst_reg, rax */ 1792 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0); 1793 1794 if (dst_reg != BPF_REG_3) 1795 EMIT1(0x5A); /* pop rdx */ 1796 if (dst_reg != BPF_REG_0) 1797 EMIT1(0x58); /* pop rax */ 1798 break; 1799 } 1800 1801 case BPF_ALU | BPF_MUL | BPF_K: 1802 case BPF_ALU64 | BPF_MUL | BPF_K: 1803 maybe_emit_mod(&prog, dst_reg, dst_reg, 1804 BPF_CLASS(insn->code) == BPF_ALU64); 1805 1806 if (is_imm8(imm32)) 1807 /* imul dst_reg, dst_reg, imm8 */ 1808 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg), 1809 imm32); 1810 else 1811 /* imul dst_reg, dst_reg, imm32 */ 1812 EMIT2_off32(0x69, 1813 add_2reg(0xC0, dst_reg, dst_reg), 1814 imm32); 1815 break; 1816 1817 case BPF_ALU | BPF_MUL | BPF_X: 1818 case BPF_ALU64 | BPF_MUL | BPF_X: 1819 maybe_emit_mod(&prog, src_reg, dst_reg, 1820 BPF_CLASS(insn->code) == BPF_ALU64); 1821 1822 /* imul dst_reg, src_reg */ 1823 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg)); 1824 break; 1825 1826 /* Shifts */ 1827 case BPF_ALU | BPF_LSH | BPF_K: 1828 case BPF_ALU | BPF_RSH | BPF_K: 1829 case BPF_ALU | BPF_ARSH | BPF_K: 1830 case BPF_ALU64 | BPF_LSH | BPF_K: 1831 case BPF_ALU64 | BPF_RSH | BPF_K: 1832 case BPF_ALU64 | BPF_ARSH | BPF_K: 1833 maybe_emit_1mod(&prog, dst_reg, 1834 BPF_CLASS(insn->code) == BPF_ALU64); 1835 1836 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1837 if (imm32 == 1) 1838 EMIT2(0xD1, add_1reg(b3, dst_reg)); 1839 else 1840 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32); 1841 break; 1842 1843 case BPF_ALU | BPF_LSH | BPF_X: 1844 case BPF_ALU | BPF_RSH | BPF_X: 1845 case BPF_ALU | BPF_ARSH | BPF_X: 1846 case BPF_ALU64 | BPF_LSH | BPF_X: 1847 case BPF_ALU64 | BPF_RSH | BPF_X: 1848 case BPF_ALU64 | BPF_ARSH | BPF_X: 1849 /* BMI2 shifts aren't better when shift count is already in rcx */ 1850 if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) { 1851 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */ 1852 bool w = (BPF_CLASS(insn->code) == BPF_ALU64); 1853 u8 op; 1854 1855 switch (BPF_OP(insn->code)) { 1856 case BPF_LSH: 1857 op = 1; /* prefix 0x66 */ 1858 break; 1859 case BPF_RSH: 1860 op = 3; /* prefix 0xf2 */ 1861 break; 1862 case BPF_ARSH: 1863 op = 2; /* prefix 0xf3 */ 1864 break; 1865 } 1866 1867 emit_shiftx(&prog, dst_reg, src_reg, w, op); 1868 1869 break; 1870 } 1871 1872 if (src_reg != BPF_REG_4) { /* common case */ 1873 /* Check for bad case when dst_reg == rcx */ 1874 if (dst_reg == BPF_REG_4) { 1875 /* mov r11, dst_reg */ 1876 EMIT_mov(AUX_REG, dst_reg); 1877 dst_reg = AUX_REG; 1878 } else { 1879 EMIT1(0x51); /* push rcx */ 1880 } 1881 /* mov rcx, src_reg */ 1882 EMIT_mov(BPF_REG_4, src_reg); 1883 } 1884 1885 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */ 1886 maybe_emit_1mod(&prog, dst_reg, 1887 BPF_CLASS(insn->code) == BPF_ALU64); 1888 1889 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1890 EMIT2(0xD3, add_1reg(b3, dst_reg)); 1891 1892 if (src_reg != BPF_REG_4) { 1893 if (insn->dst_reg == BPF_REG_4) 1894 /* mov dst_reg, r11 */ 1895 EMIT_mov(insn->dst_reg, AUX_REG); 1896 else 1897 EMIT1(0x59); /* pop rcx */ 1898 } 1899 1900 break; 1901 1902 case BPF_ALU | BPF_END | BPF_FROM_BE: 1903 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1904 switch (imm32) { 1905 case 16: 1906 /* Emit 'ror %ax, 8' to swap lower 2 bytes */ 1907 EMIT1(0x66); 1908 if (is_ereg(dst_reg)) 1909 EMIT1(0x41); 1910 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8); 1911 1912 /* Emit 'movzwl eax, ax' */ 1913 if (is_ereg(dst_reg)) 1914 EMIT3(0x45, 0x0F, 0xB7); 1915 else 1916 EMIT2(0x0F, 0xB7); 1917 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 1918 break; 1919 case 32: 1920 /* Emit 'bswap eax' to swap lower 4 bytes */ 1921 if (is_ereg(dst_reg)) 1922 EMIT2(0x41, 0x0F); 1923 else 1924 EMIT1(0x0F); 1925 EMIT1(add_1reg(0xC8, dst_reg)); 1926 break; 1927 case 64: 1928 /* Emit 'bswap rax' to swap 8 bytes */ 1929 EMIT3(add_1mod(0x48, dst_reg), 0x0F, 1930 add_1reg(0xC8, dst_reg)); 1931 break; 1932 } 1933 break; 1934 1935 case BPF_ALU | BPF_END | BPF_FROM_LE: 1936 switch (imm32) { 1937 case 16: 1938 /* 1939 * Emit 'movzwl eax, ax' to zero extend 16-bit 1940 * into 64 bit 1941 */ 1942 if (is_ereg(dst_reg)) 1943 EMIT3(0x45, 0x0F, 0xB7); 1944 else 1945 EMIT2(0x0F, 0xB7); 1946 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 1947 break; 1948 case 32: 1949 /* Emit 'mov eax, eax' to clear upper 32-bits */ 1950 if (is_ereg(dst_reg)) 1951 EMIT1(0x45); 1952 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg)); 1953 break; 1954 case 64: 1955 /* nop */ 1956 break; 1957 } 1958 break; 1959 1960 /* speculation barrier */ 1961 case BPF_ST | BPF_NOSPEC: 1962 EMIT_LFENCE(); 1963 break; 1964 1965 /* ST: *(u8*)(dst_reg + off) = imm */ 1966 case BPF_ST | BPF_MEM | BPF_B: 1967 if (is_ereg(dst_reg)) 1968 EMIT2(0x41, 0xC6); 1969 else 1970 EMIT1(0xC6); 1971 goto st; 1972 case BPF_ST | BPF_MEM | BPF_H: 1973 if (is_ereg(dst_reg)) 1974 EMIT3(0x66, 0x41, 0xC7); 1975 else 1976 EMIT2(0x66, 0xC7); 1977 goto st; 1978 case BPF_ST | BPF_MEM | BPF_W: 1979 if (is_ereg(dst_reg)) 1980 EMIT2(0x41, 0xC7); 1981 else 1982 EMIT1(0xC7); 1983 goto st; 1984 case BPF_ST | BPF_MEM | BPF_DW: 1985 EMIT2(add_1mod(0x48, dst_reg), 0xC7); 1986 1987 st: if (is_imm8(insn->off)) 1988 EMIT2(add_1reg(0x40, dst_reg), insn->off); 1989 else 1990 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off); 1991 1992 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code))); 1993 break; 1994 1995 /* STX: *(u8*)(dst_reg + off) = src_reg */ 1996 case BPF_STX | BPF_MEM | BPF_B: 1997 case BPF_STX | BPF_MEM | BPF_H: 1998 case BPF_STX | BPF_MEM | BPF_W: 1999 case BPF_STX | BPF_MEM | BPF_DW: 2000 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2001 break; 2002 2003 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 2004 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 2005 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 2006 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 2007 start_of_ldx = prog; 2008 emit_st_r12(&prog, BPF_SIZE(insn->code), dst_reg, insn->off, insn->imm); 2009 goto populate_extable; 2010 2011 /* LDX: dst_reg = *(u8*)(src_reg + r12 + off) */ 2012 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 2013 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 2014 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 2015 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 2016 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 2017 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 2018 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 2019 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 2020 start_of_ldx = prog; 2021 if (BPF_CLASS(insn->code) == BPF_LDX) 2022 emit_ldx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2023 else 2024 emit_stx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2025 populate_extable: 2026 { 2027 struct exception_table_entry *ex; 2028 u8 *_insn = image + proglen + (start_of_ldx - temp); 2029 s64 delta; 2030 2031 if (!bpf_prog->aux->extable) 2032 break; 2033 2034 if (excnt >= bpf_prog->aux->num_exentries) { 2035 pr_err("mem32 extable bug\n"); 2036 return -EFAULT; 2037 } 2038 ex = &bpf_prog->aux->extable[excnt++]; 2039 2040 delta = _insn - (u8 *)&ex->insn; 2041 /* switch ex to rw buffer for writes */ 2042 ex = (void *)rw_image + ((void *)ex - (void *)image); 2043 2044 ex->insn = delta; 2045 2046 ex->data = EX_TYPE_BPF; 2047 2048 ex->fixup = (prog - start_of_ldx) | 2049 ((BPF_CLASS(insn->code) == BPF_LDX ? reg2pt_regs[dst_reg] : DONT_CLEAR) << 8); 2050 } 2051 break; 2052 2053 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 2054 case BPF_LDX | BPF_MEM | BPF_B: 2055 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 2056 case BPF_LDX | BPF_MEM | BPF_H: 2057 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 2058 case BPF_LDX | BPF_MEM | BPF_W: 2059 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 2060 case BPF_LDX | BPF_MEM | BPF_DW: 2061 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 2062 /* LDXS: dst_reg = *(s8*)(src_reg + off) */ 2063 case BPF_LDX | BPF_MEMSX | BPF_B: 2064 case BPF_LDX | BPF_MEMSX | BPF_H: 2065 case BPF_LDX | BPF_MEMSX | BPF_W: 2066 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 2067 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 2068 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 2069 insn_off = insn->off; 2070 2071 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 2072 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 2073 /* Conservatively check that src_reg + insn->off is a kernel address: 2074 * src_reg + insn->off > TASK_SIZE_MAX + PAGE_SIZE 2075 * and 2076 * src_reg + insn->off < VSYSCALL_ADDR 2077 */ 2078 2079 u64 limit = TASK_SIZE_MAX + PAGE_SIZE - VSYSCALL_ADDR; 2080 u8 *end_of_jmp; 2081 2082 /* movabsq r10, VSYSCALL_ADDR */ 2083 emit_mov_imm64(&prog, BPF_REG_AX, (long)VSYSCALL_ADDR >> 32, 2084 (u32)(long)VSYSCALL_ADDR); 2085 2086 /* mov src_reg, r11 */ 2087 EMIT_mov(AUX_REG, src_reg); 2088 2089 if (insn->off) { 2090 /* add r11, insn->off */ 2091 maybe_emit_1mod(&prog, AUX_REG, true); 2092 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off); 2093 } 2094 2095 /* sub r11, r10 */ 2096 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true); 2097 EMIT2(0x29, add_2reg(0xC0, AUX_REG, BPF_REG_AX)); 2098 2099 /* movabsq r10, limit */ 2100 emit_mov_imm64(&prog, BPF_REG_AX, (long)limit >> 32, 2101 (u32)(long)limit); 2102 2103 /* cmp r10, r11 */ 2104 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true); 2105 EMIT2(0x39, add_2reg(0xC0, AUX_REG, BPF_REG_AX)); 2106 2107 /* if unsigned '>', goto load */ 2108 EMIT2(X86_JA, 0); 2109 end_of_jmp = prog; 2110 2111 /* xor dst_reg, dst_reg */ 2112 emit_mov_imm32(&prog, false, dst_reg, 0); 2113 /* jmp byte_after_ldx */ 2114 EMIT2(0xEB, 0); 2115 2116 /* populate jmp_offset for JAE above to jump to start_of_ldx */ 2117 start_of_ldx = prog; 2118 end_of_jmp[-1] = start_of_ldx - end_of_jmp; 2119 } 2120 if (BPF_MODE(insn->code) == BPF_PROBE_MEMSX || 2121 BPF_MODE(insn->code) == BPF_MEMSX) 2122 emit_ldsx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 2123 else 2124 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 2125 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 2126 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 2127 struct exception_table_entry *ex; 2128 u8 *_insn = image + proglen + (start_of_ldx - temp); 2129 s64 delta; 2130 2131 /* populate jmp_offset for JMP above */ 2132 start_of_ldx[-1] = prog - start_of_ldx; 2133 2134 if (!bpf_prog->aux->extable) 2135 break; 2136 2137 if (excnt >= bpf_prog->aux->num_exentries) { 2138 pr_err("ex gen bug\n"); 2139 return -EFAULT; 2140 } 2141 ex = &bpf_prog->aux->extable[excnt++]; 2142 2143 delta = _insn - (u8 *)&ex->insn; 2144 if (!is_simm32(delta)) { 2145 pr_err("extable->insn doesn't fit into 32-bit\n"); 2146 return -EFAULT; 2147 } 2148 /* switch ex to rw buffer for writes */ 2149 ex = (void *)rw_image + ((void *)ex - (void *)image); 2150 2151 ex->insn = delta; 2152 2153 ex->data = EX_TYPE_BPF; 2154 2155 if (dst_reg > BPF_REG_9) { 2156 pr_err("verifier error\n"); 2157 return -EFAULT; 2158 } 2159 /* 2160 * Compute size of x86 insn and its target dest x86 register. 2161 * ex_handler_bpf() will use lower 8 bits to adjust 2162 * pt_regs->ip to jump over this x86 instruction 2163 * and upper bits to figure out which pt_regs to zero out. 2164 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]" 2165 * of 4 bytes will be ignored and rbx will be zero inited. 2166 */ 2167 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8); 2168 } 2169 break; 2170 2171 case BPF_STX | BPF_ATOMIC | BPF_B: 2172 case BPF_STX | BPF_ATOMIC | BPF_H: 2173 if (!bpf_atomic_is_load_store(insn)) { 2174 pr_err("bpf_jit: 1- and 2-byte RMW atomics are not supported\n"); 2175 return -EFAULT; 2176 } 2177 fallthrough; 2178 case BPF_STX | BPF_ATOMIC | BPF_W: 2179 case BPF_STX | BPF_ATOMIC | BPF_DW: 2180 if (insn->imm == (BPF_AND | BPF_FETCH) || 2181 insn->imm == (BPF_OR | BPF_FETCH) || 2182 insn->imm == (BPF_XOR | BPF_FETCH)) { 2183 bool is64 = BPF_SIZE(insn->code) == BPF_DW; 2184 u32 real_src_reg = src_reg; 2185 u32 real_dst_reg = dst_reg; 2186 u8 *branch_target; 2187 2188 /* 2189 * Can't be implemented with a single x86 insn. 2190 * Need to do a CMPXCHG loop. 2191 */ 2192 2193 /* Will need RAX as a CMPXCHG operand so save R0 */ 2194 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0); 2195 if (src_reg == BPF_REG_0) 2196 real_src_reg = BPF_REG_AX; 2197 if (dst_reg == BPF_REG_0) 2198 real_dst_reg = BPF_REG_AX; 2199 2200 branch_target = prog; 2201 /* Load old value */ 2202 emit_ldx(&prog, BPF_SIZE(insn->code), 2203 BPF_REG_0, real_dst_reg, insn->off); 2204 /* 2205 * Perform the (commutative) operation locally, 2206 * put the result in the AUX_REG. 2207 */ 2208 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0); 2209 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64); 2210 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)], 2211 add_2reg(0xC0, AUX_REG, real_src_reg)); 2212 /* Attempt to swap in new value */ 2213 err = emit_atomic_rmw(&prog, BPF_CMPXCHG, 2214 real_dst_reg, AUX_REG, 2215 insn->off, 2216 BPF_SIZE(insn->code)); 2217 if (WARN_ON(err)) 2218 return err; 2219 /* 2220 * ZF tells us whether we won the race. If it's 2221 * cleared we need to try again. 2222 */ 2223 EMIT2(X86_JNE, -(prog - branch_target) - 2); 2224 /* Return the pre-modification value */ 2225 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0); 2226 /* Restore R0 after clobbering RAX */ 2227 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX); 2228 break; 2229 } 2230 2231 if (bpf_atomic_is_load_store(insn)) 2232 err = emit_atomic_ld_st(&prog, insn->imm, dst_reg, src_reg, 2233 insn->off, BPF_SIZE(insn->code)); 2234 else 2235 err = emit_atomic_rmw(&prog, insn->imm, dst_reg, src_reg, 2236 insn->off, BPF_SIZE(insn->code)); 2237 if (err) 2238 return err; 2239 break; 2240 2241 case BPF_STX | BPF_PROBE_ATOMIC | BPF_B: 2242 case BPF_STX | BPF_PROBE_ATOMIC | BPF_H: 2243 if (!bpf_atomic_is_load_store(insn)) { 2244 pr_err("bpf_jit: 1- and 2-byte RMW atomics are not supported\n"); 2245 return -EFAULT; 2246 } 2247 fallthrough; 2248 case BPF_STX | BPF_PROBE_ATOMIC | BPF_W: 2249 case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW: 2250 start_of_ldx = prog; 2251 2252 if (bpf_atomic_is_load_store(insn)) 2253 err = emit_atomic_ld_st_index(&prog, insn->imm, 2254 BPF_SIZE(insn->code), dst_reg, 2255 src_reg, X86_REG_R12, insn->off); 2256 else 2257 err = emit_atomic_rmw_index(&prog, insn->imm, BPF_SIZE(insn->code), 2258 dst_reg, src_reg, X86_REG_R12, 2259 insn->off); 2260 if (err) 2261 return err; 2262 goto populate_extable; 2263 2264 /* call */ 2265 case BPF_JMP | BPF_CALL: { 2266 u8 *ip = image + addrs[i - 1]; 2267 2268 func = (u8 *) __bpf_call_base + imm32; 2269 if (src_reg == BPF_PSEUDO_CALL && tail_call_reachable) { 2270 LOAD_TAIL_CALL_CNT_PTR(stack_depth); 2271 ip += 7; 2272 } 2273 if (!imm32) 2274 return -EINVAL; 2275 if (priv_frame_ptr) { 2276 push_r9(&prog); 2277 ip += 2; 2278 } 2279 ip += x86_call_depth_emit_accounting(&prog, func, ip); 2280 if (emit_call(&prog, func, ip)) 2281 return -EINVAL; 2282 if (priv_frame_ptr) 2283 pop_r9(&prog); 2284 break; 2285 } 2286 2287 case BPF_JMP | BPF_TAIL_CALL: 2288 if (imm32) 2289 emit_bpf_tail_call_direct(bpf_prog, 2290 &bpf_prog->aux->poke_tab[imm32 - 1], 2291 &prog, image + addrs[i - 1], 2292 callee_regs_used, 2293 stack_depth, 2294 ctx); 2295 else 2296 emit_bpf_tail_call_indirect(bpf_prog, 2297 &prog, 2298 callee_regs_used, 2299 stack_depth, 2300 image + addrs[i - 1], 2301 ctx); 2302 break; 2303 2304 /* cond jump */ 2305 case BPF_JMP | BPF_JEQ | BPF_X: 2306 case BPF_JMP | BPF_JNE | BPF_X: 2307 case BPF_JMP | BPF_JGT | BPF_X: 2308 case BPF_JMP | BPF_JLT | BPF_X: 2309 case BPF_JMP | BPF_JGE | BPF_X: 2310 case BPF_JMP | BPF_JLE | BPF_X: 2311 case BPF_JMP | BPF_JSGT | BPF_X: 2312 case BPF_JMP | BPF_JSLT | BPF_X: 2313 case BPF_JMP | BPF_JSGE | BPF_X: 2314 case BPF_JMP | BPF_JSLE | BPF_X: 2315 case BPF_JMP32 | BPF_JEQ | BPF_X: 2316 case BPF_JMP32 | BPF_JNE | BPF_X: 2317 case BPF_JMP32 | BPF_JGT | BPF_X: 2318 case BPF_JMP32 | BPF_JLT | BPF_X: 2319 case BPF_JMP32 | BPF_JGE | BPF_X: 2320 case BPF_JMP32 | BPF_JLE | BPF_X: 2321 case BPF_JMP32 | BPF_JSGT | BPF_X: 2322 case BPF_JMP32 | BPF_JSLT | BPF_X: 2323 case BPF_JMP32 | BPF_JSGE | BPF_X: 2324 case BPF_JMP32 | BPF_JSLE | BPF_X: 2325 /* cmp dst_reg, src_reg */ 2326 maybe_emit_mod(&prog, dst_reg, src_reg, 2327 BPF_CLASS(insn->code) == BPF_JMP); 2328 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg)); 2329 goto emit_cond_jmp; 2330 2331 case BPF_JMP | BPF_JSET | BPF_X: 2332 case BPF_JMP32 | BPF_JSET | BPF_X: 2333 /* test dst_reg, src_reg */ 2334 maybe_emit_mod(&prog, dst_reg, src_reg, 2335 BPF_CLASS(insn->code) == BPF_JMP); 2336 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg)); 2337 goto emit_cond_jmp; 2338 2339 case BPF_JMP | BPF_JSET | BPF_K: 2340 case BPF_JMP32 | BPF_JSET | BPF_K: 2341 /* test dst_reg, imm32 */ 2342 maybe_emit_1mod(&prog, dst_reg, 2343 BPF_CLASS(insn->code) == BPF_JMP); 2344 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32); 2345 goto emit_cond_jmp; 2346 2347 case BPF_JMP | BPF_JEQ | BPF_K: 2348 case BPF_JMP | BPF_JNE | BPF_K: 2349 case BPF_JMP | BPF_JGT | BPF_K: 2350 case BPF_JMP | BPF_JLT | BPF_K: 2351 case BPF_JMP | BPF_JGE | BPF_K: 2352 case BPF_JMP | BPF_JLE | BPF_K: 2353 case BPF_JMP | BPF_JSGT | BPF_K: 2354 case BPF_JMP | BPF_JSLT | BPF_K: 2355 case BPF_JMP | BPF_JSGE | BPF_K: 2356 case BPF_JMP | BPF_JSLE | BPF_K: 2357 case BPF_JMP32 | BPF_JEQ | BPF_K: 2358 case BPF_JMP32 | BPF_JNE | BPF_K: 2359 case BPF_JMP32 | BPF_JGT | BPF_K: 2360 case BPF_JMP32 | BPF_JLT | BPF_K: 2361 case BPF_JMP32 | BPF_JGE | BPF_K: 2362 case BPF_JMP32 | BPF_JLE | BPF_K: 2363 case BPF_JMP32 | BPF_JSGT | BPF_K: 2364 case BPF_JMP32 | BPF_JSLT | BPF_K: 2365 case BPF_JMP32 | BPF_JSGE | BPF_K: 2366 case BPF_JMP32 | BPF_JSLE | BPF_K: 2367 /* test dst_reg, dst_reg to save one extra byte */ 2368 if (imm32 == 0) { 2369 maybe_emit_mod(&prog, dst_reg, dst_reg, 2370 BPF_CLASS(insn->code) == BPF_JMP); 2371 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 2372 goto emit_cond_jmp; 2373 } 2374 2375 /* cmp dst_reg, imm8/32 */ 2376 maybe_emit_1mod(&prog, dst_reg, 2377 BPF_CLASS(insn->code) == BPF_JMP); 2378 2379 if (is_imm8(imm32)) 2380 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32); 2381 else 2382 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32); 2383 2384 emit_cond_jmp: /* Convert BPF opcode to x86 */ 2385 switch (BPF_OP(insn->code)) { 2386 case BPF_JEQ: 2387 jmp_cond = X86_JE; 2388 break; 2389 case BPF_JSET: 2390 case BPF_JNE: 2391 jmp_cond = X86_JNE; 2392 break; 2393 case BPF_JGT: 2394 /* GT is unsigned '>', JA in x86 */ 2395 jmp_cond = X86_JA; 2396 break; 2397 case BPF_JLT: 2398 /* LT is unsigned '<', JB in x86 */ 2399 jmp_cond = X86_JB; 2400 break; 2401 case BPF_JGE: 2402 /* GE is unsigned '>=', JAE in x86 */ 2403 jmp_cond = X86_JAE; 2404 break; 2405 case BPF_JLE: 2406 /* LE is unsigned '<=', JBE in x86 */ 2407 jmp_cond = X86_JBE; 2408 break; 2409 case BPF_JSGT: 2410 /* Signed '>', GT in x86 */ 2411 jmp_cond = X86_JG; 2412 break; 2413 case BPF_JSLT: 2414 /* Signed '<', LT in x86 */ 2415 jmp_cond = X86_JL; 2416 break; 2417 case BPF_JSGE: 2418 /* Signed '>=', GE in x86 */ 2419 jmp_cond = X86_JGE; 2420 break; 2421 case BPF_JSLE: 2422 /* Signed '<=', LE in x86 */ 2423 jmp_cond = X86_JLE; 2424 break; 2425 default: /* to silence GCC warning */ 2426 return -EFAULT; 2427 } 2428 jmp_offset = addrs[i + insn->off] - addrs[i]; 2429 if (is_imm8_jmp_offset(jmp_offset)) { 2430 if (jmp_padding) { 2431 /* To keep the jmp_offset valid, the extra bytes are 2432 * padded before the jump insn, so we subtract the 2433 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF. 2434 * 2435 * If the previous pass already emits an imm8 2436 * jmp_cond, then this BPF insn won't shrink, so 2437 * "nops" is 0. 2438 * 2439 * On the other hand, if the previous pass emits an 2440 * imm32 jmp_cond, the extra 4 bytes(*) is padded to 2441 * keep the image from shrinking further. 2442 * 2443 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond 2444 * is 2 bytes, so the size difference is 4 bytes. 2445 */ 2446 nops = INSN_SZ_DIFF - 2; 2447 if (nops != 0 && nops != 4) { 2448 pr_err("unexpected jmp_cond padding: %d bytes\n", 2449 nops); 2450 return -EFAULT; 2451 } 2452 emit_nops(&prog, nops); 2453 } 2454 EMIT2(jmp_cond, jmp_offset); 2455 } else if (is_simm32(jmp_offset)) { 2456 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset); 2457 } else { 2458 pr_err("cond_jmp gen bug %llx\n", jmp_offset); 2459 return -EFAULT; 2460 } 2461 2462 break; 2463 2464 case BPF_JMP | BPF_JA: 2465 case BPF_JMP32 | BPF_JA: 2466 if (BPF_CLASS(insn->code) == BPF_JMP) { 2467 if (insn->off == -1) 2468 /* -1 jmp instructions will always jump 2469 * backwards two bytes. Explicitly handling 2470 * this case avoids wasting too many passes 2471 * when there are long sequences of replaced 2472 * dead code. 2473 */ 2474 jmp_offset = -2; 2475 else 2476 jmp_offset = addrs[i + insn->off] - addrs[i]; 2477 } else { 2478 if (insn->imm == -1) 2479 jmp_offset = -2; 2480 else 2481 jmp_offset = addrs[i + insn->imm] - addrs[i]; 2482 } 2483 2484 if (!jmp_offset) { 2485 /* 2486 * If jmp_padding is enabled, the extra nops will 2487 * be inserted. Otherwise, optimize out nop jumps. 2488 */ 2489 if (jmp_padding) { 2490 /* There are 3 possible conditions. 2491 * (1) This BPF_JA is already optimized out in 2492 * the previous run, so there is no need 2493 * to pad any extra byte (0 byte). 2494 * (2) The previous pass emits an imm8 jmp, 2495 * so we pad 2 bytes to match the previous 2496 * insn size. 2497 * (3) Similarly, the previous pass emits an 2498 * imm32 jmp, and 5 bytes is padded. 2499 */ 2500 nops = INSN_SZ_DIFF; 2501 if (nops != 0 && nops != 2 && nops != 5) { 2502 pr_err("unexpected nop jump padding: %d bytes\n", 2503 nops); 2504 return -EFAULT; 2505 } 2506 emit_nops(&prog, nops); 2507 } 2508 break; 2509 } 2510 emit_jmp: 2511 if (is_imm8_jmp_offset(jmp_offset)) { 2512 if (jmp_padding) { 2513 /* To avoid breaking jmp_offset, the extra bytes 2514 * are padded before the actual jmp insn, so 2515 * 2 bytes is subtracted from INSN_SZ_DIFF. 2516 * 2517 * If the previous pass already emits an imm8 2518 * jmp, there is nothing to pad (0 byte). 2519 * 2520 * If it emits an imm32 jmp (5 bytes) previously 2521 * and now an imm8 jmp (2 bytes), then we pad 2522 * (5 - 2 = 3) bytes to stop the image from 2523 * shrinking further. 2524 */ 2525 nops = INSN_SZ_DIFF - 2; 2526 if (nops != 0 && nops != 3) { 2527 pr_err("unexpected jump padding: %d bytes\n", 2528 nops); 2529 return -EFAULT; 2530 } 2531 emit_nops(&prog, INSN_SZ_DIFF - 2); 2532 } 2533 EMIT2(0xEB, jmp_offset); 2534 } else if (is_simm32(jmp_offset)) { 2535 EMIT1_off32(0xE9, jmp_offset); 2536 } else { 2537 pr_err("jmp gen bug %llx\n", jmp_offset); 2538 return -EFAULT; 2539 } 2540 break; 2541 2542 case BPF_JMP | BPF_EXIT: 2543 if (seen_exit) { 2544 jmp_offset = ctx->cleanup_addr - addrs[i]; 2545 goto emit_jmp; 2546 } 2547 seen_exit = true; 2548 /* Update cleanup_addr */ 2549 ctx->cleanup_addr = proglen; 2550 if (bpf_prog->aux->exception_boundary) { 2551 pop_callee_regs(&prog, all_callee_regs_used); 2552 pop_r12(&prog); 2553 } else { 2554 pop_callee_regs(&prog, callee_regs_used); 2555 if (arena_vm_start) 2556 pop_r12(&prog); 2557 } 2558 EMIT1(0xC9); /* leave */ 2559 emit_return(&prog, image + addrs[i - 1] + (prog - temp)); 2560 break; 2561 2562 default: 2563 /* 2564 * By design x86-64 JIT should support all BPF instructions. 2565 * This error will be seen if new instruction was added 2566 * to the interpreter, but not to the JIT, or if there is 2567 * junk in bpf_prog. 2568 */ 2569 pr_err("bpf_jit: unknown opcode %02x\n", insn->code); 2570 return -EINVAL; 2571 } 2572 2573 ilen = prog - temp; 2574 if (ilen > BPF_MAX_INSN_SIZE) { 2575 pr_err("bpf_jit: fatal insn size error\n"); 2576 return -EFAULT; 2577 } 2578 2579 if (image) { 2580 /* 2581 * When populating the image, assert that: 2582 * 2583 * i) We do not write beyond the allocated space, and 2584 * ii) addrs[i] did not change from the prior run, in order 2585 * to validate assumptions made for computing branch 2586 * displacements. 2587 */ 2588 if (unlikely(proglen + ilen > oldproglen || 2589 proglen + ilen != addrs[i])) { 2590 pr_err("bpf_jit: fatal error\n"); 2591 return -EFAULT; 2592 } 2593 memcpy(rw_image + proglen, temp, ilen); 2594 } 2595 proglen += ilen; 2596 addrs[i] = proglen; 2597 prog = temp; 2598 } 2599 2600 if (image && excnt != bpf_prog->aux->num_exentries) { 2601 pr_err("extable is not populated\n"); 2602 return -EFAULT; 2603 } 2604 return proglen; 2605 } 2606 2607 static void clean_stack_garbage(const struct btf_func_model *m, 2608 u8 **pprog, int nr_stack_slots, 2609 int stack_size) 2610 { 2611 int arg_size, off; 2612 u8 *prog; 2613 2614 /* Generally speaking, the compiler will pass the arguments 2615 * on-stack with "push" instruction, which will take 8-byte 2616 * on the stack. In this case, there won't be garbage values 2617 * while we copy the arguments from origin stack frame to current 2618 * in BPF_DW. 2619 * 2620 * However, sometimes the compiler will only allocate 4-byte on 2621 * the stack for the arguments. For now, this case will only 2622 * happen if there is only one argument on-stack and its size 2623 * not more than 4 byte. In this case, there will be garbage 2624 * values on the upper 4-byte where we store the argument on 2625 * current stack frame. 2626 * 2627 * arguments on origin stack: 2628 * 2629 * stack_arg_1(4-byte) xxx(4-byte) 2630 * 2631 * what we copy: 2632 * 2633 * stack_arg_1(8-byte): stack_arg_1(origin) xxx 2634 * 2635 * and the xxx is the garbage values which we should clean here. 2636 */ 2637 if (nr_stack_slots != 1) 2638 return; 2639 2640 /* the size of the last argument */ 2641 arg_size = m->arg_size[m->nr_args - 1]; 2642 if (arg_size <= 4) { 2643 off = -(stack_size - 4); 2644 prog = *pprog; 2645 /* mov DWORD PTR [rbp + off], 0 */ 2646 if (!is_imm8(off)) 2647 EMIT2_off32(0xC7, 0x85, off); 2648 else 2649 EMIT3(0xC7, 0x45, off); 2650 EMIT(0, 4); 2651 *pprog = prog; 2652 } 2653 } 2654 2655 /* get the count of the regs that are used to pass arguments */ 2656 static int get_nr_used_regs(const struct btf_func_model *m) 2657 { 2658 int i, arg_regs, nr_used_regs = 0; 2659 2660 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2661 arg_regs = (m->arg_size[i] + 7) / 8; 2662 if (nr_used_regs + arg_regs <= 6) 2663 nr_used_regs += arg_regs; 2664 2665 if (nr_used_regs >= 6) 2666 break; 2667 } 2668 2669 return nr_used_regs; 2670 } 2671 2672 static void save_args(const struct btf_func_model *m, u8 **prog, 2673 int stack_size, bool for_call_origin) 2674 { 2675 int arg_regs, first_off = 0, nr_regs = 0, nr_stack_slots = 0; 2676 int i, j; 2677 2678 /* Store function arguments to stack. 2679 * For a function that accepts two pointers the sequence will be: 2680 * mov QWORD PTR [rbp-0x10],rdi 2681 * mov QWORD PTR [rbp-0x8],rsi 2682 */ 2683 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2684 arg_regs = (m->arg_size[i] + 7) / 8; 2685 2686 /* According to the research of Yonghong, struct members 2687 * should be all in register or all on the stack. 2688 * Meanwhile, the compiler will pass the argument on regs 2689 * if the remaining regs can hold the argument. 2690 * 2691 * Disorder of the args can happen. For example: 2692 * 2693 * struct foo_struct { 2694 * long a; 2695 * int b; 2696 * }; 2697 * int foo(char, char, char, char, char, struct foo_struct, 2698 * char); 2699 * 2700 * the arg1-5,arg7 will be passed by regs, and arg6 will 2701 * by stack. 2702 */ 2703 if (nr_regs + arg_regs > 6) { 2704 /* copy function arguments from origin stack frame 2705 * into current stack frame. 2706 * 2707 * The starting address of the arguments on-stack 2708 * is: 2709 * rbp + 8(push rbp) + 2710 * 8(return addr of origin call) + 2711 * 8(return addr of the caller) 2712 * which means: rbp + 24 2713 */ 2714 for (j = 0; j < arg_regs; j++) { 2715 emit_ldx(prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 2716 nr_stack_slots * 8 + 0x18); 2717 emit_stx(prog, BPF_DW, BPF_REG_FP, BPF_REG_0, 2718 -stack_size); 2719 2720 if (!nr_stack_slots) 2721 first_off = stack_size; 2722 stack_size -= 8; 2723 nr_stack_slots++; 2724 } 2725 } else { 2726 /* Only copy the arguments on-stack to current 2727 * 'stack_size' and ignore the regs, used to 2728 * prepare the arguments on-stack for origin call. 2729 */ 2730 if (for_call_origin) { 2731 nr_regs += arg_regs; 2732 continue; 2733 } 2734 2735 /* copy the arguments from regs into stack */ 2736 for (j = 0; j < arg_regs; j++) { 2737 emit_stx(prog, BPF_DW, BPF_REG_FP, 2738 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2739 -stack_size); 2740 stack_size -= 8; 2741 nr_regs++; 2742 } 2743 } 2744 } 2745 2746 clean_stack_garbage(m, prog, nr_stack_slots, first_off); 2747 } 2748 2749 static void restore_regs(const struct btf_func_model *m, u8 **prog, 2750 int stack_size) 2751 { 2752 int i, j, arg_regs, nr_regs = 0; 2753 2754 /* Restore function arguments from stack. 2755 * For a function that accepts two pointers the sequence will be: 2756 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10] 2757 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8] 2758 * 2759 * The logic here is similar to what we do in save_args() 2760 */ 2761 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2762 arg_regs = (m->arg_size[i] + 7) / 8; 2763 if (nr_regs + arg_regs <= 6) { 2764 for (j = 0; j < arg_regs; j++) { 2765 emit_ldx(prog, BPF_DW, 2766 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2767 BPF_REG_FP, 2768 -stack_size); 2769 stack_size -= 8; 2770 nr_regs++; 2771 } 2772 } else { 2773 stack_size -= 8 * arg_regs; 2774 } 2775 2776 if (nr_regs >= 6) 2777 break; 2778 } 2779 } 2780 2781 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog, 2782 struct bpf_tramp_link *l, int stack_size, 2783 int run_ctx_off, bool save_ret, 2784 void *image, void *rw_image) 2785 { 2786 u8 *prog = *pprog; 2787 u8 *jmp_insn; 2788 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 2789 struct bpf_prog *p = l->link.prog; 2790 u64 cookie = l->cookie; 2791 2792 /* mov rdi, cookie */ 2793 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie); 2794 2795 /* Prepare struct bpf_tramp_run_ctx. 2796 * 2797 * bpf_tramp_run_ctx is already preserved by 2798 * arch_prepare_bpf_trampoline(). 2799 * 2800 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi 2801 */ 2802 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off); 2803 2804 /* arg1: mov rdi, progs[i] */ 2805 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 2806 /* arg2: lea rsi, [rbp - ctx_cookie_off] */ 2807 if (!is_imm8(-run_ctx_off)) 2808 EMIT3_off32(0x48, 0x8D, 0xB5, -run_ctx_off); 2809 else 2810 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off); 2811 2812 if (emit_rsb_call(&prog, bpf_trampoline_enter(p), image + (prog - (u8 *)rw_image))) 2813 return -EINVAL; 2814 /* remember prog start time returned by __bpf_prog_enter */ 2815 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0); 2816 2817 /* if (__bpf_prog_enter*(prog) == 0) 2818 * goto skip_exec_of_prog; 2819 */ 2820 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */ 2821 /* emit 2 nops that will be replaced with JE insn */ 2822 jmp_insn = prog; 2823 emit_nops(&prog, 2); 2824 2825 /* arg1: lea rdi, [rbp - stack_size] */ 2826 if (!is_imm8(-stack_size)) 2827 EMIT3_off32(0x48, 0x8D, 0xBD, -stack_size); 2828 else 2829 EMIT4(0x48, 0x8D, 0x7D, -stack_size); 2830 /* arg2: progs[i]->insnsi for interpreter */ 2831 if (!p->jited) 2832 emit_mov_imm64(&prog, BPF_REG_2, 2833 (long) p->insnsi >> 32, 2834 (u32) (long) p->insnsi); 2835 /* call JITed bpf program or interpreter */ 2836 if (emit_rsb_call(&prog, p->bpf_func, image + (prog - (u8 *)rw_image))) 2837 return -EINVAL; 2838 2839 /* 2840 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return 2841 * of the previous call which is then passed on the stack to 2842 * the next BPF program. 2843 * 2844 * BPF_TRAMP_FENTRY trampoline may need to return the return 2845 * value of BPF_PROG_TYPE_STRUCT_OPS prog. 2846 */ 2847 if (save_ret) 2848 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2849 2850 /* replace 2 nops with JE insn, since jmp target is known */ 2851 jmp_insn[0] = X86_JE; 2852 jmp_insn[1] = prog - jmp_insn - 2; 2853 2854 /* arg1: mov rdi, progs[i] */ 2855 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 2856 /* arg2: mov rsi, rbx <- start time in nsec */ 2857 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6); 2858 /* arg3: lea rdx, [rbp - run_ctx_off] */ 2859 if (!is_imm8(-run_ctx_off)) 2860 EMIT3_off32(0x48, 0x8D, 0x95, -run_ctx_off); 2861 else 2862 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off); 2863 if (emit_rsb_call(&prog, bpf_trampoline_exit(p), image + (prog - (u8 *)rw_image))) 2864 return -EINVAL; 2865 2866 *pprog = prog; 2867 return 0; 2868 } 2869 2870 static void emit_align(u8 **pprog, u32 align) 2871 { 2872 u8 *target, *prog = *pprog; 2873 2874 target = PTR_ALIGN(prog, align); 2875 if (target != prog) 2876 emit_nops(&prog, target - prog); 2877 2878 *pprog = prog; 2879 } 2880 2881 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond) 2882 { 2883 u8 *prog = *pprog; 2884 s64 offset; 2885 2886 offset = func - (ip + 2 + 4); 2887 if (!is_simm32(offset)) { 2888 pr_err("Target %p is out of range\n", func); 2889 return -EINVAL; 2890 } 2891 EMIT2_off32(0x0F, jmp_cond + 0x10, offset); 2892 *pprog = prog; 2893 return 0; 2894 } 2895 2896 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog, 2897 struct bpf_tramp_links *tl, int stack_size, 2898 int run_ctx_off, bool save_ret, 2899 void *image, void *rw_image) 2900 { 2901 int i; 2902 u8 *prog = *pprog; 2903 2904 for (i = 0; i < tl->nr_links; i++) { 2905 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, 2906 run_ctx_off, save_ret, image, rw_image)) 2907 return -EINVAL; 2908 } 2909 *pprog = prog; 2910 return 0; 2911 } 2912 2913 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog, 2914 struct bpf_tramp_links *tl, int stack_size, 2915 int run_ctx_off, u8 **branches, 2916 void *image, void *rw_image) 2917 { 2918 u8 *prog = *pprog; 2919 int i; 2920 2921 /* The first fmod_ret program will receive a garbage return value. 2922 * Set this to 0 to avoid confusing the program. 2923 */ 2924 emit_mov_imm32(&prog, false, BPF_REG_0, 0); 2925 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2926 for (i = 0; i < tl->nr_links; i++) { 2927 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true, 2928 image, rw_image)) 2929 return -EINVAL; 2930 2931 /* mod_ret prog stored return value into [rbp - 8]. Emit: 2932 * if (*(u64 *)(rbp - 8) != 0) 2933 * goto do_fexit; 2934 */ 2935 /* cmp QWORD PTR [rbp - 0x8], 0x0 */ 2936 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00); 2937 2938 /* Save the location of the branch and Generate 6 nops 2939 * (4 bytes for an offset and 2 bytes for the jump) These nops 2940 * are replaced with a conditional jump once do_fexit (i.e. the 2941 * start of the fexit invocation) is finalized. 2942 */ 2943 branches[i] = prog; 2944 emit_nops(&prog, 4 + 2); 2945 } 2946 2947 *pprog = prog; 2948 return 0; 2949 } 2950 2951 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */ 2952 #define LOAD_TRAMP_TAIL_CALL_CNT_PTR(stack) \ 2953 __LOAD_TCC_PTR(-round_up(stack, 8) - 8) 2954 2955 /* Example: 2956 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev); 2957 * its 'struct btf_func_model' will be nr_args=2 2958 * The assembly code when eth_type_trans is executing after trampoline: 2959 * 2960 * push rbp 2961 * mov rbp, rsp 2962 * sub rsp, 16 // space for skb and dev 2963 * push rbx // temp regs to pass start time 2964 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack 2965 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack 2966 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2967 * mov rbx, rax // remember start time in bpf stats are enabled 2968 * lea rdi, [rbp - 16] // R1==ctx of bpf prog 2969 * call addr_of_jited_FENTRY_prog 2970 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2971 * mov rsi, rbx // prog start time 2972 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2973 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack 2974 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack 2975 * pop rbx 2976 * leave 2977 * ret 2978 * 2979 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be 2980 * replaced with 'call generated_bpf_trampoline'. When it returns 2981 * eth_type_trans will continue executing with original skb and dev pointers. 2982 * 2983 * The assembly code when eth_type_trans is called from trampoline: 2984 * 2985 * push rbp 2986 * mov rbp, rsp 2987 * sub rsp, 24 // space for skb, dev, return value 2988 * push rbx // temp regs to pass start time 2989 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack 2990 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack 2991 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2992 * mov rbx, rax // remember start time if bpf stats are enabled 2993 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 2994 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev 2995 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2996 * mov rsi, rbx // prog start time 2997 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2998 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack 2999 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack 3000 * call eth_type_trans+5 // execute body of eth_type_trans 3001 * mov qword ptr [rbp - 8], rax // save return value 3002 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 3003 * mov rbx, rax // remember start time in bpf stats are enabled 3004 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 3005 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value 3006 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 3007 * mov rsi, rbx // prog start time 3008 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 3009 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value 3010 * pop rbx 3011 * leave 3012 * add rsp, 8 // skip eth_type_trans's frame 3013 * ret // return to its caller 3014 */ 3015 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *rw_image, 3016 void *rw_image_end, void *image, 3017 const struct btf_func_model *m, u32 flags, 3018 struct bpf_tramp_links *tlinks, 3019 void *func_addr) 3020 { 3021 int i, ret, nr_regs = m->nr_args, stack_size = 0; 3022 int regs_off, nregs_off, ip_off, run_ctx_off, arg_stack_off, rbx_off; 3023 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 3024 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 3025 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 3026 void *orig_call = func_addr; 3027 u8 **branches = NULL; 3028 u8 *prog; 3029 bool save_ret; 3030 3031 /* 3032 * F_INDIRECT is only compatible with F_RET_FENTRY_RET, it is 3033 * explicitly incompatible with F_CALL_ORIG | F_SKIP_FRAME | F_IP_ARG 3034 * because @func_addr. 3035 */ 3036 WARN_ON_ONCE((flags & BPF_TRAMP_F_INDIRECT) && 3037 (flags & ~(BPF_TRAMP_F_INDIRECT | BPF_TRAMP_F_RET_FENTRY_RET))); 3038 3039 /* extra registers for struct arguments */ 3040 for (i = 0; i < m->nr_args; i++) { 3041 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) 3042 nr_regs += (m->arg_size[i] + 7) / 8 - 1; 3043 } 3044 3045 /* x86-64 supports up to MAX_BPF_FUNC_ARGS arguments. 1-6 3046 * are passed through regs, the remains are through stack. 3047 */ 3048 if (nr_regs > MAX_BPF_FUNC_ARGS) 3049 return -ENOTSUPP; 3050 3051 /* Generated trampoline stack layout: 3052 * 3053 * RBP + 8 [ return address ] 3054 * RBP + 0 [ RBP ] 3055 * 3056 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or 3057 * BPF_TRAMP_F_RET_FENTRY_RET flags 3058 * 3059 * [ reg_argN ] always 3060 * [ ... ] 3061 * RBP - regs_off [ reg_arg1 ] program's ctx pointer 3062 * 3063 * RBP - nregs_off [ regs count ] always 3064 * 3065 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag 3066 * 3067 * RBP - rbx_off [ rbx value ] always 3068 * 3069 * RBP - run_ctx_off [ bpf_tramp_run_ctx ] 3070 * 3071 * [ stack_argN ] BPF_TRAMP_F_CALL_ORIG 3072 * [ ... ] 3073 * [ stack_arg2 ] 3074 * RBP - arg_stack_off [ stack_arg1 ] 3075 * RSP [ tail_call_cnt_ptr ] BPF_TRAMP_F_TAIL_CALL_CTX 3076 */ 3077 3078 /* room for return value of orig_call or fentry prog */ 3079 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 3080 if (save_ret) 3081 stack_size += 8; 3082 3083 stack_size += nr_regs * 8; 3084 regs_off = stack_size; 3085 3086 /* regs count */ 3087 stack_size += 8; 3088 nregs_off = stack_size; 3089 3090 if (flags & BPF_TRAMP_F_IP_ARG) 3091 stack_size += 8; /* room for IP address argument */ 3092 3093 ip_off = stack_size; 3094 3095 stack_size += 8; 3096 rbx_off = stack_size; 3097 3098 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7; 3099 run_ctx_off = stack_size; 3100 3101 if (nr_regs > 6 && (flags & BPF_TRAMP_F_CALL_ORIG)) { 3102 /* the space that used to pass arguments on-stack */ 3103 stack_size += (nr_regs - get_nr_used_regs(m)) * 8; 3104 /* make sure the stack pointer is 16-byte aligned if we 3105 * need pass arguments on stack, which means 3106 * [stack_size + 8(rbp) + 8(rip) + 8(origin rip)] 3107 * should be 16-byte aligned. Following code depend on 3108 * that stack_size is already 8-byte aligned. 3109 */ 3110 stack_size += (stack_size % 16) ? 0 : 8; 3111 } 3112 3113 arg_stack_off = stack_size; 3114 3115 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 3116 /* skip patched call instruction and point orig_call to actual 3117 * body of the kernel function. 3118 */ 3119 if (is_endbr(orig_call)) 3120 orig_call += ENDBR_INSN_SIZE; 3121 orig_call += X86_PATCH_SIZE; 3122 } 3123 3124 prog = rw_image; 3125 3126 if (flags & BPF_TRAMP_F_INDIRECT) { 3127 /* 3128 * Indirect call for bpf_struct_ops 3129 */ 3130 emit_cfi(&prog, image, 3131 cfi_get_func_hash(func_addr), 3132 cfi_get_func_arity(func_addr)); 3133 } else { 3134 /* 3135 * Direct-call fentry stub, as such it needs accounting for the 3136 * __fentry__ call. 3137 */ 3138 x86_call_depth_emit_accounting(&prog, NULL, image); 3139 } 3140 EMIT1(0x55); /* push rbp */ 3141 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 3142 if (!is_imm8(stack_size)) { 3143 /* sub rsp, stack_size */ 3144 EMIT3_off32(0x48, 0x81, 0xEC, stack_size); 3145 } else { 3146 /* sub rsp, stack_size */ 3147 EMIT4(0x48, 0x83, 0xEC, stack_size); 3148 } 3149 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) 3150 EMIT1(0x50); /* push rax */ 3151 /* mov QWORD PTR [rbp - rbx_off], rbx */ 3152 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_6, -rbx_off); 3153 3154 /* Store number of argument registers of the traced function: 3155 * mov rax, nr_regs 3156 * mov QWORD PTR [rbp - nregs_off], rax 3157 */ 3158 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs); 3159 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off); 3160 3161 if (flags & BPF_TRAMP_F_IP_ARG) { 3162 /* Store IP address of the traced function: 3163 * movabsq rax, func_addr 3164 * mov QWORD PTR [rbp - ip_off], rax 3165 */ 3166 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr); 3167 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off); 3168 } 3169 3170 save_args(m, &prog, regs_off, false); 3171 3172 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3173 /* arg1: mov rdi, im */ 3174 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 3175 if (emit_rsb_call(&prog, __bpf_tramp_enter, 3176 image + (prog - (u8 *)rw_image))) { 3177 ret = -EINVAL; 3178 goto cleanup; 3179 } 3180 } 3181 3182 if (fentry->nr_links) { 3183 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off, 3184 flags & BPF_TRAMP_F_RET_FENTRY_RET, image, rw_image)) 3185 return -EINVAL; 3186 } 3187 3188 if (fmod_ret->nr_links) { 3189 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *), 3190 GFP_KERNEL); 3191 if (!branches) 3192 return -ENOMEM; 3193 3194 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off, 3195 run_ctx_off, branches, image, rw_image)) { 3196 ret = -EINVAL; 3197 goto cleanup; 3198 } 3199 } 3200 3201 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3202 restore_regs(m, &prog, regs_off); 3203 save_args(m, &prog, arg_stack_off, true); 3204 3205 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) { 3206 /* Before calling the original function, load the 3207 * tail_call_cnt_ptr from stack to rax. 3208 */ 3209 LOAD_TRAMP_TAIL_CALL_CNT_PTR(stack_size); 3210 } 3211 3212 if (flags & BPF_TRAMP_F_ORIG_STACK) { 3213 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, 8); 3214 EMIT2(0xff, 0xd3); /* call *rbx */ 3215 } else { 3216 /* call original function */ 3217 if (emit_rsb_call(&prog, orig_call, image + (prog - (u8 *)rw_image))) { 3218 ret = -EINVAL; 3219 goto cleanup; 3220 } 3221 } 3222 /* remember return value in a stack for bpf prog to access */ 3223 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 3224 im->ip_after_call = image + (prog - (u8 *)rw_image); 3225 emit_nops(&prog, X86_PATCH_SIZE); 3226 } 3227 3228 if (fmod_ret->nr_links) { 3229 /* From Intel 64 and IA-32 Architectures Optimization 3230 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 3231 * Coding Rule 11: All branch targets should be 16-byte 3232 * aligned. 3233 */ 3234 emit_align(&prog, 16); 3235 /* Update the branches saved in invoke_bpf_mod_ret with the 3236 * aligned address of do_fexit. 3237 */ 3238 for (i = 0; i < fmod_ret->nr_links; i++) { 3239 emit_cond_near_jump(&branches[i], image + (prog - (u8 *)rw_image), 3240 image + (branches[i] - (u8 *)rw_image), X86_JNE); 3241 } 3242 } 3243 3244 if (fexit->nr_links) { 3245 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, 3246 false, image, rw_image)) { 3247 ret = -EINVAL; 3248 goto cleanup; 3249 } 3250 } 3251 3252 if (flags & BPF_TRAMP_F_RESTORE_REGS) 3253 restore_regs(m, &prog, regs_off); 3254 3255 /* This needs to be done regardless. If there were fmod_ret programs, 3256 * the return value is only updated on the stack and still needs to be 3257 * restored to R0. 3258 */ 3259 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3260 im->ip_epilogue = image + (prog - (u8 *)rw_image); 3261 /* arg1: mov rdi, im */ 3262 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 3263 if (emit_rsb_call(&prog, __bpf_tramp_exit, image + (prog - (u8 *)rw_image))) { 3264 ret = -EINVAL; 3265 goto cleanup; 3266 } 3267 } else if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) { 3268 /* Before running the original function, load the 3269 * tail_call_cnt_ptr from stack to rax. 3270 */ 3271 LOAD_TRAMP_TAIL_CALL_CNT_PTR(stack_size); 3272 } 3273 3274 /* restore return value of orig_call or fentry prog back into RAX */ 3275 if (save_ret) 3276 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8); 3277 3278 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, -rbx_off); 3279 EMIT1(0xC9); /* leave */ 3280 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 3281 /* skip our return address and return to parent */ 3282 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */ 3283 } 3284 emit_return(&prog, image + (prog - (u8 *)rw_image)); 3285 /* Make sure the trampoline generation logic doesn't overflow */ 3286 if (WARN_ON_ONCE(prog > (u8 *)rw_image_end - BPF_INSN_SAFETY)) { 3287 ret = -EFAULT; 3288 goto cleanup; 3289 } 3290 ret = prog - (u8 *)rw_image + BPF_INSN_SAFETY; 3291 3292 cleanup: 3293 kfree(branches); 3294 return ret; 3295 } 3296 3297 void *arch_alloc_bpf_trampoline(unsigned int size) 3298 { 3299 return bpf_prog_pack_alloc(size, jit_fill_hole); 3300 } 3301 3302 void arch_free_bpf_trampoline(void *image, unsigned int size) 3303 { 3304 bpf_prog_pack_free(image, size); 3305 } 3306 3307 int arch_protect_bpf_trampoline(void *image, unsigned int size) 3308 { 3309 return 0; 3310 } 3311 3312 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end, 3313 const struct btf_func_model *m, u32 flags, 3314 struct bpf_tramp_links *tlinks, 3315 void *func_addr) 3316 { 3317 void *rw_image, *tmp; 3318 int ret; 3319 u32 size = image_end - image; 3320 3321 /* rw_image doesn't need to be in module memory range, so we can 3322 * use kvmalloc. 3323 */ 3324 rw_image = kvmalloc(size, GFP_KERNEL); 3325 if (!rw_image) 3326 return -ENOMEM; 3327 3328 ret = __arch_prepare_bpf_trampoline(im, rw_image, rw_image + size, image, m, 3329 flags, tlinks, func_addr); 3330 if (ret < 0) 3331 goto out; 3332 3333 tmp = bpf_arch_text_copy(image, rw_image, size); 3334 if (IS_ERR(tmp)) 3335 ret = PTR_ERR(tmp); 3336 out: 3337 kvfree(rw_image); 3338 return ret; 3339 } 3340 3341 int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags, 3342 struct bpf_tramp_links *tlinks, void *func_addr) 3343 { 3344 struct bpf_tramp_image im; 3345 void *image; 3346 int ret; 3347 3348 /* Allocate a temporary buffer for __arch_prepare_bpf_trampoline(). 3349 * This will NOT cause fragmentation in direct map, as we do not 3350 * call set_memory_*() on this buffer. 3351 * 3352 * We cannot use kvmalloc here, because we need image to be in 3353 * module memory range. 3354 */ 3355 image = bpf_jit_alloc_exec(PAGE_SIZE); 3356 if (!image) 3357 return -ENOMEM; 3358 3359 ret = __arch_prepare_bpf_trampoline(&im, image, image + PAGE_SIZE, image, 3360 m, flags, tlinks, func_addr); 3361 bpf_jit_free_exec(image); 3362 return ret; 3363 } 3364 3365 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf) 3366 { 3367 u8 *jg_reloc, *prog = *pprog; 3368 int pivot, err, jg_bytes = 1; 3369 s64 jg_offset; 3370 3371 if (a == b) { 3372 /* Leaf node of recursion, i.e. not a range of indices 3373 * anymore. 3374 */ 3375 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 3376 if (!is_simm32(progs[a])) 3377 return -1; 3378 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), 3379 progs[a]); 3380 err = emit_cond_near_jump(&prog, /* je func */ 3381 (void *)progs[a], image + (prog - buf), 3382 X86_JE); 3383 if (err) 3384 return err; 3385 3386 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf)); 3387 3388 *pprog = prog; 3389 return 0; 3390 } 3391 3392 /* Not a leaf node, so we pivot, and recursively descend into 3393 * the lower and upper ranges. 3394 */ 3395 pivot = (b - a) / 2; 3396 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 3397 if (!is_simm32(progs[a + pivot])) 3398 return -1; 3399 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]); 3400 3401 if (pivot > 2) { /* jg upper_part */ 3402 /* Require near jump. */ 3403 jg_bytes = 4; 3404 EMIT2_off32(0x0F, X86_JG + 0x10, 0); 3405 } else { 3406 EMIT2(X86_JG, 0); 3407 } 3408 jg_reloc = prog; 3409 3410 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */ 3411 progs, image, buf); 3412 if (err) 3413 return err; 3414 3415 /* From Intel 64 and IA-32 Architectures Optimization 3416 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 3417 * Coding Rule 11: All branch targets should be 16-byte 3418 * aligned. 3419 */ 3420 emit_align(&prog, 16); 3421 jg_offset = prog - jg_reloc; 3422 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes); 3423 3424 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */ 3425 b, progs, image, buf); 3426 if (err) 3427 return err; 3428 3429 *pprog = prog; 3430 return 0; 3431 } 3432 3433 static int cmp_ips(const void *a, const void *b) 3434 { 3435 const s64 *ipa = a; 3436 const s64 *ipb = b; 3437 3438 if (*ipa > *ipb) 3439 return 1; 3440 if (*ipa < *ipb) 3441 return -1; 3442 return 0; 3443 } 3444 3445 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs) 3446 { 3447 u8 *prog = buf; 3448 3449 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL); 3450 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf); 3451 } 3452 3453 static const char *bpf_get_prog_name(struct bpf_prog *prog) 3454 { 3455 if (prog->aux->ksym.prog) 3456 return prog->aux->ksym.name; 3457 return prog->aux->name; 3458 } 3459 3460 static void priv_stack_init_guard(void __percpu *priv_stack_ptr, int alloc_size) 3461 { 3462 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 3463 u64 *stack_ptr; 3464 3465 for_each_possible_cpu(cpu) { 3466 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 3467 stack_ptr[0] = PRIV_STACK_GUARD_VAL; 3468 stack_ptr[underflow_idx] = PRIV_STACK_GUARD_VAL; 3469 } 3470 } 3471 3472 static void priv_stack_check_guard(void __percpu *priv_stack_ptr, int alloc_size, 3473 struct bpf_prog *prog) 3474 { 3475 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 3476 u64 *stack_ptr; 3477 3478 for_each_possible_cpu(cpu) { 3479 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 3480 if (stack_ptr[0] != PRIV_STACK_GUARD_VAL || 3481 stack_ptr[underflow_idx] != PRIV_STACK_GUARD_VAL) { 3482 pr_err("BPF private stack overflow/underflow detected for prog %sx\n", 3483 bpf_get_prog_name(prog)); 3484 break; 3485 } 3486 } 3487 } 3488 3489 struct x64_jit_data { 3490 struct bpf_binary_header *rw_header; 3491 struct bpf_binary_header *header; 3492 int *addrs; 3493 u8 *image; 3494 int proglen; 3495 struct jit_context ctx; 3496 }; 3497 3498 #define MAX_PASSES 20 3499 #define PADDING_PASSES (MAX_PASSES - 5) 3500 3501 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) 3502 { 3503 struct bpf_binary_header *rw_header = NULL; 3504 struct bpf_binary_header *header = NULL; 3505 struct bpf_prog *tmp, *orig_prog = prog; 3506 void __percpu *priv_stack_ptr = NULL; 3507 struct x64_jit_data *jit_data; 3508 int priv_stack_alloc_sz; 3509 int proglen, oldproglen = 0; 3510 struct jit_context ctx = {}; 3511 bool tmp_blinded = false; 3512 bool extra_pass = false; 3513 bool padding = false; 3514 u8 *rw_image = NULL; 3515 u8 *image = NULL; 3516 int *addrs; 3517 int pass; 3518 int i; 3519 3520 if (!prog->jit_requested) 3521 return orig_prog; 3522 3523 tmp = bpf_jit_blind_constants(prog); 3524 /* 3525 * If blinding was requested and we failed during blinding, 3526 * we must fall back to the interpreter. 3527 */ 3528 if (IS_ERR(tmp)) 3529 return orig_prog; 3530 if (tmp != prog) { 3531 tmp_blinded = true; 3532 prog = tmp; 3533 } 3534 3535 jit_data = prog->aux->jit_data; 3536 if (!jit_data) { 3537 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); 3538 if (!jit_data) { 3539 prog = orig_prog; 3540 goto out; 3541 } 3542 prog->aux->jit_data = jit_data; 3543 } 3544 priv_stack_ptr = prog->aux->priv_stack_ptr; 3545 if (!priv_stack_ptr && prog->aux->jits_use_priv_stack) { 3546 /* Allocate actual private stack size with verifier-calculated 3547 * stack size plus two memory guards to protect overflow and 3548 * underflow. 3549 */ 3550 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 8) + 3551 2 * PRIV_STACK_GUARD_SZ; 3552 priv_stack_ptr = __alloc_percpu_gfp(priv_stack_alloc_sz, 8, GFP_KERNEL); 3553 if (!priv_stack_ptr) { 3554 prog = orig_prog; 3555 goto out_priv_stack; 3556 } 3557 3558 priv_stack_init_guard(priv_stack_ptr, priv_stack_alloc_sz); 3559 prog->aux->priv_stack_ptr = priv_stack_ptr; 3560 } 3561 addrs = jit_data->addrs; 3562 if (addrs) { 3563 ctx = jit_data->ctx; 3564 oldproglen = jit_data->proglen; 3565 image = jit_data->image; 3566 header = jit_data->header; 3567 rw_header = jit_data->rw_header; 3568 rw_image = (void *)rw_header + ((void *)image - (void *)header); 3569 extra_pass = true; 3570 padding = true; 3571 goto skip_init_addrs; 3572 } 3573 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL); 3574 if (!addrs) { 3575 prog = orig_prog; 3576 goto out_addrs; 3577 } 3578 3579 /* 3580 * Before first pass, make a rough estimation of addrs[] 3581 * each BPF instruction is translated to less than 64 bytes 3582 */ 3583 for (proglen = 0, i = 0; i <= prog->len; i++) { 3584 proglen += 64; 3585 addrs[i] = proglen; 3586 } 3587 ctx.cleanup_addr = proglen; 3588 skip_init_addrs: 3589 3590 /* 3591 * JITed image shrinks with every pass and the loop iterates 3592 * until the image stops shrinking. Very large BPF programs 3593 * may converge on the last pass. In such case do one more 3594 * pass to emit the final image. 3595 */ 3596 for (pass = 0; pass < MAX_PASSES || image; pass++) { 3597 if (!padding && pass >= PADDING_PASSES) 3598 padding = true; 3599 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding); 3600 if (proglen <= 0) { 3601 out_image: 3602 image = NULL; 3603 if (header) { 3604 bpf_arch_text_copy(&header->size, &rw_header->size, 3605 sizeof(rw_header->size)); 3606 bpf_jit_binary_pack_free(header, rw_header); 3607 } 3608 /* Fall back to interpreter mode */ 3609 prog = orig_prog; 3610 if (extra_pass) { 3611 prog->bpf_func = NULL; 3612 prog->jited = 0; 3613 prog->jited_len = 0; 3614 } 3615 goto out_addrs; 3616 } 3617 if (image) { 3618 if (proglen != oldproglen) { 3619 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n", 3620 proglen, oldproglen); 3621 goto out_image; 3622 } 3623 break; 3624 } 3625 if (proglen == oldproglen) { 3626 /* 3627 * The number of entries in extable is the number of BPF_LDX 3628 * insns that access kernel memory via "pointer to BTF type". 3629 * The verifier changed their opcode from LDX|MEM|size 3630 * to LDX|PROBE_MEM|size to make JITing easier. 3631 */ 3632 u32 align = __alignof__(struct exception_table_entry); 3633 u32 extable_size = prog->aux->num_exentries * 3634 sizeof(struct exception_table_entry); 3635 3636 /* allocate module memory for x86 insns and extable */ 3637 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size, 3638 &image, align, &rw_header, &rw_image, 3639 jit_fill_hole); 3640 if (!header) { 3641 prog = orig_prog; 3642 goto out_addrs; 3643 } 3644 prog->aux->extable = (void *) image + roundup(proglen, align); 3645 } 3646 oldproglen = proglen; 3647 cond_resched(); 3648 } 3649 3650 if (bpf_jit_enable > 1) 3651 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image); 3652 3653 if (image) { 3654 if (!prog->is_func || extra_pass) { 3655 /* 3656 * bpf_jit_binary_pack_finalize fails in two scenarios: 3657 * 1) header is not pointing to proper module memory; 3658 * 2) the arch doesn't support bpf_arch_text_copy(). 3659 * 3660 * Both cases are serious bugs and justify WARN_ON. 3661 */ 3662 if (WARN_ON(bpf_jit_binary_pack_finalize(header, rw_header))) { 3663 /* header has been freed */ 3664 header = NULL; 3665 goto out_image; 3666 } 3667 3668 bpf_tail_call_direct_fixup(prog); 3669 } else { 3670 jit_data->addrs = addrs; 3671 jit_data->ctx = ctx; 3672 jit_data->proglen = proglen; 3673 jit_data->image = image; 3674 jit_data->header = header; 3675 jit_data->rw_header = rw_header; 3676 } 3677 /* 3678 * ctx.prog_offset is used when CFI preambles put code *before* 3679 * the function. See emit_cfi(). For FineIBT specifically this code 3680 * can also be executed and bpf_prog_kallsyms_add() will 3681 * generate an additional symbol to cover this, hence also 3682 * decrement proglen. 3683 */ 3684 prog->bpf_func = (void *)image + cfi_get_offset(); 3685 prog->jited = 1; 3686 prog->jited_len = proglen - cfi_get_offset(); 3687 } else { 3688 prog = orig_prog; 3689 } 3690 3691 if (!image || !prog->is_func || extra_pass) { 3692 if (image) 3693 bpf_prog_fill_jited_linfo(prog, addrs + 1); 3694 out_addrs: 3695 kvfree(addrs); 3696 if (!image && priv_stack_ptr) { 3697 free_percpu(priv_stack_ptr); 3698 prog->aux->priv_stack_ptr = NULL; 3699 } 3700 out_priv_stack: 3701 kfree(jit_data); 3702 prog->aux->jit_data = NULL; 3703 } 3704 out: 3705 if (tmp_blinded) 3706 bpf_jit_prog_release_other(prog, prog == orig_prog ? 3707 tmp : orig_prog); 3708 return prog; 3709 } 3710 3711 bool bpf_jit_supports_kfunc_call(void) 3712 { 3713 return true; 3714 } 3715 3716 void *bpf_arch_text_copy(void *dst, void *src, size_t len) 3717 { 3718 if (text_poke_copy(dst, src, len) == NULL) 3719 return ERR_PTR(-EINVAL); 3720 return dst; 3721 } 3722 3723 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */ 3724 bool bpf_jit_supports_subprog_tailcalls(void) 3725 { 3726 return true; 3727 } 3728 3729 bool bpf_jit_supports_percpu_insn(void) 3730 { 3731 return true; 3732 } 3733 3734 void bpf_jit_free(struct bpf_prog *prog) 3735 { 3736 if (prog->jited) { 3737 struct x64_jit_data *jit_data = prog->aux->jit_data; 3738 struct bpf_binary_header *hdr; 3739 void __percpu *priv_stack_ptr; 3740 int priv_stack_alloc_sz; 3741 3742 /* 3743 * If we fail the final pass of JIT (from jit_subprogs), 3744 * the program may not be finalized yet. Call finalize here 3745 * before freeing it. 3746 */ 3747 if (jit_data) { 3748 bpf_jit_binary_pack_finalize(jit_data->header, 3749 jit_data->rw_header); 3750 kvfree(jit_data->addrs); 3751 kfree(jit_data); 3752 } 3753 prog->bpf_func = (void *)prog->bpf_func - cfi_get_offset(); 3754 hdr = bpf_jit_binary_pack_hdr(prog); 3755 bpf_jit_binary_pack_free(hdr, NULL); 3756 priv_stack_ptr = prog->aux->priv_stack_ptr; 3757 if (priv_stack_ptr) { 3758 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 8) + 3759 2 * PRIV_STACK_GUARD_SZ; 3760 priv_stack_check_guard(priv_stack_ptr, priv_stack_alloc_sz, prog); 3761 free_percpu(prog->aux->priv_stack_ptr); 3762 } 3763 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog)); 3764 } 3765 3766 bpf_prog_unlock_free(prog); 3767 } 3768 3769 bool bpf_jit_supports_exceptions(void) 3770 { 3771 /* We unwind through both kernel frames (starting from within bpf_throw 3772 * call) and BPF frames. Therefore we require ORC unwinder to be enabled 3773 * to walk kernel frames and reach BPF frames in the stack trace. 3774 */ 3775 return IS_ENABLED(CONFIG_UNWINDER_ORC); 3776 } 3777 3778 bool bpf_jit_supports_private_stack(void) 3779 { 3780 return true; 3781 } 3782 3783 void arch_bpf_stack_walk(bool (*consume_fn)(void *cookie, u64 ip, u64 sp, u64 bp), void *cookie) 3784 { 3785 #if defined(CONFIG_UNWINDER_ORC) 3786 struct unwind_state state; 3787 unsigned long addr; 3788 3789 for (unwind_start(&state, current, NULL, NULL); !unwind_done(&state); 3790 unwind_next_frame(&state)) { 3791 addr = unwind_get_return_address(&state); 3792 if (!addr || !consume_fn(cookie, (u64)addr, (u64)state.sp, (u64)state.bp)) 3793 break; 3794 } 3795 return; 3796 #endif 3797 WARN(1, "verification of programs using bpf_throw should have failed\n"); 3798 } 3799 3800 void bpf_arch_poke_desc_update(struct bpf_jit_poke_descriptor *poke, 3801 struct bpf_prog *new, struct bpf_prog *old) 3802 { 3803 u8 *old_addr, *new_addr, *old_bypass_addr; 3804 int ret; 3805 3806 old_bypass_addr = old ? NULL : poke->bypass_addr; 3807 old_addr = old ? (u8 *)old->bpf_func + poke->adj_off : NULL; 3808 new_addr = new ? (u8 *)new->bpf_func + poke->adj_off : NULL; 3809 3810 /* 3811 * On program loading or teardown, the program's kallsym entry 3812 * might not be in place, so we use __bpf_arch_text_poke to skip 3813 * the kallsyms check. 3814 */ 3815 if (new) { 3816 ret = __bpf_arch_text_poke(poke->tailcall_target, 3817 BPF_MOD_JUMP, 3818 old_addr, new_addr); 3819 BUG_ON(ret < 0); 3820 if (!old) { 3821 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 3822 BPF_MOD_JUMP, 3823 poke->bypass_addr, 3824 NULL); 3825 BUG_ON(ret < 0); 3826 } 3827 } else { 3828 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 3829 BPF_MOD_JUMP, 3830 old_bypass_addr, 3831 poke->bypass_addr); 3832 BUG_ON(ret < 0); 3833 /* let other CPUs finish the execution of program 3834 * so that it will not possible to expose them 3835 * to invalid nop, stack unwind, nop state 3836 */ 3837 if (!ret) 3838 synchronize_rcu(); 3839 ret = __bpf_arch_text_poke(poke->tailcall_target, 3840 BPF_MOD_JUMP, 3841 old_addr, NULL); 3842 BUG_ON(ret < 0); 3843 } 3844 } 3845 3846 bool bpf_jit_supports_arena(void) 3847 { 3848 return true; 3849 } 3850 3851 bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena) 3852 { 3853 if (!in_arena) 3854 return true; 3855 switch (insn->code) { 3856 case BPF_STX | BPF_ATOMIC | BPF_W: 3857 case BPF_STX | BPF_ATOMIC | BPF_DW: 3858 if (insn->imm == (BPF_AND | BPF_FETCH) || 3859 insn->imm == (BPF_OR | BPF_FETCH) || 3860 insn->imm == (BPF_XOR | BPF_FETCH)) 3861 return false; 3862 } 3863 return true; 3864 } 3865 3866 bool bpf_jit_supports_ptr_xchg(void) 3867 { 3868 return true; 3869 } 3870 3871 /* x86-64 JIT emits its own code to filter user addresses so return 0 here */ 3872 u64 bpf_arch_uaddress_limit(void) 3873 { 3874 return 0; 3875 } 3876 3877 bool bpf_jit_supports_timed_may_goto(void) 3878 { 3879 return true; 3880 } 3881