1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BPF JIT compiler 4 * 5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com) 6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com 7 */ 8 #include <linux/netdevice.h> 9 #include <linux/filter.h> 10 #include <linux/if_vlan.h> 11 #include <linux/bpf.h> 12 #include <linux/memory.h> 13 #include <linux/sort.h> 14 #include <asm/extable.h> 15 #include <asm/ftrace.h> 16 #include <asm/set_memory.h> 17 #include <asm/nospec-branch.h> 18 #include <asm/text-patching.h> 19 #include <asm/unwind.h> 20 #include <asm/cfi.h> 21 22 static bool all_callee_regs_used[4] = {true, true, true, true}; 23 24 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len) 25 { 26 if (len == 1) 27 *ptr = bytes; 28 else if (len == 2) 29 *(u16 *)ptr = bytes; 30 else { 31 *(u32 *)ptr = bytes; 32 barrier(); 33 } 34 return ptr + len; 35 } 36 37 #define EMIT(bytes, len) \ 38 do { prog = emit_code(prog, bytes, len); } while (0) 39 40 #define EMIT1(b1) EMIT(b1, 1) 41 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2) 42 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3) 43 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4) 44 45 #define EMIT1_off32(b1, off) \ 46 do { EMIT1(b1); EMIT(off, 4); } while (0) 47 #define EMIT2_off32(b1, b2, off) \ 48 do { EMIT2(b1, b2); EMIT(off, 4); } while (0) 49 #define EMIT3_off32(b1, b2, b3, off) \ 50 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0) 51 #define EMIT4_off32(b1, b2, b3, b4, off) \ 52 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0) 53 54 #ifdef CONFIG_X86_KERNEL_IBT 55 #define EMIT_ENDBR() EMIT(gen_endbr(), 4) 56 #define EMIT_ENDBR_POISON() EMIT(gen_endbr_poison(), 4) 57 #else 58 #define EMIT_ENDBR() 59 #define EMIT_ENDBR_POISON() 60 #endif 61 62 static bool is_imm8(int value) 63 { 64 return value <= 127 && value >= -128; 65 } 66 67 static bool is_simm32(s64 value) 68 { 69 return value == (s64)(s32)value; 70 } 71 72 static bool is_uimm32(u64 value) 73 { 74 return value == (u64)(u32)value; 75 } 76 77 /* mov dst, src */ 78 #define EMIT_mov(DST, SRC) \ 79 do { \ 80 if (DST != SRC) \ 81 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \ 82 } while (0) 83 84 static int bpf_size_to_x86_bytes(int bpf_size) 85 { 86 if (bpf_size == BPF_W) 87 return 4; 88 else if (bpf_size == BPF_H) 89 return 2; 90 else if (bpf_size == BPF_B) 91 return 1; 92 else if (bpf_size == BPF_DW) 93 return 4; /* imm32 */ 94 else 95 return 0; 96 } 97 98 /* 99 * List of x86 cond jumps opcodes (. + s8) 100 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32) 101 */ 102 #define X86_JB 0x72 103 #define X86_JAE 0x73 104 #define X86_JE 0x74 105 #define X86_JNE 0x75 106 #define X86_JBE 0x76 107 #define X86_JA 0x77 108 #define X86_JL 0x7C 109 #define X86_JGE 0x7D 110 #define X86_JLE 0x7E 111 #define X86_JG 0x7F 112 113 /* Pick a register outside of BPF range for JIT internal work */ 114 #define AUX_REG (MAX_BPF_JIT_REG + 1) 115 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2) 116 #define X86_REG_R12 (MAX_BPF_JIT_REG + 3) 117 118 /* 119 * The following table maps BPF registers to x86-64 registers. 120 * 121 * x86-64 register R12 is unused, since if used as base address 122 * register in load/store instructions, it always needs an 123 * extra byte of encoding and is callee saved. 124 * 125 * x86-64 register R9 is not used by BPF programs, but can be used by BPF 126 * trampoline. x86-64 register R10 is used for blinding (if enabled). 127 */ 128 static const int reg2hex[] = { 129 [BPF_REG_0] = 0, /* RAX */ 130 [BPF_REG_1] = 7, /* RDI */ 131 [BPF_REG_2] = 6, /* RSI */ 132 [BPF_REG_3] = 2, /* RDX */ 133 [BPF_REG_4] = 1, /* RCX */ 134 [BPF_REG_5] = 0, /* R8 */ 135 [BPF_REG_6] = 3, /* RBX callee saved */ 136 [BPF_REG_7] = 5, /* R13 callee saved */ 137 [BPF_REG_8] = 6, /* R14 callee saved */ 138 [BPF_REG_9] = 7, /* R15 callee saved */ 139 [BPF_REG_FP] = 5, /* RBP readonly */ 140 [BPF_REG_AX] = 2, /* R10 temp register */ 141 [AUX_REG] = 3, /* R11 temp register */ 142 [X86_REG_R9] = 1, /* R9 register, 6th function argument */ 143 [X86_REG_R12] = 4, /* R12 callee saved */ 144 }; 145 146 static const int reg2pt_regs[] = { 147 [BPF_REG_0] = offsetof(struct pt_regs, ax), 148 [BPF_REG_1] = offsetof(struct pt_regs, di), 149 [BPF_REG_2] = offsetof(struct pt_regs, si), 150 [BPF_REG_3] = offsetof(struct pt_regs, dx), 151 [BPF_REG_4] = offsetof(struct pt_regs, cx), 152 [BPF_REG_5] = offsetof(struct pt_regs, r8), 153 [BPF_REG_6] = offsetof(struct pt_regs, bx), 154 [BPF_REG_7] = offsetof(struct pt_regs, r13), 155 [BPF_REG_8] = offsetof(struct pt_regs, r14), 156 [BPF_REG_9] = offsetof(struct pt_regs, r15), 157 }; 158 159 /* 160 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15 161 * which need extra byte of encoding. 162 * rax,rcx,...,rbp have simpler encoding 163 */ 164 static bool is_ereg(u32 reg) 165 { 166 return (1 << reg) & (BIT(BPF_REG_5) | 167 BIT(AUX_REG) | 168 BIT(BPF_REG_7) | 169 BIT(BPF_REG_8) | 170 BIT(BPF_REG_9) | 171 BIT(X86_REG_R9) | 172 BIT(X86_REG_R12) | 173 BIT(BPF_REG_AX)); 174 } 175 176 /* 177 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64 178 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte 179 * of encoding. al,cl,dl,bl have simpler encoding. 180 */ 181 static bool is_ereg_8l(u32 reg) 182 { 183 return is_ereg(reg) || 184 (1 << reg) & (BIT(BPF_REG_1) | 185 BIT(BPF_REG_2) | 186 BIT(BPF_REG_FP)); 187 } 188 189 static bool is_axreg(u32 reg) 190 { 191 return reg == BPF_REG_0; 192 } 193 194 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */ 195 static u8 add_1mod(u8 byte, u32 reg) 196 { 197 if (is_ereg(reg)) 198 byte |= 1; 199 return byte; 200 } 201 202 static u8 add_2mod(u8 byte, u32 r1, u32 r2) 203 { 204 if (is_ereg(r1)) 205 byte |= 1; 206 if (is_ereg(r2)) 207 byte |= 4; 208 return byte; 209 } 210 211 static u8 add_3mod(u8 byte, u32 r1, u32 r2, u32 index) 212 { 213 if (is_ereg(r1)) 214 byte |= 1; 215 if (is_ereg(index)) 216 byte |= 2; 217 if (is_ereg(r2)) 218 byte |= 4; 219 return byte; 220 } 221 222 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */ 223 static u8 add_1reg(u8 byte, u32 dst_reg) 224 { 225 return byte + reg2hex[dst_reg]; 226 } 227 228 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */ 229 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg) 230 { 231 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3); 232 } 233 234 /* Some 1-byte opcodes for binary ALU operations */ 235 static u8 simple_alu_opcodes[] = { 236 [BPF_ADD] = 0x01, 237 [BPF_SUB] = 0x29, 238 [BPF_AND] = 0x21, 239 [BPF_OR] = 0x09, 240 [BPF_XOR] = 0x31, 241 [BPF_LSH] = 0xE0, 242 [BPF_RSH] = 0xE8, 243 [BPF_ARSH] = 0xF8, 244 }; 245 246 static void jit_fill_hole(void *area, unsigned int size) 247 { 248 /* Fill whole space with INT3 instructions */ 249 memset(area, 0xcc, size); 250 } 251 252 int bpf_arch_text_invalidate(void *dst, size_t len) 253 { 254 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len)); 255 } 256 257 struct jit_context { 258 int cleanup_addr; /* Epilogue code offset */ 259 260 /* 261 * Program specific offsets of labels in the code; these rely on the 262 * JIT doing at least 2 passes, recording the position on the first 263 * pass, only to generate the correct offset on the second pass. 264 */ 265 int tail_call_direct_label; 266 int tail_call_indirect_label; 267 }; 268 269 /* Maximum number of bytes emitted while JITing one eBPF insn */ 270 #define BPF_MAX_INSN_SIZE 128 271 #define BPF_INSN_SAFETY 64 272 273 /* Number of bytes emit_patch() needs to generate instructions */ 274 #define X86_PATCH_SIZE 5 275 /* Number of bytes that will be skipped on tailcall */ 276 #define X86_TAIL_CALL_OFFSET (11 + ENDBR_INSN_SIZE) 277 278 static void push_r12(u8 **pprog) 279 { 280 u8 *prog = *pprog; 281 282 EMIT2(0x41, 0x54); /* push r12 */ 283 *pprog = prog; 284 } 285 286 static void push_callee_regs(u8 **pprog, bool *callee_regs_used) 287 { 288 u8 *prog = *pprog; 289 290 if (callee_regs_used[0]) 291 EMIT1(0x53); /* push rbx */ 292 if (callee_regs_used[1]) 293 EMIT2(0x41, 0x55); /* push r13 */ 294 if (callee_regs_used[2]) 295 EMIT2(0x41, 0x56); /* push r14 */ 296 if (callee_regs_used[3]) 297 EMIT2(0x41, 0x57); /* push r15 */ 298 *pprog = prog; 299 } 300 301 static void pop_r12(u8 **pprog) 302 { 303 u8 *prog = *pprog; 304 305 EMIT2(0x41, 0x5C); /* pop r12 */ 306 *pprog = prog; 307 } 308 309 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used) 310 { 311 u8 *prog = *pprog; 312 313 if (callee_regs_used[3]) 314 EMIT2(0x41, 0x5F); /* pop r15 */ 315 if (callee_regs_used[2]) 316 EMIT2(0x41, 0x5E); /* pop r14 */ 317 if (callee_regs_used[1]) 318 EMIT2(0x41, 0x5D); /* pop r13 */ 319 if (callee_regs_used[0]) 320 EMIT1(0x5B); /* pop rbx */ 321 *pprog = prog; 322 } 323 324 static void emit_nops(u8 **pprog, int len) 325 { 326 u8 *prog = *pprog; 327 int i, noplen; 328 329 while (len > 0) { 330 noplen = len; 331 332 if (noplen > ASM_NOP_MAX) 333 noplen = ASM_NOP_MAX; 334 335 for (i = 0; i < noplen; i++) 336 EMIT1(x86_nops[noplen][i]); 337 len -= noplen; 338 } 339 340 *pprog = prog; 341 } 342 343 /* 344 * Emit the various CFI preambles, see asm/cfi.h and the comments about FineIBT 345 * in arch/x86/kernel/alternative.c 346 */ 347 348 static void emit_fineibt(u8 **pprog, u32 hash) 349 { 350 u8 *prog = *pprog; 351 352 EMIT_ENDBR(); 353 EMIT3_off32(0x41, 0x81, 0xea, hash); /* subl $hash, %r10d */ 354 EMIT2(0x74, 0x07); /* jz.d8 +7 */ 355 EMIT2(0x0f, 0x0b); /* ud2 */ 356 EMIT1(0x90); /* nop */ 357 EMIT_ENDBR_POISON(); 358 359 *pprog = prog; 360 } 361 362 static void emit_kcfi(u8 **pprog, u32 hash) 363 { 364 u8 *prog = *pprog; 365 366 EMIT1_off32(0xb8, hash); /* movl $hash, %eax */ 367 #ifdef CONFIG_CALL_PADDING 368 EMIT1(0x90); 369 EMIT1(0x90); 370 EMIT1(0x90); 371 EMIT1(0x90); 372 EMIT1(0x90); 373 EMIT1(0x90); 374 EMIT1(0x90); 375 EMIT1(0x90); 376 EMIT1(0x90); 377 EMIT1(0x90); 378 EMIT1(0x90); 379 #endif 380 EMIT_ENDBR(); 381 382 *pprog = prog; 383 } 384 385 static void emit_cfi(u8 **pprog, u32 hash) 386 { 387 u8 *prog = *pprog; 388 389 switch (cfi_mode) { 390 case CFI_FINEIBT: 391 emit_fineibt(&prog, hash); 392 break; 393 394 case CFI_KCFI: 395 emit_kcfi(&prog, hash); 396 break; 397 398 default: 399 EMIT_ENDBR(); 400 break; 401 } 402 403 *pprog = prog; 404 } 405 406 /* 407 * Emit x86-64 prologue code for BPF program. 408 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes 409 * while jumping to another program 410 */ 411 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf, 412 bool tail_call_reachable, bool is_subprog, 413 bool is_exception_cb) 414 { 415 u8 *prog = *pprog; 416 417 emit_cfi(&prog, is_subprog ? cfi_bpf_subprog_hash : cfi_bpf_hash); 418 /* BPF trampoline can be made to work without these nops, 419 * but let's waste 5 bytes for now and optimize later 420 */ 421 emit_nops(&prog, X86_PATCH_SIZE); 422 if (!ebpf_from_cbpf) { 423 if (tail_call_reachable && !is_subprog) 424 /* When it's the entry of the whole tailcall context, 425 * zeroing rax means initialising tail_call_cnt. 426 */ 427 EMIT2(0x31, 0xC0); /* xor eax, eax */ 428 else 429 /* Keep the same instruction layout. */ 430 EMIT2(0x66, 0x90); /* nop2 */ 431 } 432 /* Exception callback receives FP as third parameter */ 433 if (is_exception_cb) { 434 EMIT3(0x48, 0x89, 0xF4); /* mov rsp, rsi */ 435 EMIT3(0x48, 0x89, 0xD5); /* mov rbp, rdx */ 436 /* The main frame must have exception_boundary as true, so we 437 * first restore those callee-saved regs from stack, before 438 * reusing the stack frame. 439 */ 440 pop_callee_regs(&prog, all_callee_regs_used); 441 pop_r12(&prog); 442 /* Reset the stack frame. */ 443 EMIT3(0x48, 0x89, 0xEC); /* mov rsp, rbp */ 444 } else { 445 EMIT1(0x55); /* push rbp */ 446 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 447 } 448 449 /* X86_TAIL_CALL_OFFSET is here */ 450 EMIT_ENDBR(); 451 452 /* sub rsp, rounded_stack_depth */ 453 if (stack_depth) 454 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8)); 455 if (tail_call_reachable) 456 EMIT1(0x50); /* push rax */ 457 *pprog = prog; 458 } 459 460 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode) 461 { 462 u8 *prog = *pprog; 463 s64 offset; 464 465 offset = func - (ip + X86_PATCH_SIZE); 466 if (!is_simm32(offset)) { 467 pr_err("Target call %p is out of range\n", func); 468 return -ERANGE; 469 } 470 EMIT1_off32(opcode, offset); 471 *pprog = prog; 472 return 0; 473 } 474 475 static int emit_call(u8 **pprog, void *func, void *ip) 476 { 477 return emit_patch(pprog, func, ip, 0xE8); 478 } 479 480 static int emit_rsb_call(u8 **pprog, void *func, void *ip) 481 { 482 OPTIMIZER_HIDE_VAR(func); 483 x86_call_depth_emit_accounting(pprog, func); 484 return emit_patch(pprog, func, ip, 0xE8); 485 } 486 487 static int emit_jump(u8 **pprog, void *func, void *ip) 488 { 489 return emit_patch(pprog, func, ip, 0xE9); 490 } 491 492 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 493 void *old_addr, void *new_addr) 494 { 495 const u8 *nop_insn = x86_nops[5]; 496 u8 old_insn[X86_PATCH_SIZE]; 497 u8 new_insn[X86_PATCH_SIZE]; 498 u8 *prog; 499 int ret; 500 501 memcpy(old_insn, nop_insn, X86_PATCH_SIZE); 502 if (old_addr) { 503 prog = old_insn; 504 ret = t == BPF_MOD_CALL ? 505 emit_call(&prog, old_addr, ip) : 506 emit_jump(&prog, old_addr, ip); 507 if (ret) 508 return ret; 509 } 510 511 memcpy(new_insn, nop_insn, X86_PATCH_SIZE); 512 if (new_addr) { 513 prog = new_insn; 514 ret = t == BPF_MOD_CALL ? 515 emit_call(&prog, new_addr, ip) : 516 emit_jump(&prog, new_addr, ip); 517 if (ret) 518 return ret; 519 } 520 521 ret = -EBUSY; 522 mutex_lock(&text_mutex); 523 if (memcmp(ip, old_insn, X86_PATCH_SIZE)) 524 goto out; 525 ret = 1; 526 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) { 527 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL); 528 ret = 0; 529 } 530 out: 531 mutex_unlock(&text_mutex); 532 return ret; 533 } 534 535 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 536 void *old_addr, void *new_addr) 537 { 538 if (!is_kernel_text((long)ip) && 539 !is_bpf_text_address((long)ip)) 540 /* BPF poking in modules is not supported */ 541 return -EINVAL; 542 543 /* 544 * See emit_prologue(), for IBT builds the trampoline hook is preceded 545 * with an ENDBR instruction. 546 */ 547 if (is_endbr(*(u32 *)ip)) 548 ip += ENDBR_INSN_SIZE; 549 550 return __bpf_arch_text_poke(ip, t, old_addr, new_addr); 551 } 552 553 #define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8) 554 555 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip) 556 { 557 u8 *prog = *pprog; 558 559 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 560 EMIT_LFENCE(); 561 EMIT2(0xFF, 0xE0 + reg); 562 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) { 563 OPTIMIZER_HIDE_VAR(reg); 564 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH)) 565 emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip); 566 else 567 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip); 568 } else { 569 EMIT2(0xFF, 0xE0 + reg); /* jmp *%\reg */ 570 if (IS_ENABLED(CONFIG_MITIGATION_RETPOLINE) || IS_ENABLED(CONFIG_MITIGATION_SLS)) 571 EMIT1(0xCC); /* int3 */ 572 } 573 574 *pprog = prog; 575 } 576 577 static void emit_return(u8 **pprog, u8 *ip) 578 { 579 u8 *prog = *pprog; 580 581 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) { 582 emit_jump(&prog, x86_return_thunk, ip); 583 } else { 584 EMIT1(0xC3); /* ret */ 585 if (IS_ENABLED(CONFIG_MITIGATION_SLS)) 586 EMIT1(0xCC); /* int3 */ 587 } 588 589 *pprog = prog; 590 } 591 592 /* 593 * Generate the following code: 594 * 595 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ... 596 * if (index >= array->map.max_entries) 597 * goto out; 598 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) 599 * goto out; 600 * prog = array->ptrs[index]; 601 * if (prog == NULL) 602 * goto out; 603 * goto *(prog->bpf_func + prologue_size); 604 * out: 605 */ 606 static void emit_bpf_tail_call_indirect(struct bpf_prog *bpf_prog, 607 u8 **pprog, bool *callee_regs_used, 608 u32 stack_depth, u8 *ip, 609 struct jit_context *ctx) 610 { 611 int tcc_off = -4 - round_up(stack_depth, 8); 612 u8 *prog = *pprog, *start = *pprog; 613 int offset; 614 615 /* 616 * rdi - pointer to ctx 617 * rsi - pointer to bpf_array 618 * rdx - index in bpf_array 619 */ 620 621 /* 622 * if (index >= array->map.max_entries) 623 * goto out; 624 */ 625 EMIT2(0x89, 0xD2); /* mov edx, edx */ 626 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */ 627 offsetof(struct bpf_array, map.max_entries)); 628 629 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 630 EMIT2(X86_JBE, offset); /* jbe out */ 631 632 /* 633 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) 634 * goto out; 635 */ 636 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ 637 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ 638 639 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 640 EMIT2(X86_JAE, offset); /* jae out */ 641 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ 642 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ 643 644 /* prog = array->ptrs[index]; */ 645 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */ 646 offsetof(struct bpf_array, ptrs)); 647 648 /* 649 * if (prog == NULL) 650 * goto out; 651 */ 652 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */ 653 654 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 655 EMIT2(X86_JE, offset); /* je out */ 656 657 if (bpf_prog->aux->exception_boundary) { 658 pop_callee_regs(&prog, all_callee_regs_used); 659 pop_r12(&prog); 660 } else { 661 pop_callee_regs(&prog, callee_regs_used); 662 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena)) 663 pop_r12(&prog); 664 } 665 666 EMIT1(0x58); /* pop rax */ 667 if (stack_depth) 668 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */ 669 round_up(stack_depth, 8)); 670 671 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */ 672 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */ 673 offsetof(struct bpf_prog, bpf_func)); 674 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */ 675 X86_TAIL_CALL_OFFSET); 676 /* 677 * Now we're ready to jump into next BPF program 678 * rdi == ctx (1st arg) 679 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET 680 */ 681 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start)); 682 683 /* out: */ 684 ctx->tail_call_indirect_label = prog - start; 685 *pprog = prog; 686 } 687 688 static void emit_bpf_tail_call_direct(struct bpf_prog *bpf_prog, 689 struct bpf_jit_poke_descriptor *poke, 690 u8 **pprog, u8 *ip, 691 bool *callee_regs_used, u32 stack_depth, 692 struct jit_context *ctx) 693 { 694 int tcc_off = -4 - round_up(stack_depth, 8); 695 u8 *prog = *pprog, *start = *pprog; 696 int offset; 697 698 /* 699 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT) 700 * goto out; 701 */ 702 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */ 703 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */ 704 705 offset = ctx->tail_call_direct_label - (prog + 2 - start); 706 EMIT2(X86_JAE, offset); /* jae out */ 707 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */ 708 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */ 709 710 poke->tailcall_bypass = ip + (prog - start); 711 poke->adj_off = X86_TAIL_CALL_OFFSET; 712 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE; 713 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE; 714 715 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE, 716 poke->tailcall_bypass); 717 718 if (bpf_prog->aux->exception_boundary) { 719 pop_callee_regs(&prog, all_callee_regs_used); 720 pop_r12(&prog); 721 } else { 722 pop_callee_regs(&prog, callee_regs_used); 723 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena)) 724 pop_r12(&prog); 725 } 726 727 EMIT1(0x58); /* pop rax */ 728 if (stack_depth) 729 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8)); 730 731 emit_nops(&prog, X86_PATCH_SIZE); 732 733 /* out: */ 734 ctx->tail_call_direct_label = prog - start; 735 736 *pprog = prog; 737 } 738 739 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog) 740 { 741 struct bpf_jit_poke_descriptor *poke; 742 struct bpf_array *array; 743 struct bpf_prog *target; 744 int i, ret; 745 746 for (i = 0; i < prog->aux->size_poke_tab; i++) { 747 poke = &prog->aux->poke_tab[i]; 748 if (poke->aux && poke->aux != prog->aux) 749 continue; 750 751 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable)); 752 753 if (poke->reason != BPF_POKE_REASON_TAIL_CALL) 754 continue; 755 756 array = container_of(poke->tail_call.map, struct bpf_array, map); 757 mutex_lock(&array->aux->poke_mutex); 758 target = array->ptrs[poke->tail_call.key]; 759 if (target) { 760 ret = __bpf_arch_text_poke(poke->tailcall_target, 761 BPF_MOD_JUMP, NULL, 762 (u8 *)target->bpf_func + 763 poke->adj_off); 764 BUG_ON(ret < 0); 765 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 766 BPF_MOD_JUMP, 767 (u8 *)poke->tailcall_target + 768 X86_PATCH_SIZE, NULL); 769 BUG_ON(ret < 0); 770 } 771 WRITE_ONCE(poke->tailcall_target_stable, true); 772 mutex_unlock(&array->aux->poke_mutex); 773 } 774 } 775 776 static void emit_mov_imm32(u8 **pprog, bool sign_propagate, 777 u32 dst_reg, const u32 imm32) 778 { 779 u8 *prog = *pprog; 780 u8 b1, b2, b3; 781 782 /* 783 * Optimization: if imm32 is positive, use 'mov %eax, imm32' 784 * (which zero-extends imm32) to save 2 bytes. 785 */ 786 if (sign_propagate && (s32)imm32 < 0) { 787 /* 'mov %rax, imm32' sign extends imm32 */ 788 b1 = add_1mod(0x48, dst_reg); 789 b2 = 0xC7; 790 b3 = 0xC0; 791 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32); 792 goto done; 793 } 794 795 /* 796 * Optimization: if imm32 is zero, use 'xor %eax, %eax' 797 * to save 3 bytes. 798 */ 799 if (imm32 == 0) { 800 if (is_ereg(dst_reg)) 801 EMIT1(add_2mod(0x40, dst_reg, dst_reg)); 802 b2 = 0x31; /* xor */ 803 b3 = 0xC0; 804 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg)); 805 goto done; 806 } 807 808 /* mov %eax, imm32 */ 809 if (is_ereg(dst_reg)) 810 EMIT1(add_1mod(0x40, dst_reg)); 811 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32); 812 done: 813 *pprog = prog; 814 } 815 816 static void emit_mov_imm64(u8 **pprog, u32 dst_reg, 817 const u32 imm32_hi, const u32 imm32_lo) 818 { 819 u64 imm64 = ((u64)imm32_hi << 32) | (u32)imm32_lo; 820 u8 *prog = *pprog; 821 822 if (is_uimm32(imm64)) { 823 /* 824 * For emitting plain u32, where sign bit must not be 825 * propagated LLVM tends to load imm64 over mov32 826 * directly, so save couple of bytes by just doing 827 * 'mov %eax, imm32' instead. 828 */ 829 emit_mov_imm32(&prog, false, dst_reg, imm32_lo); 830 } else if (is_simm32(imm64)) { 831 emit_mov_imm32(&prog, true, dst_reg, imm32_lo); 832 } else { 833 /* movabsq rax, imm64 */ 834 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg)); 835 EMIT(imm32_lo, 4); 836 EMIT(imm32_hi, 4); 837 } 838 839 *pprog = prog; 840 } 841 842 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg) 843 { 844 u8 *prog = *pprog; 845 846 if (is64) { 847 /* mov dst, src */ 848 EMIT_mov(dst_reg, src_reg); 849 } else { 850 /* mov32 dst, src */ 851 if (is_ereg(dst_reg) || is_ereg(src_reg)) 852 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 853 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg)); 854 } 855 856 *pprog = prog; 857 } 858 859 static void emit_movsx_reg(u8 **pprog, int num_bits, bool is64, u32 dst_reg, 860 u32 src_reg) 861 { 862 u8 *prog = *pprog; 863 864 if (is64) { 865 /* movs[b,w,l]q dst, src */ 866 if (num_bits == 8) 867 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbe, 868 add_2reg(0xC0, src_reg, dst_reg)); 869 else if (num_bits == 16) 870 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbf, 871 add_2reg(0xC0, src_reg, dst_reg)); 872 else if (num_bits == 32) 873 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x63, 874 add_2reg(0xC0, src_reg, dst_reg)); 875 } else { 876 /* movs[b,w]l dst, src */ 877 if (num_bits == 8) { 878 EMIT4(add_2mod(0x40, src_reg, dst_reg), 0x0f, 0xbe, 879 add_2reg(0xC0, src_reg, dst_reg)); 880 } else if (num_bits == 16) { 881 if (is_ereg(dst_reg) || is_ereg(src_reg)) 882 EMIT1(add_2mod(0x40, src_reg, dst_reg)); 883 EMIT3(add_2mod(0x0f, src_reg, dst_reg), 0xbf, 884 add_2reg(0xC0, src_reg, dst_reg)); 885 } 886 } 887 888 *pprog = prog; 889 } 890 891 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */ 892 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off) 893 { 894 u8 *prog = *pprog; 895 896 if (is_imm8(off)) { 897 /* 1-byte signed displacement. 898 * 899 * If off == 0 we could skip this and save one extra byte, but 900 * special case of x86 R13 which always needs an offset is not 901 * worth the hassle 902 */ 903 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off); 904 } else { 905 /* 4-byte signed displacement */ 906 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off); 907 } 908 *pprog = prog; 909 } 910 911 static void emit_insn_suffix_SIB(u8 **pprog, u32 ptr_reg, u32 val_reg, u32 index_reg, int off) 912 { 913 u8 *prog = *pprog; 914 915 if (is_imm8(off)) { 916 EMIT3(add_2reg(0x44, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off); 917 } else { 918 EMIT2_off32(add_2reg(0x84, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off); 919 } 920 *pprog = prog; 921 } 922 923 /* 924 * Emit a REX byte if it will be necessary to address these registers 925 */ 926 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64) 927 { 928 u8 *prog = *pprog; 929 930 if (is64) 931 EMIT1(add_2mod(0x48, dst_reg, src_reg)); 932 else if (is_ereg(dst_reg) || is_ereg(src_reg)) 933 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 934 *pprog = prog; 935 } 936 937 /* 938 * Similar version of maybe_emit_mod() for a single register 939 */ 940 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64) 941 { 942 u8 *prog = *pprog; 943 944 if (is64) 945 EMIT1(add_1mod(0x48, reg)); 946 else if (is_ereg(reg)) 947 EMIT1(add_1mod(0x40, reg)); 948 *pprog = prog; 949 } 950 951 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 952 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 953 { 954 u8 *prog = *pprog; 955 956 switch (size) { 957 case BPF_B: 958 /* Emit 'movzx rax, byte ptr [rax + off]' */ 959 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6); 960 break; 961 case BPF_H: 962 /* Emit 'movzx rax, word ptr [rax + off]' */ 963 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7); 964 break; 965 case BPF_W: 966 /* Emit 'mov eax, dword ptr [rax+0x14]' */ 967 if (is_ereg(dst_reg) || is_ereg(src_reg)) 968 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B); 969 else 970 EMIT1(0x8B); 971 break; 972 case BPF_DW: 973 /* Emit 'mov rax, qword ptr [rax+0x14]' */ 974 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B); 975 break; 976 } 977 emit_insn_suffix(&prog, src_reg, dst_reg, off); 978 *pprog = prog; 979 } 980 981 /* LDSX: dst_reg = *(s8*)(src_reg + off) */ 982 static void emit_ldsx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 983 { 984 u8 *prog = *pprog; 985 986 switch (size) { 987 case BPF_B: 988 /* Emit 'movsx rax, byte ptr [rax + off]' */ 989 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBE); 990 break; 991 case BPF_H: 992 /* Emit 'movsx rax, word ptr [rax + off]' */ 993 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBF); 994 break; 995 case BPF_W: 996 /* Emit 'movsx rax, dword ptr [rax+0x14]' */ 997 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x63); 998 break; 999 } 1000 emit_insn_suffix(&prog, src_reg, dst_reg, off); 1001 *pprog = prog; 1002 } 1003 1004 static void emit_ldx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1005 { 1006 u8 *prog = *pprog; 1007 1008 switch (size) { 1009 case BPF_B: 1010 /* movzx rax, byte ptr [rax + r12 + off] */ 1011 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB6); 1012 break; 1013 case BPF_H: 1014 /* movzx rax, word ptr [rax + r12 + off] */ 1015 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB7); 1016 break; 1017 case BPF_W: 1018 /* mov eax, dword ptr [rax + r12 + off] */ 1019 EMIT2(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x8B); 1020 break; 1021 case BPF_DW: 1022 /* mov rax, qword ptr [rax + r12 + off] */ 1023 EMIT2(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x8B); 1024 break; 1025 } 1026 emit_insn_suffix_SIB(&prog, src_reg, dst_reg, index_reg, off); 1027 *pprog = prog; 1028 } 1029 1030 static void emit_ldx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1031 { 1032 emit_ldx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off); 1033 } 1034 1035 /* STX: *(u8*)(dst_reg + off) = src_reg */ 1036 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1037 { 1038 u8 *prog = *pprog; 1039 1040 switch (size) { 1041 case BPF_B: 1042 /* Emit 'mov byte ptr [rax + off], al' */ 1043 if (is_ereg(dst_reg) || is_ereg_8l(src_reg)) 1044 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */ 1045 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88); 1046 else 1047 EMIT1(0x88); 1048 break; 1049 case BPF_H: 1050 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1051 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89); 1052 else 1053 EMIT2(0x66, 0x89); 1054 break; 1055 case BPF_W: 1056 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1057 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89); 1058 else 1059 EMIT1(0x89); 1060 break; 1061 case BPF_DW: 1062 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89); 1063 break; 1064 } 1065 emit_insn_suffix(&prog, dst_reg, src_reg, off); 1066 *pprog = prog; 1067 } 1068 1069 /* STX: *(u8*)(dst_reg + index_reg + off) = src_reg */ 1070 static void emit_stx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1071 { 1072 u8 *prog = *pprog; 1073 1074 switch (size) { 1075 case BPF_B: 1076 /* mov byte ptr [rax + r12 + off], al */ 1077 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x88); 1078 break; 1079 case BPF_H: 1080 /* mov word ptr [rax + r12 + off], ax */ 1081 EMIT3(0x66, add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89); 1082 break; 1083 case BPF_W: 1084 /* mov dword ptr [rax + r12 + 1], eax */ 1085 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89); 1086 break; 1087 case BPF_DW: 1088 /* mov qword ptr [rax + r12 + 1], rax */ 1089 EMIT2(add_3mod(0x48, dst_reg, src_reg, index_reg), 0x89); 1090 break; 1091 } 1092 emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off); 1093 *pprog = prog; 1094 } 1095 1096 static void emit_stx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1097 { 1098 emit_stx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off); 1099 } 1100 1101 /* ST: *(u8*)(dst_reg + index_reg + off) = imm32 */ 1102 static void emit_st_index(u8 **pprog, u32 size, u32 dst_reg, u32 index_reg, int off, int imm) 1103 { 1104 u8 *prog = *pprog; 1105 1106 switch (size) { 1107 case BPF_B: 1108 /* mov byte ptr [rax + r12 + off], imm8 */ 1109 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC6); 1110 break; 1111 case BPF_H: 1112 /* mov word ptr [rax + r12 + off], imm16 */ 1113 EMIT3(0x66, add_3mod(0x40, dst_reg, 0, index_reg), 0xC7); 1114 break; 1115 case BPF_W: 1116 /* mov dword ptr [rax + r12 + 1], imm32 */ 1117 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC7); 1118 break; 1119 case BPF_DW: 1120 /* mov qword ptr [rax + r12 + 1], imm32 */ 1121 EMIT2(add_3mod(0x48, dst_reg, 0, index_reg), 0xC7); 1122 break; 1123 } 1124 emit_insn_suffix_SIB(&prog, dst_reg, 0, index_reg, off); 1125 EMIT(imm, bpf_size_to_x86_bytes(size)); 1126 *pprog = prog; 1127 } 1128 1129 static void emit_st_r12(u8 **pprog, u32 size, u32 dst_reg, int off, int imm) 1130 { 1131 emit_st_index(pprog, size, dst_reg, X86_REG_R12, off, imm); 1132 } 1133 1134 static int emit_atomic(u8 **pprog, u8 atomic_op, 1135 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size) 1136 { 1137 u8 *prog = *pprog; 1138 1139 EMIT1(0xF0); /* lock prefix */ 1140 1141 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW); 1142 1143 /* emit opcode */ 1144 switch (atomic_op) { 1145 case BPF_ADD: 1146 case BPF_AND: 1147 case BPF_OR: 1148 case BPF_XOR: 1149 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */ 1150 EMIT1(simple_alu_opcodes[atomic_op]); 1151 break; 1152 case BPF_ADD | BPF_FETCH: 1153 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */ 1154 EMIT2(0x0F, 0xC1); 1155 break; 1156 case BPF_XCHG: 1157 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 1158 EMIT1(0x87); 1159 break; 1160 case BPF_CMPXCHG: 1161 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 1162 EMIT2(0x0F, 0xB1); 1163 break; 1164 default: 1165 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 1166 return -EFAULT; 1167 } 1168 1169 emit_insn_suffix(&prog, dst_reg, src_reg, off); 1170 1171 *pprog = prog; 1172 return 0; 1173 } 1174 1175 static int emit_atomic_index(u8 **pprog, u8 atomic_op, u32 size, 1176 u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1177 { 1178 u8 *prog = *pprog; 1179 1180 EMIT1(0xF0); /* lock prefix */ 1181 switch (size) { 1182 case BPF_W: 1183 EMIT1(add_3mod(0x40, dst_reg, src_reg, index_reg)); 1184 break; 1185 case BPF_DW: 1186 EMIT1(add_3mod(0x48, dst_reg, src_reg, index_reg)); 1187 break; 1188 default: 1189 pr_err("bpf_jit: 1 and 2 byte atomics are not supported\n"); 1190 return -EFAULT; 1191 } 1192 1193 /* emit opcode */ 1194 switch (atomic_op) { 1195 case BPF_ADD: 1196 case BPF_AND: 1197 case BPF_OR: 1198 case BPF_XOR: 1199 /* lock *(u32/u64*)(dst_reg + idx_reg + off) <op>= src_reg */ 1200 EMIT1(simple_alu_opcodes[atomic_op]); 1201 break; 1202 case BPF_ADD | BPF_FETCH: 1203 /* src_reg = atomic_fetch_add(dst_reg + idx_reg + off, src_reg); */ 1204 EMIT2(0x0F, 0xC1); 1205 break; 1206 case BPF_XCHG: 1207 /* src_reg = atomic_xchg(dst_reg + idx_reg + off, src_reg); */ 1208 EMIT1(0x87); 1209 break; 1210 case BPF_CMPXCHG: 1211 /* r0 = atomic_cmpxchg(dst_reg + idx_reg + off, r0, src_reg); */ 1212 EMIT2(0x0F, 0xB1); 1213 break; 1214 default: 1215 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 1216 return -EFAULT; 1217 } 1218 emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off); 1219 *pprog = prog; 1220 return 0; 1221 } 1222 1223 #define DONT_CLEAR 1 1224 1225 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs) 1226 { 1227 u32 reg = x->fixup >> 8; 1228 1229 /* jump over faulting load and clear dest register */ 1230 if (reg != DONT_CLEAR) 1231 *(unsigned long *)((void *)regs + reg) = 0; 1232 regs->ip += x->fixup & 0xff; 1233 return true; 1234 } 1235 1236 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt, 1237 bool *regs_used, bool *tail_call_seen) 1238 { 1239 int i; 1240 1241 for (i = 1; i <= insn_cnt; i++, insn++) { 1242 if (insn->code == (BPF_JMP | BPF_TAIL_CALL)) 1243 *tail_call_seen = true; 1244 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) 1245 regs_used[0] = true; 1246 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) 1247 regs_used[1] = true; 1248 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) 1249 regs_used[2] = true; 1250 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) 1251 regs_used[3] = true; 1252 } 1253 } 1254 1255 /* emit the 3-byte VEX prefix 1256 * 1257 * r: same as rex.r, extra bit for ModRM reg field 1258 * x: same as rex.x, extra bit for SIB index field 1259 * b: same as rex.b, extra bit for ModRM r/m, or SIB base 1260 * m: opcode map select, encoding escape bytes e.g. 0x0f38 1261 * w: same as rex.w (32 bit or 64 bit) or opcode specific 1262 * src_reg2: additional source reg (encoded as BPF reg) 1263 * l: vector length (128 bit or 256 bit) or reserved 1264 * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3) 1265 */ 1266 static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m, 1267 bool w, u8 src_reg2, bool l, u8 pp) 1268 { 1269 u8 *prog = *pprog; 1270 const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */ 1271 u8 b1, b2; 1272 u8 vvvv = reg2hex[src_reg2]; 1273 1274 /* reg2hex gives only the lower 3 bit of vvvv */ 1275 if (is_ereg(src_reg2)) 1276 vvvv |= 1 << 3; 1277 1278 /* 1279 * 2nd byte of 3-byte VEX prefix 1280 * ~ means bit inverted encoding 1281 * 1282 * 7 0 1283 * +---+---+---+---+---+---+---+---+ 1284 * |~R |~X |~B | m | 1285 * +---+---+---+---+---+---+---+---+ 1286 */ 1287 b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f); 1288 /* 1289 * 3rd byte of 3-byte VEX prefix 1290 * 1291 * 7 0 1292 * +---+---+---+---+---+---+---+---+ 1293 * | W | ~vvvv | L | pp | 1294 * +---+---+---+---+---+---+---+---+ 1295 */ 1296 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3); 1297 1298 EMIT3(b0, b1, b2); 1299 *pprog = prog; 1300 } 1301 1302 /* emit BMI2 shift instruction */ 1303 static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op) 1304 { 1305 u8 *prog = *pprog; 1306 bool r = is_ereg(dst_reg); 1307 u8 m = 2; /* escape code 0f38 */ 1308 1309 emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op); 1310 EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg)); 1311 *pprog = prog; 1312 } 1313 1314 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp))) 1315 1316 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */ 1317 #define RESTORE_TAIL_CALL_CNT(stack) \ 1318 EMIT3_off32(0x48, 0x8B, 0x85, -round_up(stack, 8) - 8) 1319 1320 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image, 1321 int oldproglen, struct jit_context *ctx, bool jmp_padding) 1322 { 1323 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable; 1324 struct bpf_insn *insn = bpf_prog->insnsi; 1325 bool callee_regs_used[4] = {}; 1326 int insn_cnt = bpf_prog->len; 1327 bool tail_call_seen = false; 1328 bool seen_exit = false; 1329 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY]; 1330 u64 arena_vm_start, user_vm_start; 1331 int i, excnt = 0; 1332 int ilen, proglen = 0; 1333 u8 *prog = temp; 1334 int err; 1335 1336 arena_vm_start = bpf_arena_get_kern_vm_start(bpf_prog->aux->arena); 1337 user_vm_start = bpf_arena_get_user_vm_start(bpf_prog->aux->arena); 1338 1339 detect_reg_usage(insn, insn_cnt, callee_regs_used, 1340 &tail_call_seen); 1341 1342 /* tail call's presence in current prog implies it is reachable */ 1343 tail_call_reachable |= tail_call_seen; 1344 1345 emit_prologue(&prog, bpf_prog->aux->stack_depth, 1346 bpf_prog_was_classic(bpf_prog), tail_call_reachable, 1347 bpf_is_subprog(bpf_prog), bpf_prog->aux->exception_cb); 1348 /* Exception callback will clobber callee regs for its own use, and 1349 * restore the original callee regs from main prog's stack frame. 1350 */ 1351 if (bpf_prog->aux->exception_boundary) { 1352 /* We also need to save r12, which is not mapped to any BPF 1353 * register, as we throw after entry into the kernel, which may 1354 * overwrite r12. 1355 */ 1356 push_r12(&prog); 1357 push_callee_regs(&prog, all_callee_regs_used); 1358 } else { 1359 if (arena_vm_start) 1360 push_r12(&prog); 1361 push_callee_regs(&prog, callee_regs_used); 1362 } 1363 if (arena_vm_start) 1364 emit_mov_imm64(&prog, X86_REG_R12, 1365 arena_vm_start >> 32, (u32) arena_vm_start); 1366 1367 ilen = prog - temp; 1368 if (rw_image) 1369 memcpy(rw_image + proglen, temp, ilen); 1370 proglen += ilen; 1371 addrs[0] = proglen; 1372 prog = temp; 1373 1374 for (i = 1; i <= insn_cnt; i++, insn++) { 1375 const s32 imm32 = insn->imm; 1376 u32 dst_reg = insn->dst_reg; 1377 u32 src_reg = insn->src_reg; 1378 u8 b2 = 0, b3 = 0; 1379 u8 *start_of_ldx; 1380 s64 jmp_offset; 1381 s16 insn_off; 1382 u8 jmp_cond; 1383 u8 *func; 1384 int nops; 1385 1386 switch (insn->code) { 1387 /* ALU */ 1388 case BPF_ALU | BPF_ADD | BPF_X: 1389 case BPF_ALU | BPF_SUB | BPF_X: 1390 case BPF_ALU | BPF_AND | BPF_X: 1391 case BPF_ALU | BPF_OR | BPF_X: 1392 case BPF_ALU | BPF_XOR | BPF_X: 1393 case BPF_ALU64 | BPF_ADD | BPF_X: 1394 case BPF_ALU64 | BPF_SUB | BPF_X: 1395 case BPF_ALU64 | BPF_AND | BPF_X: 1396 case BPF_ALU64 | BPF_OR | BPF_X: 1397 case BPF_ALU64 | BPF_XOR | BPF_X: 1398 maybe_emit_mod(&prog, dst_reg, src_reg, 1399 BPF_CLASS(insn->code) == BPF_ALU64); 1400 b2 = simple_alu_opcodes[BPF_OP(insn->code)]; 1401 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg)); 1402 break; 1403 1404 case BPF_ALU64 | BPF_MOV | BPF_X: 1405 if (insn_is_cast_user(insn)) { 1406 if (dst_reg != src_reg) 1407 /* 32-bit mov */ 1408 emit_mov_reg(&prog, false, dst_reg, src_reg); 1409 /* shl dst_reg, 32 */ 1410 maybe_emit_1mod(&prog, dst_reg, true); 1411 EMIT3(0xC1, add_1reg(0xE0, dst_reg), 32); 1412 1413 /* or dst_reg, user_vm_start */ 1414 maybe_emit_1mod(&prog, dst_reg, true); 1415 if (is_axreg(dst_reg)) 1416 EMIT1_off32(0x0D, user_vm_start >> 32); 1417 else 1418 EMIT2_off32(0x81, add_1reg(0xC8, dst_reg), user_vm_start >> 32); 1419 1420 /* rol dst_reg, 32 */ 1421 maybe_emit_1mod(&prog, dst_reg, true); 1422 EMIT3(0xC1, add_1reg(0xC0, dst_reg), 32); 1423 1424 /* xor r11, r11 */ 1425 EMIT3(0x4D, 0x31, 0xDB); 1426 1427 /* test dst_reg32, dst_reg32; check if lower 32-bit are zero */ 1428 maybe_emit_mod(&prog, dst_reg, dst_reg, false); 1429 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 1430 1431 /* cmove r11, dst_reg; if so, set dst_reg to zero */ 1432 /* WARNING: Intel swapped src/dst register encoding in CMOVcc !!! */ 1433 maybe_emit_mod(&prog, AUX_REG, dst_reg, true); 1434 EMIT3(0x0F, 0x44, add_2reg(0xC0, AUX_REG, dst_reg)); 1435 break; 1436 } else if (insn_is_mov_percpu_addr(insn)) { 1437 /* mov <dst>, <src> (if necessary) */ 1438 EMIT_mov(dst_reg, src_reg); 1439 #ifdef CONFIG_SMP 1440 /* add <dst>, gs:[<off>] */ 1441 EMIT2(0x65, add_1mod(0x48, dst_reg)); 1442 EMIT3(0x03, add_2reg(0x04, 0, dst_reg), 0x25); 1443 EMIT((u32)(unsigned long)&this_cpu_off, 4); 1444 #endif 1445 break; 1446 } 1447 fallthrough; 1448 case BPF_ALU | BPF_MOV | BPF_X: 1449 if (insn->off == 0) 1450 emit_mov_reg(&prog, 1451 BPF_CLASS(insn->code) == BPF_ALU64, 1452 dst_reg, src_reg); 1453 else 1454 emit_movsx_reg(&prog, insn->off, 1455 BPF_CLASS(insn->code) == BPF_ALU64, 1456 dst_reg, src_reg); 1457 break; 1458 1459 /* neg dst */ 1460 case BPF_ALU | BPF_NEG: 1461 case BPF_ALU64 | BPF_NEG: 1462 maybe_emit_1mod(&prog, dst_reg, 1463 BPF_CLASS(insn->code) == BPF_ALU64); 1464 EMIT2(0xF7, add_1reg(0xD8, dst_reg)); 1465 break; 1466 1467 case BPF_ALU | BPF_ADD | BPF_K: 1468 case BPF_ALU | BPF_SUB | BPF_K: 1469 case BPF_ALU | BPF_AND | BPF_K: 1470 case BPF_ALU | BPF_OR | BPF_K: 1471 case BPF_ALU | BPF_XOR | BPF_K: 1472 case BPF_ALU64 | BPF_ADD | BPF_K: 1473 case BPF_ALU64 | BPF_SUB | BPF_K: 1474 case BPF_ALU64 | BPF_AND | BPF_K: 1475 case BPF_ALU64 | BPF_OR | BPF_K: 1476 case BPF_ALU64 | BPF_XOR | BPF_K: 1477 maybe_emit_1mod(&prog, dst_reg, 1478 BPF_CLASS(insn->code) == BPF_ALU64); 1479 1480 /* 1481 * b3 holds 'normal' opcode, b2 short form only valid 1482 * in case dst is eax/rax. 1483 */ 1484 switch (BPF_OP(insn->code)) { 1485 case BPF_ADD: 1486 b3 = 0xC0; 1487 b2 = 0x05; 1488 break; 1489 case BPF_SUB: 1490 b3 = 0xE8; 1491 b2 = 0x2D; 1492 break; 1493 case BPF_AND: 1494 b3 = 0xE0; 1495 b2 = 0x25; 1496 break; 1497 case BPF_OR: 1498 b3 = 0xC8; 1499 b2 = 0x0D; 1500 break; 1501 case BPF_XOR: 1502 b3 = 0xF0; 1503 b2 = 0x35; 1504 break; 1505 } 1506 1507 if (is_imm8(imm32)) 1508 EMIT3(0x83, add_1reg(b3, dst_reg), imm32); 1509 else if (is_axreg(dst_reg)) 1510 EMIT1_off32(b2, imm32); 1511 else 1512 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32); 1513 break; 1514 1515 case BPF_ALU64 | BPF_MOV | BPF_K: 1516 case BPF_ALU | BPF_MOV | BPF_K: 1517 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64, 1518 dst_reg, imm32); 1519 break; 1520 1521 case BPF_LD | BPF_IMM | BPF_DW: 1522 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm); 1523 insn++; 1524 i++; 1525 break; 1526 1527 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */ 1528 case BPF_ALU | BPF_MOD | BPF_X: 1529 case BPF_ALU | BPF_DIV | BPF_X: 1530 case BPF_ALU | BPF_MOD | BPF_K: 1531 case BPF_ALU | BPF_DIV | BPF_K: 1532 case BPF_ALU64 | BPF_MOD | BPF_X: 1533 case BPF_ALU64 | BPF_DIV | BPF_X: 1534 case BPF_ALU64 | BPF_MOD | BPF_K: 1535 case BPF_ALU64 | BPF_DIV | BPF_K: { 1536 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64; 1537 1538 if (dst_reg != BPF_REG_0) 1539 EMIT1(0x50); /* push rax */ 1540 if (dst_reg != BPF_REG_3) 1541 EMIT1(0x52); /* push rdx */ 1542 1543 if (BPF_SRC(insn->code) == BPF_X) { 1544 if (src_reg == BPF_REG_0 || 1545 src_reg == BPF_REG_3) { 1546 /* mov r11, src_reg */ 1547 EMIT_mov(AUX_REG, src_reg); 1548 src_reg = AUX_REG; 1549 } 1550 } else { 1551 /* mov r11, imm32 */ 1552 EMIT3_off32(0x49, 0xC7, 0xC3, imm32); 1553 src_reg = AUX_REG; 1554 } 1555 1556 if (dst_reg != BPF_REG_0) 1557 /* mov rax, dst_reg */ 1558 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg); 1559 1560 if (insn->off == 0) { 1561 /* 1562 * xor edx, edx 1563 * equivalent to 'xor rdx, rdx', but one byte less 1564 */ 1565 EMIT2(0x31, 0xd2); 1566 1567 /* div src_reg */ 1568 maybe_emit_1mod(&prog, src_reg, is64); 1569 EMIT2(0xF7, add_1reg(0xF0, src_reg)); 1570 } else { 1571 if (BPF_CLASS(insn->code) == BPF_ALU) 1572 EMIT1(0x99); /* cdq */ 1573 else 1574 EMIT2(0x48, 0x99); /* cqo */ 1575 1576 /* idiv src_reg */ 1577 maybe_emit_1mod(&prog, src_reg, is64); 1578 EMIT2(0xF7, add_1reg(0xF8, src_reg)); 1579 } 1580 1581 if (BPF_OP(insn->code) == BPF_MOD && 1582 dst_reg != BPF_REG_3) 1583 /* mov dst_reg, rdx */ 1584 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3); 1585 else if (BPF_OP(insn->code) == BPF_DIV && 1586 dst_reg != BPF_REG_0) 1587 /* mov dst_reg, rax */ 1588 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0); 1589 1590 if (dst_reg != BPF_REG_3) 1591 EMIT1(0x5A); /* pop rdx */ 1592 if (dst_reg != BPF_REG_0) 1593 EMIT1(0x58); /* pop rax */ 1594 break; 1595 } 1596 1597 case BPF_ALU | BPF_MUL | BPF_K: 1598 case BPF_ALU64 | BPF_MUL | BPF_K: 1599 maybe_emit_mod(&prog, dst_reg, dst_reg, 1600 BPF_CLASS(insn->code) == BPF_ALU64); 1601 1602 if (is_imm8(imm32)) 1603 /* imul dst_reg, dst_reg, imm8 */ 1604 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg), 1605 imm32); 1606 else 1607 /* imul dst_reg, dst_reg, imm32 */ 1608 EMIT2_off32(0x69, 1609 add_2reg(0xC0, dst_reg, dst_reg), 1610 imm32); 1611 break; 1612 1613 case BPF_ALU | BPF_MUL | BPF_X: 1614 case BPF_ALU64 | BPF_MUL | BPF_X: 1615 maybe_emit_mod(&prog, src_reg, dst_reg, 1616 BPF_CLASS(insn->code) == BPF_ALU64); 1617 1618 /* imul dst_reg, src_reg */ 1619 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg)); 1620 break; 1621 1622 /* Shifts */ 1623 case BPF_ALU | BPF_LSH | BPF_K: 1624 case BPF_ALU | BPF_RSH | BPF_K: 1625 case BPF_ALU | BPF_ARSH | BPF_K: 1626 case BPF_ALU64 | BPF_LSH | BPF_K: 1627 case BPF_ALU64 | BPF_RSH | BPF_K: 1628 case BPF_ALU64 | BPF_ARSH | BPF_K: 1629 maybe_emit_1mod(&prog, dst_reg, 1630 BPF_CLASS(insn->code) == BPF_ALU64); 1631 1632 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1633 if (imm32 == 1) 1634 EMIT2(0xD1, add_1reg(b3, dst_reg)); 1635 else 1636 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32); 1637 break; 1638 1639 case BPF_ALU | BPF_LSH | BPF_X: 1640 case BPF_ALU | BPF_RSH | BPF_X: 1641 case BPF_ALU | BPF_ARSH | BPF_X: 1642 case BPF_ALU64 | BPF_LSH | BPF_X: 1643 case BPF_ALU64 | BPF_RSH | BPF_X: 1644 case BPF_ALU64 | BPF_ARSH | BPF_X: 1645 /* BMI2 shifts aren't better when shift count is already in rcx */ 1646 if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) { 1647 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */ 1648 bool w = (BPF_CLASS(insn->code) == BPF_ALU64); 1649 u8 op; 1650 1651 switch (BPF_OP(insn->code)) { 1652 case BPF_LSH: 1653 op = 1; /* prefix 0x66 */ 1654 break; 1655 case BPF_RSH: 1656 op = 3; /* prefix 0xf2 */ 1657 break; 1658 case BPF_ARSH: 1659 op = 2; /* prefix 0xf3 */ 1660 break; 1661 } 1662 1663 emit_shiftx(&prog, dst_reg, src_reg, w, op); 1664 1665 break; 1666 } 1667 1668 if (src_reg != BPF_REG_4) { /* common case */ 1669 /* Check for bad case when dst_reg == rcx */ 1670 if (dst_reg == BPF_REG_4) { 1671 /* mov r11, dst_reg */ 1672 EMIT_mov(AUX_REG, dst_reg); 1673 dst_reg = AUX_REG; 1674 } else { 1675 EMIT1(0x51); /* push rcx */ 1676 } 1677 /* mov rcx, src_reg */ 1678 EMIT_mov(BPF_REG_4, src_reg); 1679 } 1680 1681 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */ 1682 maybe_emit_1mod(&prog, dst_reg, 1683 BPF_CLASS(insn->code) == BPF_ALU64); 1684 1685 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1686 EMIT2(0xD3, add_1reg(b3, dst_reg)); 1687 1688 if (src_reg != BPF_REG_4) { 1689 if (insn->dst_reg == BPF_REG_4) 1690 /* mov dst_reg, r11 */ 1691 EMIT_mov(insn->dst_reg, AUX_REG); 1692 else 1693 EMIT1(0x59); /* pop rcx */ 1694 } 1695 1696 break; 1697 1698 case BPF_ALU | BPF_END | BPF_FROM_BE: 1699 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 1700 switch (imm32) { 1701 case 16: 1702 /* Emit 'ror %ax, 8' to swap lower 2 bytes */ 1703 EMIT1(0x66); 1704 if (is_ereg(dst_reg)) 1705 EMIT1(0x41); 1706 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8); 1707 1708 /* Emit 'movzwl eax, ax' */ 1709 if (is_ereg(dst_reg)) 1710 EMIT3(0x45, 0x0F, 0xB7); 1711 else 1712 EMIT2(0x0F, 0xB7); 1713 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 1714 break; 1715 case 32: 1716 /* Emit 'bswap eax' to swap lower 4 bytes */ 1717 if (is_ereg(dst_reg)) 1718 EMIT2(0x41, 0x0F); 1719 else 1720 EMIT1(0x0F); 1721 EMIT1(add_1reg(0xC8, dst_reg)); 1722 break; 1723 case 64: 1724 /* Emit 'bswap rax' to swap 8 bytes */ 1725 EMIT3(add_1mod(0x48, dst_reg), 0x0F, 1726 add_1reg(0xC8, dst_reg)); 1727 break; 1728 } 1729 break; 1730 1731 case BPF_ALU | BPF_END | BPF_FROM_LE: 1732 switch (imm32) { 1733 case 16: 1734 /* 1735 * Emit 'movzwl eax, ax' to zero extend 16-bit 1736 * into 64 bit 1737 */ 1738 if (is_ereg(dst_reg)) 1739 EMIT3(0x45, 0x0F, 0xB7); 1740 else 1741 EMIT2(0x0F, 0xB7); 1742 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 1743 break; 1744 case 32: 1745 /* Emit 'mov eax, eax' to clear upper 32-bits */ 1746 if (is_ereg(dst_reg)) 1747 EMIT1(0x45); 1748 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg)); 1749 break; 1750 case 64: 1751 /* nop */ 1752 break; 1753 } 1754 break; 1755 1756 /* speculation barrier */ 1757 case BPF_ST | BPF_NOSPEC: 1758 EMIT_LFENCE(); 1759 break; 1760 1761 /* ST: *(u8*)(dst_reg + off) = imm */ 1762 case BPF_ST | BPF_MEM | BPF_B: 1763 if (is_ereg(dst_reg)) 1764 EMIT2(0x41, 0xC6); 1765 else 1766 EMIT1(0xC6); 1767 goto st; 1768 case BPF_ST | BPF_MEM | BPF_H: 1769 if (is_ereg(dst_reg)) 1770 EMIT3(0x66, 0x41, 0xC7); 1771 else 1772 EMIT2(0x66, 0xC7); 1773 goto st; 1774 case BPF_ST | BPF_MEM | BPF_W: 1775 if (is_ereg(dst_reg)) 1776 EMIT2(0x41, 0xC7); 1777 else 1778 EMIT1(0xC7); 1779 goto st; 1780 case BPF_ST | BPF_MEM | BPF_DW: 1781 EMIT2(add_1mod(0x48, dst_reg), 0xC7); 1782 1783 st: if (is_imm8(insn->off)) 1784 EMIT2(add_1reg(0x40, dst_reg), insn->off); 1785 else 1786 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off); 1787 1788 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code))); 1789 break; 1790 1791 /* STX: *(u8*)(dst_reg + off) = src_reg */ 1792 case BPF_STX | BPF_MEM | BPF_B: 1793 case BPF_STX | BPF_MEM | BPF_H: 1794 case BPF_STX | BPF_MEM | BPF_W: 1795 case BPF_STX | BPF_MEM | BPF_DW: 1796 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 1797 break; 1798 1799 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 1800 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 1801 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 1802 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 1803 start_of_ldx = prog; 1804 emit_st_r12(&prog, BPF_SIZE(insn->code), dst_reg, insn->off, insn->imm); 1805 goto populate_extable; 1806 1807 /* LDX: dst_reg = *(u8*)(src_reg + r12 + off) */ 1808 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 1809 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 1810 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 1811 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 1812 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 1813 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 1814 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 1815 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 1816 start_of_ldx = prog; 1817 if (BPF_CLASS(insn->code) == BPF_LDX) 1818 emit_ldx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 1819 else 1820 emit_stx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 1821 populate_extable: 1822 { 1823 struct exception_table_entry *ex; 1824 u8 *_insn = image + proglen + (start_of_ldx - temp); 1825 s64 delta; 1826 1827 if (!bpf_prog->aux->extable) 1828 break; 1829 1830 if (excnt >= bpf_prog->aux->num_exentries) { 1831 pr_err("mem32 extable bug\n"); 1832 return -EFAULT; 1833 } 1834 ex = &bpf_prog->aux->extable[excnt++]; 1835 1836 delta = _insn - (u8 *)&ex->insn; 1837 /* switch ex to rw buffer for writes */ 1838 ex = (void *)rw_image + ((void *)ex - (void *)image); 1839 1840 ex->insn = delta; 1841 1842 ex->data = EX_TYPE_BPF; 1843 1844 ex->fixup = (prog - start_of_ldx) | 1845 ((BPF_CLASS(insn->code) == BPF_LDX ? reg2pt_regs[dst_reg] : DONT_CLEAR) << 8); 1846 } 1847 break; 1848 1849 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 1850 case BPF_LDX | BPF_MEM | BPF_B: 1851 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 1852 case BPF_LDX | BPF_MEM | BPF_H: 1853 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 1854 case BPF_LDX | BPF_MEM | BPF_W: 1855 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 1856 case BPF_LDX | BPF_MEM | BPF_DW: 1857 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 1858 /* LDXS: dst_reg = *(s8*)(src_reg + off) */ 1859 case BPF_LDX | BPF_MEMSX | BPF_B: 1860 case BPF_LDX | BPF_MEMSX | BPF_H: 1861 case BPF_LDX | BPF_MEMSX | BPF_W: 1862 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 1863 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 1864 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 1865 insn_off = insn->off; 1866 1867 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 1868 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 1869 /* Conservatively check that src_reg + insn->off is a kernel address: 1870 * src_reg + insn->off >= TASK_SIZE_MAX + PAGE_SIZE 1871 * src_reg is used as scratch for src_reg += insn->off and restored 1872 * after emit_ldx if necessary 1873 */ 1874 1875 u64 limit = TASK_SIZE_MAX + PAGE_SIZE; 1876 u8 *end_of_jmp; 1877 1878 /* At end of these emitted checks, insn->off will have been added 1879 * to src_reg, so no need to do relative load with insn->off offset 1880 */ 1881 insn_off = 0; 1882 1883 /* movabsq r11, limit */ 1884 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG)); 1885 EMIT((u32)limit, 4); 1886 EMIT(limit >> 32, 4); 1887 1888 if (insn->off) { 1889 /* add src_reg, insn->off */ 1890 maybe_emit_1mod(&prog, src_reg, true); 1891 EMIT2_off32(0x81, add_1reg(0xC0, src_reg), insn->off); 1892 } 1893 1894 /* cmp src_reg, r11 */ 1895 maybe_emit_mod(&prog, src_reg, AUX_REG, true); 1896 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG)); 1897 1898 /* if unsigned '>=', goto load */ 1899 EMIT2(X86_JAE, 0); 1900 end_of_jmp = prog; 1901 1902 /* xor dst_reg, dst_reg */ 1903 emit_mov_imm32(&prog, false, dst_reg, 0); 1904 /* jmp byte_after_ldx */ 1905 EMIT2(0xEB, 0); 1906 1907 /* populate jmp_offset for JAE above to jump to start_of_ldx */ 1908 start_of_ldx = prog; 1909 end_of_jmp[-1] = start_of_ldx - end_of_jmp; 1910 } 1911 if (BPF_MODE(insn->code) == BPF_PROBE_MEMSX || 1912 BPF_MODE(insn->code) == BPF_MEMSX) 1913 emit_ldsx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 1914 else 1915 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 1916 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 1917 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 1918 struct exception_table_entry *ex; 1919 u8 *_insn = image + proglen + (start_of_ldx - temp); 1920 s64 delta; 1921 1922 /* populate jmp_offset for JMP above */ 1923 start_of_ldx[-1] = prog - start_of_ldx; 1924 1925 if (insn->off && src_reg != dst_reg) { 1926 /* sub src_reg, insn->off 1927 * Restore src_reg after "add src_reg, insn->off" in prev 1928 * if statement. But if src_reg == dst_reg, emit_ldx 1929 * above already clobbered src_reg, so no need to restore. 1930 * If add src_reg, insn->off was unnecessary, no need to 1931 * restore either. 1932 */ 1933 maybe_emit_1mod(&prog, src_reg, true); 1934 EMIT2_off32(0x81, add_1reg(0xE8, src_reg), insn->off); 1935 } 1936 1937 if (!bpf_prog->aux->extable) 1938 break; 1939 1940 if (excnt >= bpf_prog->aux->num_exentries) { 1941 pr_err("ex gen bug\n"); 1942 return -EFAULT; 1943 } 1944 ex = &bpf_prog->aux->extable[excnt++]; 1945 1946 delta = _insn - (u8 *)&ex->insn; 1947 if (!is_simm32(delta)) { 1948 pr_err("extable->insn doesn't fit into 32-bit\n"); 1949 return -EFAULT; 1950 } 1951 /* switch ex to rw buffer for writes */ 1952 ex = (void *)rw_image + ((void *)ex - (void *)image); 1953 1954 ex->insn = delta; 1955 1956 ex->data = EX_TYPE_BPF; 1957 1958 if (dst_reg > BPF_REG_9) { 1959 pr_err("verifier error\n"); 1960 return -EFAULT; 1961 } 1962 /* 1963 * Compute size of x86 insn and its target dest x86 register. 1964 * ex_handler_bpf() will use lower 8 bits to adjust 1965 * pt_regs->ip to jump over this x86 instruction 1966 * and upper bits to figure out which pt_regs to zero out. 1967 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]" 1968 * of 4 bytes will be ignored and rbx will be zero inited. 1969 */ 1970 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8); 1971 } 1972 break; 1973 1974 case BPF_STX | BPF_ATOMIC | BPF_W: 1975 case BPF_STX | BPF_ATOMIC | BPF_DW: 1976 if (insn->imm == (BPF_AND | BPF_FETCH) || 1977 insn->imm == (BPF_OR | BPF_FETCH) || 1978 insn->imm == (BPF_XOR | BPF_FETCH)) { 1979 bool is64 = BPF_SIZE(insn->code) == BPF_DW; 1980 u32 real_src_reg = src_reg; 1981 u32 real_dst_reg = dst_reg; 1982 u8 *branch_target; 1983 1984 /* 1985 * Can't be implemented with a single x86 insn. 1986 * Need to do a CMPXCHG loop. 1987 */ 1988 1989 /* Will need RAX as a CMPXCHG operand so save R0 */ 1990 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0); 1991 if (src_reg == BPF_REG_0) 1992 real_src_reg = BPF_REG_AX; 1993 if (dst_reg == BPF_REG_0) 1994 real_dst_reg = BPF_REG_AX; 1995 1996 branch_target = prog; 1997 /* Load old value */ 1998 emit_ldx(&prog, BPF_SIZE(insn->code), 1999 BPF_REG_0, real_dst_reg, insn->off); 2000 /* 2001 * Perform the (commutative) operation locally, 2002 * put the result in the AUX_REG. 2003 */ 2004 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0); 2005 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64); 2006 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)], 2007 add_2reg(0xC0, AUX_REG, real_src_reg)); 2008 /* Attempt to swap in new value */ 2009 err = emit_atomic(&prog, BPF_CMPXCHG, 2010 real_dst_reg, AUX_REG, 2011 insn->off, 2012 BPF_SIZE(insn->code)); 2013 if (WARN_ON(err)) 2014 return err; 2015 /* 2016 * ZF tells us whether we won the race. If it's 2017 * cleared we need to try again. 2018 */ 2019 EMIT2(X86_JNE, -(prog - branch_target) - 2); 2020 /* Return the pre-modification value */ 2021 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0); 2022 /* Restore R0 after clobbering RAX */ 2023 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX); 2024 break; 2025 } 2026 2027 err = emit_atomic(&prog, insn->imm, dst_reg, src_reg, 2028 insn->off, BPF_SIZE(insn->code)); 2029 if (err) 2030 return err; 2031 break; 2032 2033 case BPF_STX | BPF_PROBE_ATOMIC | BPF_W: 2034 case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW: 2035 start_of_ldx = prog; 2036 err = emit_atomic_index(&prog, insn->imm, BPF_SIZE(insn->code), 2037 dst_reg, src_reg, X86_REG_R12, insn->off); 2038 if (err) 2039 return err; 2040 goto populate_extable; 2041 2042 /* call */ 2043 case BPF_JMP | BPF_CALL: { 2044 int offs; 2045 2046 func = (u8 *) __bpf_call_base + imm32; 2047 if (tail_call_reachable) { 2048 RESTORE_TAIL_CALL_CNT(bpf_prog->aux->stack_depth); 2049 if (!imm32) 2050 return -EINVAL; 2051 offs = 7 + x86_call_depth_emit_accounting(&prog, func); 2052 } else { 2053 if (!imm32) 2054 return -EINVAL; 2055 offs = x86_call_depth_emit_accounting(&prog, func); 2056 } 2057 if (emit_call(&prog, func, image + addrs[i - 1] + offs)) 2058 return -EINVAL; 2059 break; 2060 } 2061 2062 case BPF_JMP | BPF_TAIL_CALL: 2063 if (imm32) 2064 emit_bpf_tail_call_direct(bpf_prog, 2065 &bpf_prog->aux->poke_tab[imm32 - 1], 2066 &prog, image + addrs[i - 1], 2067 callee_regs_used, 2068 bpf_prog->aux->stack_depth, 2069 ctx); 2070 else 2071 emit_bpf_tail_call_indirect(bpf_prog, 2072 &prog, 2073 callee_regs_used, 2074 bpf_prog->aux->stack_depth, 2075 image + addrs[i - 1], 2076 ctx); 2077 break; 2078 2079 /* cond jump */ 2080 case BPF_JMP | BPF_JEQ | BPF_X: 2081 case BPF_JMP | BPF_JNE | BPF_X: 2082 case BPF_JMP | BPF_JGT | BPF_X: 2083 case BPF_JMP | BPF_JLT | BPF_X: 2084 case BPF_JMP | BPF_JGE | BPF_X: 2085 case BPF_JMP | BPF_JLE | BPF_X: 2086 case BPF_JMP | BPF_JSGT | BPF_X: 2087 case BPF_JMP | BPF_JSLT | BPF_X: 2088 case BPF_JMP | BPF_JSGE | BPF_X: 2089 case BPF_JMP | BPF_JSLE | BPF_X: 2090 case BPF_JMP32 | BPF_JEQ | BPF_X: 2091 case BPF_JMP32 | BPF_JNE | BPF_X: 2092 case BPF_JMP32 | BPF_JGT | BPF_X: 2093 case BPF_JMP32 | BPF_JLT | BPF_X: 2094 case BPF_JMP32 | BPF_JGE | BPF_X: 2095 case BPF_JMP32 | BPF_JLE | BPF_X: 2096 case BPF_JMP32 | BPF_JSGT | BPF_X: 2097 case BPF_JMP32 | BPF_JSLT | BPF_X: 2098 case BPF_JMP32 | BPF_JSGE | BPF_X: 2099 case BPF_JMP32 | BPF_JSLE | BPF_X: 2100 /* cmp dst_reg, src_reg */ 2101 maybe_emit_mod(&prog, dst_reg, src_reg, 2102 BPF_CLASS(insn->code) == BPF_JMP); 2103 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg)); 2104 goto emit_cond_jmp; 2105 2106 case BPF_JMP | BPF_JSET | BPF_X: 2107 case BPF_JMP32 | BPF_JSET | BPF_X: 2108 /* test dst_reg, src_reg */ 2109 maybe_emit_mod(&prog, dst_reg, src_reg, 2110 BPF_CLASS(insn->code) == BPF_JMP); 2111 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg)); 2112 goto emit_cond_jmp; 2113 2114 case BPF_JMP | BPF_JSET | BPF_K: 2115 case BPF_JMP32 | BPF_JSET | BPF_K: 2116 /* test dst_reg, imm32 */ 2117 maybe_emit_1mod(&prog, dst_reg, 2118 BPF_CLASS(insn->code) == BPF_JMP); 2119 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32); 2120 goto emit_cond_jmp; 2121 2122 case BPF_JMP | BPF_JEQ | BPF_K: 2123 case BPF_JMP | BPF_JNE | BPF_K: 2124 case BPF_JMP | BPF_JGT | BPF_K: 2125 case BPF_JMP | BPF_JLT | BPF_K: 2126 case BPF_JMP | BPF_JGE | BPF_K: 2127 case BPF_JMP | BPF_JLE | BPF_K: 2128 case BPF_JMP | BPF_JSGT | BPF_K: 2129 case BPF_JMP | BPF_JSLT | BPF_K: 2130 case BPF_JMP | BPF_JSGE | BPF_K: 2131 case BPF_JMP | BPF_JSLE | BPF_K: 2132 case BPF_JMP32 | BPF_JEQ | BPF_K: 2133 case BPF_JMP32 | BPF_JNE | BPF_K: 2134 case BPF_JMP32 | BPF_JGT | BPF_K: 2135 case BPF_JMP32 | BPF_JLT | BPF_K: 2136 case BPF_JMP32 | BPF_JGE | BPF_K: 2137 case BPF_JMP32 | BPF_JLE | BPF_K: 2138 case BPF_JMP32 | BPF_JSGT | BPF_K: 2139 case BPF_JMP32 | BPF_JSLT | BPF_K: 2140 case BPF_JMP32 | BPF_JSGE | BPF_K: 2141 case BPF_JMP32 | BPF_JSLE | BPF_K: 2142 /* test dst_reg, dst_reg to save one extra byte */ 2143 if (imm32 == 0) { 2144 maybe_emit_mod(&prog, dst_reg, dst_reg, 2145 BPF_CLASS(insn->code) == BPF_JMP); 2146 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 2147 goto emit_cond_jmp; 2148 } 2149 2150 /* cmp dst_reg, imm8/32 */ 2151 maybe_emit_1mod(&prog, dst_reg, 2152 BPF_CLASS(insn->code) == BPF_JMP); 2153 2154 if (is_imm8(imm32)) 2155 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32); 2156 else 2157 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32); 2158 2159 emit_cond_jmp: /* Convert BPF opcode to x86 */ 2160 switch (BPF_OP(insn->code)) { 2161 case BPF_JEQ: 2162 jmp_cond = X86_JE; 2163 break; 2164 case BPF_JSET: 2165 case BPF_JNE: 2166 jmp_cond = X86_JNE; 2167 break; 2168 case BPF_JGT: 2169 /* GT is unsigned '>', JA in x86 */ 2170 jmp_cond = X86_JA; 2171 break; 2172 case BPF_JLT: 2173 /* LT is unsigned '<', JB in x86 */ 2174 jmp_cond = X86_JB; 2175 break; 2176 case BPF_JGE: 2177 /* GE is unsigned '>=', JAE in x86 */ 2178 jmp_cond = X86_JAE; 2179 break; 2180 case BPF_JLE: 2181 /* LE is unsigned '<=', JBE in x86 */ 2182 jmp_cond = X86_JBE; 2183 break; 2184 case BPF_JSGT: 2185 /* Signed '>', GT in x86 */ 2186 jmp_cond = X86_JG; 2187 break; 2188 case BPF_JSLT: 2189 /* Signed '<', LT in x86 */ 2190 jmp_cond = X86_JL; 2191 break; 2192 case BPF_JSGE: 2193 /* Signed '>=', GE in x86 */ 2194 jmp_cond = X86_JGE; 2195 break; 2196 case BPF_JSLE: 2197 /* Signed '<=', LE in x86 */ 2198 jmp_cond = X86_JLE; 2199 break; 2200 default: /* to silence GCC warning */ 2201 return -EFAULT; 2202 } 2203 jmp_offset = addrs[i + insn->off] - addrs[i]; 2204 if (is_imm8(jmp_offset)) { 2205 if (jmp_padding) { 2206 /* To keep the jmp_offset valid, the extra bytes are 2207 * padded before the jump insn, so we subtract the 2208 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF. 2209 * 2210 * If the previous pass already emits an imm8 2211 * jmp_cond, then this BPF insn won't shrink, so 2212 * "nops" is 0. 2213 * 2214 * On the other hand, if the previous pass emits an 2215 * imm32 jmp_cond, the extra 4 bytes(*) is padded to 2216 * keep the image from shrinking further. 2217 * 2218 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond 2219 * is 2 bytes, so the size difference is 4 bytes. 2220 */ 2221 nops = INSN_SZ_DIFF - 2; 2222 if (nops != 0 && nops != 4) { 2223 pr_err("unexpected jmp_cond padding: %d bytes\n", 2224 nops); 2225 return -EFAULT; 2226 } 2227 emit_nops(&prog, nops); 2228 } 2229 EMIT2(jmp_cond, jmp_offset); 2230 } else if (is_simm32(jmp_offset)) { 2231 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset); 2232 } else { 2233 pr_err("cond_jmp gen bug %llx\n", jmp_offset); 2234 return -EFAULT; 2235 } 2236 2237 break; 2238 2239 case BPF_JMP | BPF_JA: 2240 case BPF_JMP32 | BPF_JA: 2241 if (BPF_CLASS(insn->code) == BPF_JMP) { 2242 if (insn->off == -1) 2243 /* -1 jmp instructions will always jump 2244 * backwards two bytes. Explicitly handling 2245 * this case avoids wasting too many passes 2246 * when there are long sequences of replaced 2247 * dead code. 2248 */ 2249 jmp_offset = -2; 2250 else 2251 jmp_offset = addrs[i + insn->off] - addrs[i]; 2252 } else { 2253 if (insn->imm == -1) 2254 jmp_offset = -2; 2255 else 2256 jmp_offset = addrs[i + insn->imm] - addrs[i]; 2257 } 2258 2259 if (!jmp_offset) { 2260 /* 2261 * If jmp_padding is enabled, the extra nops will 2262 * be inserted. Otherwise, optimize out nop jumps. 2263 */ 2264 if (jmp_padding) { 2265 /* There are 3 possible conditions. 2266 * (1) This BPF_JA is already optimized out in 2267 * the previous run, so there is no need 2268 * to pad any extra byte (0 byte). 2269 * (2) The previous pass emits an imm8 jmp, 2270 * so we pad 2 bytes to match the previous 2271 * insn size. 2272 * (3) Similarly, the previous pass emits an 2273 * imm32 jmp, and 5 bytes is padded. 2274 */ 2275 nops = INSN_SZ_DIFF; 2276 if (nops != 0 && nops != 2 && nops != 5) { 2277 pr_err("unexpected nop jump padding: %d bytes\n", 2278 nops); 2279 return -EFAULT; 2280 } 2281 emit_nops(&prog, nops); 2282 } 2283 break; 2284 } 2285 emit_jmp: 2286 if (is_imm8(jmp_offset)) { 2287 if (jmp_padding) { 2288 /* To avoid breaking jmp_offset, the extra bytes 2289 * are padded before the actual jmp insn, so 2290 * 2 bytes is subtracted from INSN_SZ_DIFF. 2291 * 2292 * If the previous pass already emits an imm8 2293 * jmp, there is nothing to pad (0 byte). 2294 * 2295 * If it emits an imm32 jmp (5 bytes) previously 2296 * and now an imm8 jmp (2 bytes), then we pad 2297 * (5 - 2 = 3) bytes to stop the image from 2298 * shrinking further. 2299 */ 2300 nops = INSN_SZ_DIFF - 2; 2301 if (nops != 0 && nops != 3) { 2302 pr_err("unexpected jump padding: %d bytes\n", 2303 nops); 2304 return -EFAULT; 2305 } 2306 emit_nops(&prog, INSN_SZ_DIFF - 2); 2307 } 2308 EMIT2(0xEB, jmp_offset); 2309 } else if (is_simm32(jmp_offset)) { 2310 EMIT1_off32(0xE9, jmp_offset); 2311 } else { 2312 pr_err("jmp gen bug %llx\n", jmp_offset); 2313 return -EFAULT; 2314 } 2315 break; 2316 2317 case BPF_JMP | BPF_EXIT: 2318 if (seen_exit) { 2319 jmp_offset = ctx->cleanup_addr - addrs[i]; 2320 goto emit_jmp; 2321 } 2322 seen_exit = true; 2323 /* Update cleanup_addr */ 2324 ctx->cleanup_addr = proglen; 2325 if (bpf_prog->aux->exception_boundary) { 2326 pop_callee_regs(&prog, all_callee_regs_used); 2327 pop_r12(&prog); 2328 } else { 2329 pop_callee_regs(&prog, callee_regs_used); 2330 if (arena_vm_start) 2331 pop_r12(&prog); 2332 } 2333 EMIT1(0xC9); /* leave */ 2334 emit_return(&prog, image + addrs[i - 1] + (prog - temp)); 2335 break; 2336 2337 default: 2338 /* 2339 * By design x86-64 JIT should support all BPF instructions. 2340 * This error will be seen if new instruction was added 2341 * to the interpreter, but not to the JIT, or if there is 2342 * junk in bpf_prog. 2343 */ 2344 pr_err("bpf_jit: unknown opcode %02x\n", insn->code); 2345 return -EINVAL; 2346 } 2347 2348 ilen = prog - temp; 2349 if (ilen > BPF_MAX_INSN_SIZE) { 2350 pr_err("bpf_jit: fatal insn size error\n"); 2351 return -EFAULT; 2352 } 2353 2354 if (image) { 2355 /* 2356 * When populating the image, assert that: 2357 * 2358 * i) We do not write beyond the allocated space, and 2359 * ii) addrs[i] did not change from the prior run, in order 2360 * to validate assumptions made for computing branch 2361 * displacements. 2362 */ 2363 if (unlikely(proglen + ilen > oldproglen || 2364 proglen + ilen != addrs[i])) { 2365 pr_err("bpf_jit: fatal error\n"); 2366 return -EFAULT; 2367 } 2368 memcpy(rw_image + proglen, temp, ilen); 2369 } 2370 proglen += ilen; 2371 addrs[i] = proglen; 2372 prog = temp; 2373 } 2374 2375 if (image && excnt != bpf_prog->aux->num_exentries) { 2376 pr_err("extable is not populated\n"); 2377 return -EFAULT; 2378 } 2379 return proglen; 2380 } 2381 2382 static void clean_stack_garbage(const struct btf_func_model *m, 2383 u8 **pprog, int nr_stack_slots, 2384 int stack_size) 2385 { 2386 int arg_size, off; 2387 u8 *prog; 2388 2389 /* Generally speaking, the compiler will pass the arguments 2390 * on-stack with "push" instruction, which will take 8-byte 2391 * on the stack. In this case, there won't be garbage values 2392 * while we copy the arguments from origin stack frame to current 2393 * in BPF_DW. 2394 * 2395 * However, sometimes the compiler will only allocate 4-byte on 2396 * the stack for the arguments. For now, this case will only 2397 * happen if there is only one argument on-stack and its size 2398 * not more than 4 byte. In this case, there will be garbage 2399 * values on the upper 4-byte where we store the argument on 2400 * current stack frame. 2401 * 2402 * arguments on origin stack: 2403 * 2404 * stack_arg_1(4-byte) xxx(4-byte) 2405 * 2406 * what we copy: 2407 * 2408 * stack_arg_1(8-byte): stack_arg_1(origin) xxx 2409 * 2410 * and the xxx is the garbage values which we should clean here. 2411 */ 2412 if (nr_stack_slots != 1) 2413 return; 2414 2415 /* the size of the last argument */ 2416 arg_size = m->arg_size[m->nr_args - 1]; 2417 if (arg_size <= 4) { 2418 off = -(stack_size - 4); 2419 prog = *pprog; 2420 /* mov DWORD PTR [rbp + off], 0 */ 2421 if (!is_imm8(off)) 2422 EMIT2_off32(0xC7, 0x85, off); 2423 else 2424 EMIT3(0xC7, 0x45, off); 2425 EMIT(0, 4); 2426 *pprog = prog; 2427 } 2428 } 2429 2430 /* get the count of the regs that are used to pass arguments */ 2431 static int get_nr_used_regs(const struct btf_func_model *m) 2432 { 2433 int i, arg_regs, nr_used_regs = 0; 2434 2435 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2436 arg_regs = (m->arg_size[i] + 7) / 8; 2437 if (nr_used_regs + arg_regs <= 6) 2438 nr_used_regs += arg_regs; 2439 2440 if (nr_used_regs >= 6) 2441 break; 2442 } 2443 2444 return nr_used_regs; 2445 } 2446 2447 static void save_args(const struct btf_func_model *m, u8 **prog, 2448 int stack_size, bool for_call_origin) 2449 { 2450 int arg_regs, first_off = 0, nr_regs = 0, nr_stack_slots = 0; 2451 int i, j; 2452 2453 /* Store function arguments to stack. 2454 * For a function that accepts two pointers the sequence will be: 2455 * mov QWORD PTR [rbp-0x10],rdi 2456 * mov QWORD PTR [rbp-0x8],rsi 2457 */ 2458 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2459 arg_regs = (m->arg_size[i] + 7) / 8; 2460 2461 /* According to the research of Yonghong, struct members 2462 * should be all in register or all on the stack. 2463 * Meanwhile, the compiler will pass the argument on regs 2464 * if the remaining regs can hold the argument. 2465 * 2466 * Disorder of the args can happen. For example: 2467 * 2468 * struct foo_struct { 2469 * long a; 2470 * int b; 2471 * }; 2472 * int foo(char, char, char, char, char, struct foo_struct, 2473 * char); 2474 * 2475 * the arg1-5,arg7 will be passed by regs, and arg6 will 2476 * by stack. 2477 */ 2478 if (nr_regs + arg_regs > 6) { 2479 /* copy function arguments from origin stack frame 2480 * into current stack frame. 2481 * 2482 * The starting address of the arguments on-stack 2483 * is: 2484 * rbp + 8(push rbp) + 2485 * 8(return addr of origin call) + 2486 * 8(return addr of the caller) 2487 * which means: rbp + 24 2488 */ 2489 for (j = 0; j < arg_regs; j++) { 2490 emit_ldx(prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 2491 nr_stack_slots * 8 + 0x18); 2492 emit_stx(prog, BPF_DW, BPF_REG_FP, BPF_REG_0, 2493 -stack_size); 2494 2495 if (!nr_stack_slots) 2496 first_off = stack_size; 2497 stack_size -= 8; 2498 nr_stack_slots++; 2499 } 2500 } else { 2501 /* Only copy the arguments on-stack to current 2502 * 'stack_size' and ignore the regs, used to 2503 * prepare the arguments on-stack for origin call. 2504 */ 2505 if (for_call_origin) { 2506 nr_regs += arg_regs; 2507 continue; 2508 } 2509 2510 /* copy the arguments from regs into stack */ 2511 for (j = 0; j < arg_regs; j++) { 2512 emit_stx(prog, BPF_DW, BPF_REG_FP, 2513 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2514 -stack_size); 2515 stack_size -= 8; 2516 nr_regs++; 2517 } 2518 } 2519 } 2520 2521 clean_stack_garbage(m, prog, nr_stack_slots, first_off); 2522 } 2523 2524 static void restore_regs(const struct btf_func_model *m, u8 **prog, 2525 int stack_size) 2526 { 2527 int i, j, arg_regs, nr_regs = 0; 2528 2529 /* Restore function arguments from stack. 2530 * For a function that accepts two pointers the sequence will be: 2531 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10] 2532 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8] 2533 * 2534 * The logic here is similar to what we do in save_args() 2535 */ 2536 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2537 arg_regs = (m->arg_size[i] + 7) / 8; 2538 if (nr_regs + arg_regs <= 6) { 2539 for (j = 0; j < arg_regs; j++) { 2540 emit_ldx(prog, BPF_DW, 2541 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2542 BPF_REG_FP, 2543 -stack_size); 2544 stack_size -= 8; 2545 nr_regs++; 2546 } 2547 } else { 2548 stack_size -= 8 * arg_regs; 2549 } 2550 2551 if (nr_regs >= 6) 2552 break; 2553 } 2554 } 2555 2556 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog, 2557 struct bpf_tramp_link *l, int stack_size, 2558 int run_ctx_off, bool save_ret, 2559 void *image, void *rw_image) 2560 { 2561 u8 *prog = *pprog; 2562 u8 *jmp_insn; 2563 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 2564 struct bpf_prog *p = l->link.prog; 2565 u64 cookie = l->cookie; 2566 2567 /* mov rdi, cookie */ 2568 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie); 2569 2570 /* Prepare struct bpf_tramp_run_ctx. 2571 * 2572 * bpf_tramp_run_ctx is already preserved by 2573 * arch_prepare_bpf_trampoline(). 2574 * 2575 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi 2576 */ 2577 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off); 2578 2579 /* arg1: mov rdi, progs[i] */ 2580 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 2581 /* arg2: lea rsi, [rbp - ctx_cookie_off] */ 2582 if (!is_imm8(-run_ctx_off)) 2583 EMIT3_off32(0x48, 0x8D, 0xB5, -run_ctx_off); 2584 else 2585 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off); 2586 2587 if (emit_rsb_call(&prog, bpf_trampoline_enter(p), image + (prog - (u8 *)rw_image))) 2588 return -EINVAL; 2589 /* remember prog start time returned by __bpf_prog_enter */ 2590 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0); 2591 2592 /* if (__bpf_prog_enter*(prog) == 0) 2593 * goto skip_exec_of_prog; 2594 */ 2595 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */ 2596 /* emit 2 nops that will be replaced with JE insn */ 2597 jmp_insn = prog; 2598 emit_nops(&prog, 2); 2599 2600 /* arg1: lea rdi, [rbp - stack_size] */ 2601 if (!is_imm8(-stack_size)) 2602 EMIT3_off32(0x48, 0x8D, 0xBD, -stack_size); 2603 else 2604 EMIT4(0x48, 0x8D, 0x7D, -stack_size); 2605 /* arg2: progs[i]->insnsi for interpreter */ 2606 if (!p->jited) 2607 emit_mov_imm64(&prog, BPF_REG_2, 2608 (long) p->insnsi >> 32, 2609 (u32) (long) p->insnsi); 2610 /* call JITed bpf program or interpreter */ 2611 if (emit_rsb_call(&prog, p->bpf_func, image + (prog - (u8 *)rw_image))) 2612 return -EINVAL; 2613 2614 /* 2615 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return 2616 * of the previous call which is then passed on the stack to 2617 * the next BPF program. 2618 * 2619 * BPF_TRAMP_FENTRY trampoline may need to return the return 2620 * value of BPF_PROG_TYPE_STRUCT_OPS prog. 2621 */ 2622 if (save_ret) 2623 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2624 2625 /* replace 2 nops with JE insn, since jmp target is known */ 2626 jmp_insn[0] = X86_JE; 2627 jmp_insn[1] = prog - jmp_insn - 2; 2628 2629 /* arg1: mov rdi, progs[i] */ 2630 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 2631 /* arg2: mov rsi, rbx <- start time in nsec */ 2632 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6); 2633 /* arg3: lea rdx, [rbp - run_ctx_off] */ 2634 if (!is_imm8(-run_ctx_off)) 2635 EMIT3_off32(0x48, 0x8D, 0x95, -run_ctx_off); 2636 else 2637 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off); 2638 if (emit_rsb_call(&prog, bpf_trampoline_exit(p), image + (prog - (u8 *)rw_image))) 2639 return -EINVAL; 2640 2641 *pprog = prog; 2642 return 0; 2643 } 2644 2645 static void emit_align(u8 **pprog, u32 align) 2646 { 2647 u8 *target, *prog = *pprog; 2648 2649 target = PTR_ALIGN(prog, align); 2650 if (target != prog) 2651 emit_nops(&prog, target - prog); 2652 2653 *pprog = prog; 2654 } 2655 2656 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond) 2657 { 2658 u8 *prog = *pprog; 2659 s64 offset; 2660 2661 offset = func - (ip + 2 + 4); 2662 if (!is_simm32(offset)) { 2663 pr_err("Target %p is out of range\n", func); 2664 return -EINVAL; 2665 } 2666 EMIT2_off32(0x0F, jmp_cond + 0x10, offset); 2667 *pprog = prog; 2668 return 0; 2669 } 2670 2671 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog, 2672 struct bpf_tramp_links *tl, int stack_size, 2673 int run_ctx_off, bool save_ret, 2674 void *image, void *rw_image) 2675 { 2676 int i; 2677 u8 *prog = *pprog; 2678 2679 for (i = 0; i < tl->nr_links; i++) { 2680 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, 2681 run_ctx_off, save_ret, image, rw_image)) 2682 return -EINVAL; 2683 } 2684 *pprog = prog; 2685 return 0; 2686 } 2687 2688 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog, 2689 struct bpf_tramp_links *tl, int stack_size, 2690 int run_ctx_off, u8 **branches, 2691 void *image, void *rw_image) 2692 { 2693 u8 *prog = *pprog; 2694 int i; 2695 2696 /* The first fmod_ret program will receive a garbage return value. 2697 * Set this to 0 to avoid confusing the program. 2698 */ 2699 emit_mov_imm32(&prog, false, BPF_REG_0, 0); 2700 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2701 for (i = 0; i < tl->nr_links; i++) { 2702 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true, 2703 image, rw_image)) 2704 return -EINVAL; 2705 2706 /* mod_ret prog stored return value into [rbp - 8]. Emit: 2707 * if (*(u64 *)(rbp - 8) != 0) 2708 * goto do_fexit; 2709 */ 2710 /* cmp QWORD PTR [rbp - 0x8], 0x0 */ 2711 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00); 2712 2713 /* Save the location of the branch and Generate 6 nops 2714 * (4 bytes for an offset and 2 bytes for the jump) These nops 2715 * are replaced with a conditional jump once do_fexit (i.e. the 2716 * start of the fexit invocation) is finalized. 2717 */ 2718 branches[i] = prog; 2719 emit_nops(&prog, 4 + 2); 2720 } 2721 2722 *pprog = prog; 2723 return 0; 2724 } 2725 2726 /* Example: 2727 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev); 2728 * its 'struct btf_func_model' will be nr_args=2 2729 * The assembly code when eth_type_trans is executing after trampoline: 2730 * 2731 * push rbp 2732 * mov rbp, rsp 2733 * sub rsp, 16 // space for skb and dev 2734 * push rbx // temp regs to pass start time 2735 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack 2736 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack 2737 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2738 * mov rbx, rax // remember start time in bpf stats are enabled 2739 * lea rdi, [rbp - 16] // R1==ctx of bpf prog 2740 * call addr_of_jited_FENTRY_prog 2741 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2742 * mov rsi, rbx // prog start time 2743 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2744 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack 2745 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack 2746 * pop rbx 2747 * leave 2748 * ret 2749 * 2750 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be 2751 * replaced with 'call generated_bpf_trampoline'. When it returns 2752 * eth_type_trans will continue executing with original skb and dev pointers. 2753 * 2754 * The assembly code when eth_type_trans is called from trampoline: 2755 * 2756 * push rbp 2757 * mov rbp, rsp 2758 * sub rsp, 24 // space for skb, dev, return value 2759 * push rbx // temp regs to pass start time 2760 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack 2761 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack 2762 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2763 * mov rbx, rax // remember start time if bpf stats are enabled 2764 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 2765 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev 2766 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2767 * mov rsi, rbx // prog start time 2768 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2769 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack 2770 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack 2771 * call eth_type_trans+5 // execute body of eth_type_trans 2772 * mov qword ptr [rbp - 8], rax // save return value 2773 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 2774 * mov rbx, rax // remember start time in bpf stats are enabled 2775 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 2776 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value 2777 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 2778 * mov rsi, rbx // prog start time 2779 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 2780 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value 2781 * pop rbx 2782 * leave 2783 * add rsp, 8 // skip eth_type_trans's frame 2784 * ret // return to its caller 2785 */ 2786 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *rw_image, 2787 void *rw_image_end, void *image, 2788 const struct btf_func_model *m, u32 flags, 2789 struct bpf_tramp_links *tlinks, 2790 void *func_addr) 2791 { 2792 int i, ret, nr_regs = m->nr_args, stack_size = 0; 2793 int regs_off, nregs_off, ip_off, run_ctx_off, arg_stack_off, rbx_off; 2794 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 2795 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 2796 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 2797 void *orig_call = func_addr; 2798 u8 **branches = NULL; 2799 u8 *prog; 2800 bool save_ret; 2801 2802 /* 2803 * F_INDIRECT is only compatible with F_RET_FENTRY_RET, it is 2804 * explicitly incompatible with F_CALL_ORIG | F_SKIP_FRAME | F_IP_ARG 2805 * because @func_addr. 2806 */ 2807 WARN_ON_ONCE((flags & BPF_TRAMP_F_INDIRECT) && 2808 (flags & ~(BPF_TRAMP_F_INDIRECT | BPF_TRAMP_F_RET_FENTRY_RET))); 2809 2810 /* extra registers for struct arguments */ 2811 for (i = 0; i < m->nr_args; i++) { 2812 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) 2813 nr_regs += (m->arg_size[i] + 7) / 8 - 1; 2814 } 2815 2816 /* x86-64 supports up to MAX_BPF_FUNC_ARGS arguments. 1-6 2817 * are passed through regs, the remains are through stack. 2818 */ 2819 if (nr_regs > MAX_BPF_FUNC_ARGS) 2820 return -ENOTSUPP; 2821 2822 /* Generated trampoline stack layout: 2823 * 2824 * RBP + 8 [ return address ] 2825 * RBP + 0 [ RBP ] 2826 * 2827 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or 2828 * BPF_TRAMP_F_RET_FENTRY_RET flags 2829 * 2830 * [ reg_argN ] always 2831 * [ ... ] 2832 * RBP - regs_off [ reg_arg1 ] program's ctx pointer 2833 * 2834 * RBP - nregs_off [ regs count ] always 2835 * 2836 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag 2837 * 2838 * RBP - rbx_off [ rbx value ] always 2839 * 2840 * RBP - run_ctx_off [ bpf_tramp_run_ctx ] 2841 * 2842 * [ stack_argN ] BPF_TRAMP_F_CALL_ORIG 2843 * [ ... ] 2844 * [ stack_arg2 ] 2845 * RBP - arg_stack_off [ stack_arg1 ] 2846 * RSP [ tail_call_cnt ] BPF_TRAMP_F_TAIL_CALL_CTX 2847 */ 2848 2849 /* room for return value of orig_call or fentry prog */ 2850 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 2851 if (save_ret) 2852 stack_size += 8; 2853 2854 stack_size += nr_regs * 8; 2855 regs_off = stack_size; 2856 2857 /* regs count */ 2858 stack_size += 8; 2859 nregs_off = stack_size; 2860 2861 if (flags & BPF_TRAMP_F_IP_ARG) 2862 stack_size += 8; /* room for IP address argument */ 2863 2864 ip_off = stack_size; 2865 2866 stack_size += 8; 2867 rbx_off = stack_size; 2868 2869 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7; 2870 run_ctx_off = stack_size; 2871 2872 if (nr_regs > 6 && (flags & BPF_TRAMP_F_CALL_ORIG)) { 2873 /* the space that used to pass arguments on-stack */ 2874 stack_size += (nr_regs - get_nr_used_regs(m)) * 8; 2875 /* make sure the stack pointer is 16-byte aligned if we 2876 * need pass arguments on stack, which means 2877 * [stack_size + 8(rbp) + 8(rip) + 8(origin rip)] 2878 * should be 16-byte aligned. Following code depend on 2879 * that stack_size is already 8-byte aligned. 2880 */ 2881 stack_size += (stack_size % 16) ? 0 : 8; 2882 } 2883 2884 arg_stack_off = stack_size; 2885 2886 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 2887 /* skip patched call instruction and point orig_call to actual 2888 * body of the kernel function. 2889 */ 2890 if (is_endbr(*(u32 *)orig_call)) 2891 orig_call += ENDBR_INSN_SIZE; 2892 orig_call += X86_PATCH_SIZE; 2893 } 2894 2895 prog = rw_image; 2896 2897 if (flags & BPF_TRAMP_F_INDIRECT) { 2898 /* 2899 * Indirect call for bpf_struct_ops 2900 */ 2901 emit_cfi(&prog, cfi_get_func_hash(func_addr)); 2902 } else { 2903 /* 2904 * Direct-call fentry stub, as such it needs accounting for the 2905 * __fentry__ call. 2906 */ 2907 x86_call_depth_emit_accounting(&prog, NULL); 2908 } 2909 EMIT1(0x55); /* push rbp */ 2910 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 2911 if (!is_imm8(stack_size)) { 2912 /* sub rsp, stack_size */ 2913 EMIT3_off32(0x48, 0x81, 0xEC, stack_size); 2914 } else { 2915 /* sub rsp, stack_size */ 2916 EMIT4(0x48, 0x83, 0xEC, stack_size); 2917 } 2918 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) 2919 EMIT1(0x50); /* push rax */ 2920 /* mov QWORD PTR [rbp - rbx_off], rbx */ 2921 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_6, -rbx_off); 2922 2923 /* Store number of argument registers of the traced function: 2924 * mov rax, nr_regs 2925 * mov QWORD PTR [rbp - nregs_off], rax 2926 */ 2927 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs); 2928 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off); 2929 2930 if (flags & BPF_TRAMP_F_IP_ARG) { 2931 /* Store IP address of the traced function: 2932 * movabsq rax, func_addr 2933 * mov QWORD PTR [rbp - ip_off], rax 2934 */ 2935 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr); 2936 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off); 2937 } 2938 2939 save_args(m, &prog, regs_off, false); 2940 2941 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2942 /* arg1: mov rdi, im */ 2943 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 2944 if (emit_rsb_call(&prog, __bpf_tramp_enter, 2945 image + (prog - (u8 *)rw_image))) { 2946 ret = -EINVAL; 2947 goto cleanup; 2948 } 2949 } 2950 2951 if (fentry->nr_links) { 2952 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off, 2953 flags & BPF_TRAMP_F_RET_FENTRY_RET, image, rw_image)) 2954 return -EINVAL; 2955 } 2956 2957 if (fmod_ret->nr_links) { 2958 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *), 2959 GFP_KERNEL); 2960 if (!branches) 2961 return -ENOMEM; 2962 2963 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off, 2964 run_ctx_off, branches, image, rw_image)) { 2965 ret = -EINVAL; 2966 goto cleanup; 2967 } 2968 } 2969 2970 if (flags & BPF_TRAMP_F_CALL_ORIG) { 2971 restore_regs(m, &prog, regs_off); 2972 save_args(m, &prog, arg_stack_off, true); 2973 2974 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) { 2975 /* Before calling the original function, restore the 2976 * tail_call_cnt from stack to rax. 2977 */ 2978 RESTORE_TAIL_CALL_CNT(stack_size); 2979 } 2980 2981 if (flags & BPF_TRAMP_F_ORIG_STACK) { 2982 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, 8); 2983 EMIT2(0xff, 0xd3); /* call *rbx */ 2984 } else { 2985 /* call original function */ 2986 if (emit_rsb_call(&prog, orig_call, image + (prog - (u8 *)rw_image))) { 2987 ret = -EINVAL; 2988 goto cleanup; 2989 } 2990 } 2991 /* remember return value in a stack for bpf prog to access */ 2992 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 2993 im->ip_after_call = image + (prog - (u8 *)rw_image); 2994 emit_nops(&prog, X86_PATCH_SIZE); 2995 } 2996 2997 if (fmod_ret->nr_links) { 2998 /* From Intel 64 and IA-32 Architectures Optimization 2999 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 3000 * Coding Rule 11: All branch targets should be 16-byte 3001 * aligned. 3002 */ 3003 emit_align(&prog, 16); 3004 /* Update the branches saved in invoke_bpf_mod_ret with the 3005 * aligned address of do_fexit. 3006 */ 3007 for (i = 0; i < fmod_ret->nr_links; i++) { 3008 emit_cond_near_jump(&branches[i], image + (prog - (u8 *)rw_image), 3009 image + (branches[i] - (u8 *)rw_image), X86_JNE); 3010 } 3011 } 3012 3013 if (fexit->nr_links) { 3014 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, 3015 false, image, rw_image)) { 3016 ret = -EINVAL; 3017 goto cleanup; 3018 } 3019 } 3020 3021 if (flags & BPF_TRAMP_F_RESTORE_REGS) 3022 restore_regs(m, &prog, regs_off); 3023 3024 /* This needs to be done regardless. If there were fmod_ret programs, 3025 * the return value is only updated on the stack and still needs to be 3026 * restored to R0. 3027 */ 3028 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3029 im->ip_epilogue = image + (prog - (u8 *)rw_image); 3030 /* arg1: mov rdi, im */ 3031 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 3032 if (emit_rsb_call(&prog, __bpf_tramp_exit, image + (prog - (u8 *)rw_image))) { 3033 ret = -EINVAL; 3034 goto cleanup; 3035 } 3036 } else if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) { 3037 /* Before running the original function, restore the 3038 * tail_call_cnt from stack to rax. 3039 */ 3040 RESTORE_TAIL_CALL_CNT(stack_size); 3041 } 3042 3043 /* restore return value of orig_call or fentry prog back into RAX */ 3044 if (save_ret) 3045 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8); 3046 3047 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, -rbx_off); 3048 EMIT1(0xC9); /* leave */ 3049 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 3050 /* skip our return address and return to parent */ 3051 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */ 3052 } 3053 emit_return(&prog, image + (prog - (u8 *)rw_image)); 3054 /* Make sure the trampoline generation logic doesn't overflow */ 3055 if (WARN_ON_ONCE(prog > (u8 *)rw_image_end - BPF_INSN_SAFETY)) { 3056 ret = -EFAULT; 3057 goto cleanup; 3058 } 3059 ret = prog - (u8 *)rw_image + BPF_INSN_SAFETY; 3060 3061 cleanup: 3062 kfree(branches); 3063 return ret; 3064 } 3065 3066 void *arch_alloc_bpf_trampoline(unsigned int size) 3067 { 3068 return bpf_prog_pack_alloc(size, jit_fill_hole); 3069 } 3070 3071 void arch_free_bpf_trampoline(void *image, unsigned int size) 3072 { 3073 bpf_prog_pack_free(image, size); 3074 } 3075 3076 int arch_protect_bpf_trampoline(void *image, unsigned int size) 3077 { 3078 return 0; 3079 } 3080 3081 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end, 3082 const struct btf_func_model *m, u32 flags, 3083 struct bpf_tramp_links *tlinks, 3084 void *func_addr) 3085 { 3086 void *rw_image, *tmp; 3087 int ret; 3088 u32 size = image_end - image; 3089 3090 /* rw_image doesn't need to be in module memory range, so we can 3091 * use kvmalloc. 3092 */ 3093 rw_image = kvmalloc(size, GFP_KERNEL); 3094 if (!rw_image) 3095 return -ENOMEM; 3096 3097 ret = __arch_prepare_bpf_trampoline(im, rw_image, rw_image + size, image, m, 3098 flags, tlinks, func_addr); 3099 if (ret < 0) 3100 goto out; 3101 3102 tmp = bpf_arch_text_copy(image, rw_image, size); 3103 if (IS_ERR(tmp)) 3104 ret = PTR_ERR(tmp); 3105 out: 3106 kvfree(rw_image); 3107 return ret; 3108 } 3109 3110 int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags, 3111 struct bpf_tramp_links *tlinks, void *func_addr) 3112 { 3113 struct bpf_tramp_image im; 3114 void *image; 3115 int ret; 3116 3117 /* Allocate a temporary buffer for __arch_prepare_bpf_trampoline(). 3118 * This will NOT cause fragmentation in direct map, as we do not 3119 * call set_memory_*() on this buffer. 3120 * 3121 * We cannot use kvmalloc here, because we need image to be in 3122 * module memory range. 3123 */ 3124 image = bpf_jit_alloc_exec(PAGE_SIZE); 3125 if (!image) 3126 return -ENOMEM; 3127 3128 ret = __arch_prepare_bpf_trampoline(&im, image, image + PAGE_SIZE, image, 3129 m, flags, tlinks, func_addr); 3130 bpf_jit_free_exec(image); 3131 return ret; 3132 } 3133 3134 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf) 3135 { 3136 u8 *jg_reloc, *prog = *pprog; 3137 int pivot, err, jg_bytes = 1; 3138 s64 jg_offset; 3139 3140 if (a == b) { 3141 /* Leaf node of recursion, i.e. not a range of indices 3142 * anymore. 3143 */ 3144 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 3145 if (!is_simm32(progs[a])) 3146 return -1; 3147 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), 3148 progs[a]); 3149 err = emit_cond_near_jump(&prog, /* je func */ 3150 (void *)progs[a], image + (prog - buf), 3151 X86_JE); 3152 if (err) 3153 return err; 3154 3155 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf)); 3156 3157 *pprog = prog; 3158 return 0; 3159 } 3160 3161 /* Not a leaf node, so we pivot, and recursively descend into 3162 * the lower and upper ranges. 3163 */ 3164 pivot = (b - a) / 2; 3165 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 3166 if (!is_simm32(progs[a + pivot])) 3167 return -1; 3168 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]); 3169 3170 if (pivot > 2) { /* jg upper_part */ 3171 /* Require near jump. */ 3172 jg_bytes = 4; 3173 EMIT2_off32(0x0F, X86_JG + 0x10, 0); 3174 } else { 3175 EMIT2(X86_JG, 0); 3176 } 3177 jg_reloc = prog; 3178 3179 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */ 3180 progs, image, buf); 3181 if (err) 3182 return err; 3183 3184 /* From Intel 64 and IA-32 Architectures Optimization 3185 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 3186 * Coding Rule 11: All branch targets should be 16-byte 3187 * aligned. 3188 */ 3189 emit_align(&prog, 16); 3190 jg_offset = prog - jg_reloc; 3191 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes); 3192 3193 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */ 3194 b, progs, image, buf); 3195 if (err) 3196 return err; 3197 3198 *pprog = prog; 3199 return 0; 3200 } 3201 3202 static int cmp_ips(const void *a, const void *b) 3203 { 3204 const s64 *ipa = a; 3205 const s64 *ipb = b; 3206 3207 if (*ipa > *ipb) 3208 return 1; 3209 if (*ipa < *ipb) 3210 return -1; 3211 return 0; 3212 } 3213 3214 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs) 3215 { 3216 u8 *prog = buf; 3217 3218 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL); 3219 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf); 3220 } 3221 3222 struct x64_jit_data { 3223 struct bpf_binary_header *rw_header; 3224 struct bpf_binary_header *header; 3225 int *addrs; 3226 u8 *image; 3227 int proglen; 3228 struct jit_context ctx; 3229 }; 3230 3231 #define MAX_PASSES 20 3232 #define PADDING_PASSES (MAX_PASSES - 5) 3233 3234 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) 3235 { 3236 struct bpf_binary_header *rw_header = NULL; 3237 struct bpf_binary_header *header = NULL; 3238 struct bpf_prog *tmp, *orig_prog = prog; 3239 struct x64_jit_data *jit_data; 3240 int proglen, oldproglen = 0; 3241 struct jit_context ctx = {}; 3242 bool tmp_blinded = false; 3243 bool extra_pass = false; 3244 bool padding = false; 3245 u8 *rw_image = NULL; 3246 u8 *image = NULL; 3247 int *addrs; 3248 int pass; 3249 int i; 3250 3251 if (!prog->jit_requested) 3252 return orig_prog; 3253 3254 tmp = bpf_jit_blind_constants(prog); 3255 /* 3256 * If blinding was requested and we failed during blinding, 3257 * we must fall back to the interpreter. 3258 */ 3259 if (IS_ERR(tmp)) 3260 return orig_prog; 3261 if (tmp != prog) { 3262 tmp_blinded = true; 3263 prog = tmp; 3264 } 3265 3266 jit_data = prog->aux->jit_data; 3267 if (!jit_data) { 3268 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); 3269 if (!jit_data) { 3270 prog = orig_prog; 3271 goto out; 3272 } 3273 prog->aux->jit_data = jit_data; 3274 } 3275 addrs = jit_data->addrs; 3276 if (addrs) { 3277 ctx = jit_data->ctx; 3278 oldproglen = jit_data->proglen; 3279 image = jit_data->image; 3280 header = jit_data->header; 3281 rw_header = jit_data->rw_header; 3282 rw_image = (void *)rw_header + ((void *)image - (void *)header); 3283 extra_pass = true; 3284 padding = true; 3285 goto skip_init_addrs; 3286 } 3287 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL); 3288 if (!addrs) { 3289 prog = orig_prog; 3290 goto out_addrs; 3291 } 3292 3293 /* 3294 * Before first pass, make a rough estimation of addrs[] 3295 * each BPF instruction is translated to less than 64 bytes 3296 */ 3297 for (proglen = 0, i = 0; i <= prog->len; i++) { 3298 proglen += 64; 3299 addrs[i] = proglen; 3300 } 3301 ctx.cleanup_addr = proglen; 3302 skip_init_addrs: 3303 3304 /* 3305 * JITed image shrinks with every pass and the loop iterates 3306 * until the image stops shrinking. Very large BPF programs 3307 * may converge on the last pass. In such case do one more 3308 * pass to emit the final image. 3309 */ 3310 for (pass = 0; pass < MAX_PASSES || image; pass++) { 3311 if (!padding && pass >= PADDING_PASSES) 3312 padding = true; 3313 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding); 3314 if (proglen <= 0) { 3315 out_image: 3316 image = NULL; 3317 if (header) { 3318 bpf_arch_text_copy(&header->size, &rw_header->size, 3319 sizeof(rw_header->size)); 3320 bpf_jit_binary_pack_free(header, rw_header); 3321 } 3322 /* Fall back to interpreter mode */ 3323 prog = orig_prog; 3324 if (extra_pass) { 3325 prog->bpf_func = NULL; 3326 prog->jited = 0; 3327 prog->jited_len = 0; 3328 } 3329 goto out_addrs; 3330 } 3331 if (image) { 3332 if (proglen != oldproglen) { 3333 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n", 3334 proglen, oldproglen); 3335 goto out_image; 3336 } 3337 break; 3338 } 3339 if (proglen == oldproglen) { 3340 /* 3341 * The number of entries in extable is the number of BPF_LDX 3342 * insns that access kernel memory via "pointer to BTF type". 3343 * The verifier changed their opcode from LDX|MEM|size 3344 * to LDX|PROBE_MEM|size to make JITing easier. 3345 */ 3346 u32 align = __alignof__(struct exception_table_entry); 3347 u32 extable_size = prog->aux->num_exentries * 3348 sizeof(struct exception_table_entry); 3349 3350 /* allocate module memory for x86 insns and extable */ 3351 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size, 3352 &image, align, &rw_header, &rw_image, 3353 jit_fill_hole); 3354 if (!header) { 3355 prog = orig_prog; 3356 goto out_addrs; 3357 } 3358 prog->aux->extable = (void *) image + roundup(proglen, align); 3359 } 3360 oldproglen = proglen; 3361 cond_resched(); 3362 } 3363 3364 if (bpf_jit_enable > 1) 3365 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image); 3366 3367 if (image) { 3368 if (!prog->is_func || extra_pass) { 3369 /* 3370 * bpf_jit_binary_pack_finalize fails in two scenarios: 3371 * 1) header is not pointing to proper module memory; 3372 * 2) the arch doesn't support bpf_arch_text_copy(). 3373 * 3374 * Both cases are serious bugs and justify WARN_ON. 3375 */ 3376 if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) { 3377 /* header has been freed */ 3378 header = NULL; 3379 goto out_image; 3380 } 3381 3382 bpf_tail_call_direct_fixup(prog); 3383 } else { 3384 jit_data->addrs = addrs; 3385 jit_data->ctx = ctx; 3386 jit_data->proglen = proglen; 3387 jit_data->image = image; 3388 jit_data->header = header; 3389 jit_data->rw_header = rw_header; 3390 } 3391 /* 3392 * ctx.prog_offset is used when CFI preambles put code *before* 3393 * the function. See emit_cfi(). For FineIBT specifically this code 3394 * can also be executed and bpf_prog_kallsyms_add() will 3395 * generate an additional symbol to cover this, hence also 3396 * decrement proglen. 3397 */ 3398 prog->bpf_func = (void *)image + cfi_get_offset(); 3399 prog->jited = 1; 3400 prog->jited_len = proglen - cfi_get_offset(); 3401 } else { 3402 prog = orig_prog; 3403 } 3404 3405 if (!image || !prog->is_func || extra_pass) { 3406 if (image) 3407 bpf_prog_fill_jited_linfo(prog, addrs + 1); 3408 out_addrs: 3409 kvfree(addrs); 3410 kfree(jit_data); 3411 prog->aux->jit_data = NULL; 3412 } 3413 out: 3414 if (tmp_blinded) 3415 bpf_jit_prog_release_other(prog, prog == orig_prog ? 3416 tmp : orig_prog); 3417 return prog; 3418 } 3419 3420 bool bpf_jit_supports_kfunc_call(void) 3421 { 3422 return true; 3423 } 3424 3425 void *bpf_arch_text_copy(void *dst, void *src, size_t len) 3426 { 3427 if (text_poke_copy(dst, src, len) == NULL) 3428 return ERR_PTR(-EINVAL); 3429 return dst; 3430 } 3431 3432 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */ 3433 bool bpf_jit_supports_subprog_tailcalls(void) 3434 { 3435 return true; 3436 } 3437 3438 bool bpf_jit_supports_percpu_insn(void) 3439 { 3440 return true; 3441 } 3442 3443 void bpf_jit_free(struct bpf_prog *prog) 3444 { 3445 if (prog->jited) { 3446 struct x64_jit_data *jit_data = prog->aux->jit_data; 3447 struct bpf_binary_header *hdr; 3448 3449 /* 3450 * If we fail the final pass of JIT (from jit_subprogs), 3451 * the program may not be finalized yet. Call finalize here 3452 * before freeing it. 3453 */ 3454 if (jit_data) { 3455 bpf_jit_binary_pack_finalize(prog, jit_data->header, 3456 jit_data->rw_header); 3457 kvfree(jit_data->addrs); 3458 kfree(jit_data); 3459 } 3460 prog->bpf_func = (void *)prog->bpf_func - cfi_get_offset(); 3461 hdr = bpf_jit_binary_pack_hdr(prog); 3462 bpf_jit_binary_pack_free(hdr, NULL); 3463 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog)); 3464 } 3465 3466 bpf_prog_unlock_free(prog); 3467 } 3468 3469 bool bpf_jit_supports_exceptions(void) 3470 { 3471 /* We unwind through both kernel frames (starting from within bpf_throw 3472 * call) and BPF frames. Therefore we require ORC unwinder to be enabled 3473 * to walk kernel frames and reach BPF frames in the stack trace. 3474 */ 3475 return IS_ENABLED(CONFIG_UNWINDER_ORC); 3476 } 3477 3478 void arch_bpf_stack_walk(bool (*consume_fn)(void *cookie, u64 ip, u64 sp, u64 bp), void *cookie) 3479 { 3480 #if defined(CONFIG_UNWINDER_ORC) 3481 struct unwind_state state; 3482 unsigned long addr; 3483 3484 for (unwind_start(&state, current, NULL, NULL); !unwind_done(&state); 3485 unwind_next_frame(&state)) { 3486 addr = unwind_get_return_address(&state); 3487 if (!addr || !consume_fn(cookie, (u64)addr, (u64)state.sp, (u64)state.bp)) 3488 break; 3489 } 3490 return; 3491 #endif 3492 WARN(1, "verification of programs using bpf_throw should have failed\n"); 3493 } 3494 3495 void bpf_arch_poke_desc_update(struct bpf_jit_poke_descriptor *poke, 3496 struct bpf_prog *new, struct bpf_prog *old) 3497 { 3498 u8 *old_addr, *new_addr, *old_bypass_addr; 3499 int ret; 3500 3501 old_bypass_addr = old ? NULL : poke->bypass_addr; 3502 old_addr = old ? (u8 *)old->bpf_func + poke->adj_off : NULL; 3503 new_addr = new ? (u8 *)new->bpf_func + poke->adj_off : NULL; 3504 3505 /* 3506 * On program loading or teardown, the program's kallsym entry 3507 * might not be in place, so we use __bpf_arch_text_poke to skip 3508 * the kallsyms check. 3509 */ 3510 if (new) { 3511 ret = __bpf_arch_text_poke(poke->tailcall_target, 3512 BPF_MOD_JUMP, 3513 old_addr, new_addr); 3514 BUG_ON(ret < 0); 3515 if (!old) { 3516 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 3517 BPF_MOD_JUMP, 3518 poke->bypass_addr, 3519 NULL); 3520 BUG_ON(ret < 0); 3521 } 3522 } else { 3523 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 3524 BPF_MOD_JUMP, 3525 old_bypass_addr, 3526 poke->bypass_addr); 3527 BUG_ON(ret < 0); 3528 /* let other CPUs finish the execution of program 3529 * so that it will not possible to expose them 3530 * to invalid nop, stack unwind, nop state 3531 */ 3532 if (!ret) 3533 synchronize_rcu(); 3534 ret = __bpf_arch_text_poke(poke->tailcall_target, 3535 BPF_MOD_JUMP, 3536 old_addr, NULL); 3537 BUG_ON(ret < 0); 3538 } 3539 } 3540 3541 bool bpf_jit_supports_arena(void) 3542 { 3543 return true; 3544 } 3545 3546 bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena) 3547 { 3548 if (!in_arena) 3549 return true; 3550 switch (insn->code) { 3551 case BPF_STX | BPF_ATOMIC | BPF_W: 3552 case BPF_STX | BPF_ATOMIC | BPF_DW: 3553 if (insn->imm == (BPF_AND | BPF_FETCH) || 3554 insn->imm == (BPF_OR | BPF_FETCH) || 3555 insn->imm == (BPF_XOR | BPF_FETCH)) 3556 return false; 3557 } 3558 return true; 3559 } 3560 3561 bool bpf_jit_supports_ptr_xchg(void) 3562 { 3563 return true; 3564 } 3565