1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * BPF JIT compiler 4 * 5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com) 6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com 7 */ 8 #include <linux/netdevice.h> 9 #include <linux/filter.h> 10 #include <linux/if_vlan.h> 11 #include <linux/bitfield.h> 12 #include <linux/bpf.h> 13 #include <linux/memory.h> 14 #include <linux/sort.h> 15 #include <asm/extable.h> 16 #include <asm/ftrace.h> 17 #include <asm/set_memory.h> 18 #include <asm/nospec-branch.h> 19 #include <asm/text-patching.h> 20 #include <asm/unwind.h> 21 #include <asm/cfi.h> 22 23 static bool all_callee_regs_used[4] = {true, true, true, true}; 24 25 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len) 26 { 27 if (len == 1) 28 *ptr = bytes; 29 else if (len == 2) 30 *(u16 *)ptr = bytes; 31 else { 32 *(u32 *)ptr = bytes; 33 barrier(); 34 } 35 return ptr + len; 36 } 37 38 #define EMIT(bytes, len) \ 39 do { prog = emit_code(prog, bytes, len); } while (0) 40 41 #define EMIT1(b1) EMIT(b1, 1) 42 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2) 43 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3) 44 #define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4) 45 #define EMIT5(b1, b2, b3, b4, b5) \ 46 do { EMIT1(b1); EMIT4(b2, b3, b4, b5); } while (0) 47 48 #define EMIT1_off32(b1, off) \ 49 do { EMIT1(b1); EMIT(off, 4); } while (0) 50 #define EMIT2_off32(b1, b2, off) \ 51 do { EMIT2(b1, b2); EMIT(off, 4); } while (0) 52 #define EMIT3_off32(b1, b2, b3, off) \ 53 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0) 54 #define EMIT4_off32(b1, b2, b3, b4, off) \ 55 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0) 56 57 #ifdef CONFIG_X86_KERNEL_IBT 58 #define EMIT_ENDBR() EMIT(gen_endbr(), 4) 59 #define EMIT_ENDBR_POISON() EMIT(gen_endbr_poison(), 4) 60 #else 61 #define EMIT_ENDBR() 62 #define EMIT_ENDBR_POISON() 63 #endif 64 65 static bool is_imm8(int value) 66 { 67 return value <= 127 && value >= -128; 68 } 69 70 /* 71 * Let us limit the positive offset to be <= 123. 72 * This is to ensure eventual jit convergence For the following patterns: 73 * ... 74 * pass4, final_proglen=4391: 75 * ... 76 * 20e: 48 85 ff test rdi,rdi 77 * 211: 74 7d je 0x290 78 * 213: 48 8b 77 00 mov rsi,QWORD PTR [rdi+0x0] 79 * ... 80 * 289: 48 85 ff test rdi,rdi 81 * 28c: 74 17 je 0x2a5 82 * 28e: e9 7f ff ff ff jmp 0x212 83 * 293: bf 03 00 00 00 mov edi,0x3 84 * Note that insn at 0x211 is 2-byte cond jump insn for offset 0x7d (-125) 85 * and insn at 0x28e is 5-byte jmp insn with offset -129. 86 * 87 * pass5, final_proglen=4392: 88 * ... 89 * 20e: 48 85 ff test rdi,rdi 90 * 211: 0f 84 80 00 00 00 je 0x297 91 * 217: 48 8b 77 00 mov rsi,QWORD PTR [rdi+0x0] 92 * ... 93 * 28d: 48 85 ff test rdi,rdi 94 * 290: 74 1a je 0x2ac 95 * 292: eb 84 jmp 0x218 96 * 294: bf 03 00 00 00 mov edi,0x3 97 * Note that insn at 0x211 is 6-byte cond jump insn now since its offset 98 * becomes 0x80 based on previous round (0x293 - 0x213 = 0x80). 99 * At the same time, insn at 0x292 is a 2-byte insn since its offset is 100 * -124. 101 * 102 * pass6 will repeat the same code as in pass4 and this will prevent 103 * eventual convergence. 104 * 105 * To fix this issue, we need to break je (2->6 bytes) <-> jmp (5->2 bytes) 106 * cycle in the above. In the above example je offset <= 0x7c should work. 107 * 108 * For other cases, je <-> je needs offset <= 0x7b to avoid no convergence 109 * issue. For jmp <-> je and jmp <-> jmp cases, jmp offset <= 0x7c should 110 * avoid no convergence issue. 111 * 112 * Overall, let us limit the positive offset for 8bit cond/uncond jmp insn 113 * to maximum 123 (0x7b). This way, the jit pass can eventually converge. 114 */ 115 static bool is_imm8_jmp_offset(int value) 116 { 117 return value <= 123 && value >= -128; 118 } 119 120 static bool is_simm32(s64 value) 121 { 122 return value == (s64)(s32)value; 123 } 124 125 static bool is_uimm32(u64 value) 126 { 127 return value == (u64)(u32)value; 128 } 129 130 /* mov dst, src */ 131 #define EMIT_mov(DST, SRC) \ 132 do { \ 133 if (DST != SRC) \ 134 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \ 135 } while (0) 136 137 static int bpf_size_to_x86_bytes(int bpf_size) 138 { 139 if (bpf_size == BPF_W) 140 return 4; 141 else if (bpf_size == BPF_H) 142 return 2; 143 else if (bpf_size == BPF_B) 144 return 1; 145 else if (bpf_size == BPF_DW) 146 return 4; /* imm32 */ 147 else 148 return 0; 149 } 150 151 /* 152 * List of x86 cond jumps opcodes (. + s8) 153 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32) 154 */ 155 #define X86_JB 0x72 156 #define X86_JAE 0x73 157 #define X86_JE 0x74 158 #define X86_JNE 0x75 159 #define X86_JBE 0x76 160 #define X86_JA 0x77 161 #define X86_JL 0x7C 162 #define X86_JGE 0x7D 163 #define X86_JLE 0x7E 164 #define X86_JG 0x7F 165 166 /* Pick a register outside of BPF range for JIT internal work */ 167 #define AUX_REG (MAX_BPF_JIT_REG + 1) 168 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2) 169 #define X86_REG_R12 (MAX_BPF_JIT_REG + 3) 170 171 /* 172 * The following table maps BPF registers to x86-64 registers. 173 * 174 * x86-64 register R12 is unused, since if used as base address 175 * register in load/store instructions, it always needs an 176 * extra byte of encoding and is callee saved. 177 * 178 * x86-64 register R9 is not used by BPF programs, but can be used by BPF 179 * trampoline. x86-64 register R10 is used for blinding (if enabled). 180 */ 181 static const int reg2hex[] = { 182 [BPF_REG_0] = 0, /* RAX */ 183 [BPF_REG_1] = 7, /* RDI */ 184 [BPF_REG_2] = 6, /* RSI */ 185 [BPF_REG_3] = 2, /* RDX */ 186 [BPF_REG_4] = 1, /* RCX */ 187 [BPF_REG_5] = 0, /* R8 */ 188 [BPF_REG_6] = 3, /* RBX callee saved */ 189 [BPF_REG_7] = 5, /* R13 callee saved */ 190 [BPF_REG_8] = 6, /* R14 callee saved */ 191 [BPF_REG_9] = 7, /* R15 callee saved */ 192 [BPF_REG_FP] = 5, /* RBP readonly */ 193 [BPF_REG_AX] = 2, /* R10 temp register */ 194 [AUX_REG] = 3, /* R11 temp register */ 195 [X86_REG_R9] = 1, /* R9 register, 6th function argument */ 196 [X86_REG_R12] = 4, /* R12 callee saved */ 197 }; 198 199 static const int reg2pt_regs[] = { 200 [BPF_REG_0] = offsetof(struct pt_regs, ax), 201 [BPF_REG_1] = offsetof(struct pt_regs, di), 202 [BPF_REG_2] = offsetof(struct pt_regs, si), 203 [BPF_REG_3] = offsetof(struct pt_regs, dx), 204 [BPF_REG_4] = offsetof(struct pt_regs, cx), 205 [BPF_REG_5] = offsetof(struct pt_regs, r8), 206 [BPF_REG_6] = offsetof(struct pt_regs, bx), 207 [BPF_REG_7] = offsetof(struct pt_regs, r13), 208 [BPF_REG_8] = offsetof(struct pt_regs, r14), 209 [BPF_REG_9] = offsetof(struct pt_regs, r15), 210 }; 211 212 /* 213 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15 214 * which need extra byte of encoding. 215 * rax,rcx,...,rbp have simpler encoding 216 */ 217 static bool is_ereg(u32 reg) 218 { 219 return (1 << reg) & (BIT(BPF_REG_5) | 220 BIT(AUX_REG) | 221 BIT(BPF_REG_7) | 222 BIT(BPF_REG_8) | 223 BIT(BPF_REG_9) | 224 BIT(X86_REG_R9) | 225 BIT(X86_REG_R12) | 226 BIT(BPF_REG_AX)); 227 } 228 229 /* 230 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64 231 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte 232 * of encoding. al,cl,dl,bl have simpler encoding. 233 */ 234 static bool is_ereg_8l(u32 reg) 235 { 236 return is_ereg(reg) || 237 (1 << reg) & (BIT(BPF_REG_1) | 238 BIT(BPF_REG_2) | 239 BIT(BPF_REG_FP)); 240 } 241 242 static bool is_axreg(u32 reg) 243 { 244 return reg == BPF_REG_0; 245 } 246 247 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */ 248 static u8 add_1mod(u8 byte, u32 reg) 249 { 250 if (is_ereg(reg)) 251 byte |= 1; 252 return byte; 253 } 254 255 static u8 add_2mod(u8 byte, u32 r1, u32 r2) 256 { 257 if (is_ereg(r1)) 258 byte |= 1; 259 if (is_ereg(r2)) 260 byte |= 4; 261 return byte; 262 } 263 264 static u8 add_3mod(u8 byte, u32 r1, u32 r2, u32 index) 265 { 266 if (is_ereg(r1)) 267 byte |= 1; 268 if (is_ereg(index)) 269 byte |= 2; 270 if (is_ereg(r2)) 271 byte |= 4; 272 return byte; 273 } 274 275 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */ 276 static u8 add_1reg(u8 byte, u32 dst_reg) 277 { 278 return byte + reg2hex[dst_reg]; 279 } 280 281 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */ 282 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg) 283 { 284 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3); 285 } 286 287 /* Some 1-byte opcodes for binary ALU operations */ 288 static u8 simple_alu_opcodes[] = { 289 [BPF_ADD] = 0x01, 290 [BPF_SUB] = 0x29, 291 [BPF_AND] = 0x21, 292 [BPF_OR] = 0x09, 293 [BPF_XOR] = 0x31, 294 [BPF_LSH] = 0xE0, 295 [BPF_RSH] = 0xE8, 296 [BPF_ARSH] = 0xF8, 297 }; 298 299 static void jit_fill_hole(void *area, unsigned int size) 300 { 301 /* Fill whole space with INT3 instructions */ 302 memset(area, 0xcc, size); 303 } 304 305 int bpf_arch_text_invalidate(void *dst, size_t len) 306 { 307 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len)); 308 } 309 310 struct jit_context { 311 int cleanup_addr; /* Epilogue code offset */ 312 313 /* 314 * Program specific offsets of labels in the code; these rely on the 315 * JIT doing at least 2 passes, recording the position on the first 316 * pass, only to generate the correct offset on the second pass. 317 */ 318 int tail_call_direct_label; 319 int tail_call_indirect_label; 320 }; 321 322 /* Maximum number of bytes emitted while JITing one eBPF insn */ 323 #define BPF_MAX_INSN_SIZE 128 324 #define BPF_INSN_SAFETY 64 325 326 /* Number of bytes emit_patch() needs to generate instructions */ 327 #define X86_PATCH_SIZE 5 328 /* Number of bytes that will be skipped on tailcall */ 329 #define X86_TAIL_CALL_OFFSET (12 + ENDBR_INSN_SIZE) 330 331 static void push_r9(u8 **pprog) 332 { 333 u8 *prog = *pprog; 334 335 EMIT2(0x41, 0x51); /* push r9 */ 336 *pprog = prog; 337 } 338 339 static void pop_r9(u8 **pprog) 340 { 341 u8 *prog = *pprog; 342 343 EMIT2(0x41, 0x59); /* pop r9 */ 344 *pprog = prog; 345 } 346 347 static void push_r12(u8 **pprog) 348 { 349 u8 *prog = *pprog; 350 351 EMIT2(0x41, 0x54); /* push r12 */ 352 *pprog = prog; 353 } 354 355 static void push_callee_regs(u8 **pprog, bool *callee_regs_used) 356 { 357 u8 *prog = *pprog; 358 359 if (callee_regs_used[0]) 360 EMIT1(0x53); /* push rbx */ 361 if (callee_regs_used[1]) 362 EMIT2(0x41, 0x55); /* push r13 */ 363 if (callee_regs_used[2]) 364 EMIT2(0x41, 0x56); /* push r14 */ 365 if (callee_regs_used[3]) 366 EMIT2(0x41, 0x57); /* push r15 */ 367 *pprog = prog; 368 } 369 370 static void pop_r12(u8 **pprog) 371 { 372 u8 *prog = *pprog; 373 374 EMIT2(0x41, 0x5C); /* pop r12 */ 375 *pprog = prog; 376 } 377 378 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used) 379 { 380 u8 *prog = *pprog; 381 382 if (callee_regs_used[3]) 383 EMIT2(0x41, 0x5F); /* pop r15 */ 384 if (callee_regs_used[2]) 385 EMIT2(0x41, 0x5E); /* pop r14 */ 386 if (callee_regs_used[1]) 387 EMIT2(0x41, 0x5D); /* pop r13 */ 388 if (callee_regs_used[0]) 389 EMIT1(0x5B); /* pop rbx */ 390 *pprog = prog; 391 } 392 393 static void emit_nops(u8 **pprog, int len) 394 { 395 u8 *prog = *pprog; 396 int i, noplen; 397 398 while (len > 0) { 399 noplen = len; 400 401 if (noplen > ASM_NOP_MAX) 402 noplen = ASM_NOP_MAX; 403 404 for (i = 0; i < noplen; i++) 405 EMIT1(x86_nops[noplen][i]); 406 len -= noplen; 407 } 408 409 *pprog = prog; 410 } 411 412 /* 413 * Emit the various CFI preambles, see asm/cfi.h and the comments about FineIBT 414 * in arch/x86/kernel/alternative.c 415 */ 416 static int emit_call(u8 **prog, void *func, void *ip); 417 418 static void emit_fineibt(u8 **pprog, u8 *ip, u32 hash, int arity) 419 { 420 u8 *prog = *pprog; 421 422 EMIT_ENDBR(); 423 EMIT3_off32(0x41, 0x81, 0xea, hash); /* subl $hash, %r10d */ 424 if (cfi_bhi) { 425 emit_call(&prog, __bhi_args[arity], ip + 11); 426 } else { 427 EMIT2(0x75, 0xf9); /* jne.d8 .-7 */ 428 EMIT3(0x0f, 0x1f, 0x00); /* nop3 */ 429 } 430 EMIT_ENDBR_POISON(); 431 432 *pprog = prog; 433 } 434 435 static void emit_kcfi(u8 **pprog, u32 hash) 436 { 437 u8 *prog = *pprog; 438 439 EMIT1_off32(0xb8, hash); /* movl $hash, %eax */ 440 #ifdef CONFIG_CALL_PADDING 441 EMIT1(0x90); 442 EMIT1(0x90); 443 EMIT1(0x90); 444 EMIT1(0x90); 445 EMIT1(0x90); 446 EMIT1(0x90); 447 EMIT1(0x90); 448 EMIT1(0x90); 449 EMIT1(0x90); 450 EMIT1(0x90); 451 EMIT1(0x90); 452 #endif 453 EMIT_ENDBR(); 454 455 *pprog = prog; 456 } 457 458 static void emit_cfi(u8 **pprog, u8 *ip, u32 hash, int arity) 459 { 460 u8 *prog = *pprog; 461 462 switch (cfi_mode) { 463 case CFI_FINEIBT: 464 emit_fineibt(&prog, ip, hash, arity); 465 break; 466 467 case CFI_KCFI: 468 emit_kcfi(&prog, hash); 469 break; 470 471 default: 472 EMIT_ENDBR(); 473 break; 474 } 475 476 *pprog = prog; 477 } 478 479 static void emit_prologue_tail_call(u8 **pprog, bool is_subprog) 480 { 481 u8 *prog = *pprog; 482 483 if (!is_subprog) { 484 /* cmp rax, MAX_TAIL_CALL_CNT */ 485 EMIT4(0x48, 0x83, 0xF8, MAX_TAIL_CALL_CNT); 486 EMIT2(X86_JA, 6); /* ja 6 */ 487 /* rax is tail_call_cnt if <= MAX_TAIL_CALL_CNT. 488 * case1: entry of main prog. 489 * case2: tail callee of main prog. 490 */ 491 EMIT1(0x50); /* push rax */ 492 /* Make rax as tail_call_cnt_ptr. */ 493 EMIT3(0x48, 0x89, 0xE0); /* mov rax, rsp */ 494 EMIT2(0xEB, 1); /* jmp 1 */ 495 /* rax is tail_call_cnt_ptr if > MAX_TAIL_CALL_CNT. 496 * case: tail callee of subprog. 497 */ 498 EMIT1(0x50); /* push rax */ 499 /* push tail_call_cnt_ptr */ 500 EMIT1(0x50); /* push rax */ 501 } else { /* is_subprog */ 502 /* rax is tail_call_cnt_ptr. */ 503 EMIT1(0x50); /* push rax */ 504 EMIT1(0x50); /* push rax */ 505 } 506 507 *pprog = prog; 508 } 509 510 /* 511 * Emit x86-64 prologue code for BPF program. 512 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes 513 * while jumping to another program 514 */ 515 static void emit_prologue(u8 **pprog, u8 *ip, u32 stack_depth, bool ebpf_from_cbpf, 516 bool tail_call_reachable, bool is_subprog, 517 bool is_exception_cb) 518 { 519 u8 *prog = *pprog; 520 521 if (is_subprog) { 522 emit_cfi(&prog, ip, cfi_bpf_subprog_hash, 5); 523 } else { 524 emit_cfi(&prog, ip, cfi_bpf_hash, 1); 525 } 526 /* BPF trampoline can be made to work without these nops, 527 * but let's waste 5 bytes for now and optimize later 528 */ 529 emit_nops(&prog, X86_PATCH_SIZE); 530 if (!ebpf_from_cbpf) { 531 if (tail_call_reachable && !is_subprog) 532 /* When it's the entry of the whole tailcall context, 533 * zeroing rax means initialising tail_call_cnt. 534 */ 535 EMIT3(0x48, 0x31, 0xC0); /* xor rax, rax */ 536 else 537 /* Keep the same instruction layout. */ 538 emit_nops(&prog, 3); /* nop3 */ 539 } 540 /* Exception callback receives FP as third parameter */ 541 if (is_exception_cb) { 542 EMIT3(0x48, 0x89, 0xF4); /* mov rsp, rsi */ 543 EMIT3(0x48, 0x89, 0xD5); /* mov rbp, rdx */ 544 /* The main frame must have exception_boundary as true, so we 545 * first restore those callee-saved regs from stack, before 546 * reusing the stack frame. 547 */ 548 pop_callee_regs(&prog, all_callee_regs_used); 549 pop_r12(&prog); 550 /* Reset the stack frame. */ 551 EMIT3(0x48, 0x89, 0xEC); /* mov rsp, rbp */ 552 } else { 553 EMIT1(0x55); /* push rbp */ 554 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 555 } 556 557 /* X86_TAIL_CALL_OFFSET is here */ 558 EMIT_ENDBR(); 559 560 /* sub rsp, rounded_stack_depth */ 561 if (stack_depth) 562 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8)); 563 if (tail_call_reachable) 564 emit_prologue_tail_call(&prog, is_subprog); 565 *pprog = prog; 566 } 567 568 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode) 569 { 570 u8 *prog = *pprog; 571 s64 offset; 572 573 offset = func - (ip + X86_PATCH_SIZE); 574 if (!is_simm32(offset)) { 575 pr_err("Target call %p is out of range\n", func); 576 return -ERANGE; 577 } 578 EMIT1_off32(opcode, offset); 579 *pprog = prog; 580 return 0; 581 } 582 583 static int emit_call(u8 **pprog, void *func, void *ip) 584 { 585 return emit_patch(pprog, func, ip, 0xE8); 586 } 587 588 static int emit_rsb_call(u8 **pprog, void *func, void *ip) 589 { 590 OPTIMIZER_HIDE_VAR(func); 591 ip += x86_call_depth_emit_accounting(pprog, func, ip); 592 return emit_patch(pprog, func, ip, 0xE8); 593 } 594 595 static int emit_jump(u8 **pprog, void *func, void *ip) 596 { 597 return emit_patch(pprog, func, ip, 0xE9); 598 } 599 600 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 601 void *old_addr, void *new_addr) 602 { 603 const u8 *nop_insn = x86_nops[5]; 604 u8 old_insn[X86_PATCH_SIZE]; 605 u8 new_insn[X86_PATCH_SIZE]; 606 u8 *prog; 607 int ret; 608 609 memcpy(old_insn, nop_insn, X86_PATCH_SIZE); 610 if (old_addr) { 611 prog = old_insn; 612 ret = t == BPF_MOD_CALL ? 613 emit_call(&prog, old_addr, ip) : 614 emit_jump(&prog, old_addr, ip); 615 if (ret) 616 return ret; 617 } 618 619 memcpy(new_insn, nop_insn, X86_PATCH_SIZE); 620 if (new_addr) { 621 prog = new_insn; 622 ret = t == BPF_MOD_CALL ? 623 emit_call(&prog, new_addr, ip) : 624 emit_jump(&prog, new_addr, ip); 625 if (ret) 626 return ret; 627 } 628 629 ret = -EBUSY; 630 mutex_lock(&text_mutex); 631 if (memcmp(ip, old_insn, X86_PATCH_SIZE)) 632 goto out; 633 ret = 1; 634 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) { 635 smp_text_poke_single(ip, new_insn, X86_PATCH_SIZE, NULL); 636 ret = 0; 637 } 638 out: 639 mutex_unlock(&text_mutex); 640 return ret; 641 } 642 643 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, 644 void *old_addr, void *new_addr) 645 { 646 if (!is_kernel_text((long)ip) && 647 !is_bpf_text_address((long)ip)) 648 /* BPF poking in modules is not supported */ 649 return -EINVAL; 650 651 /* 652 * See emit_prologue(), for IBT builds the trampoline hook is preceded 653 * with an ENDBR instruction. 654 */ 655 if (is_endbr(ip)) 656 ip += ENDBR_INSN_SIZE; 657 658 return __bpf_arch_text_poke(ip, t, old_addr, new_addr); 659 } 660 661 #define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8) 662 663 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip) 664 { 665 u8 *prog = *pprog; 666 667 if (cpu_feature_enabled(X86_FEATURE_INDIRECT_THUNK_ITS)) { 668 OPTIMIZER_HIDE_VAR(reg); 669 emit_jump(&prog, its_static_thunk(reg), ip); 670 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) { 671 EMIT_LFENCE(); 672 EMIT2(0xFF, 0xE0 + reg); 673 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) { 674 OPTIMIZER_HIDE_VAR(reg); 675 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH)) 676 emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip); 677 else 678 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip); 679 } else { 680 EMIT2(0xFF, 0xE0 + reg); /* jmp *%\reg */ 681 if (IS_ENABLED(CONFIG_MITIGATION_RETPOLINE) || IS_ENABLED(CONFIG_MITIGATION_SLS)) 682 EMIT1(0xCC); /* int3 */ 683 } 684 685 *pprog = prog; 686 } 687 688 static void emit_return(u8 **pprog, u8 *ip) 689 { 690 u8 *prog = *pprog; 691 692 if (cpu_wants_rethunk()) { 693 emit_jump(&prog, x86_return_thunk, ip); 694 } else { 695 EMIT1(0xC3); /* ret */ 696 if (IS_ENABLED(CONFIG_MITIGATION_SLS)) 697 EMIT1(0xCC); /* int3 */ 698 } 699 700 *pprog = prog; 701 } 702 703 #define BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack) (-16 - round_up(stack, 8)) 704 705 /* 706 * Generate the following code: 707 * 708 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ... 709 * if (index >= array->map.max_entries) 710 * goto out; 711 * if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT) 712 * goto out; 713 * prog = array->ptrs[index]; 714 * if (prog == NULL) 715 * goto out; 716 * goto *(prog->bpf_func + prologue_size); 717 * out: 718 */ 719 static void emit_bpf_tail_call_indirect(struct bpf_prog *bpf_prog, 720 u8 **pprog, bool *callee_regs_used, 721 u32 stack_depth, u8 *ip, 722 struct jit_context *ctx) 723 { 724 int tcc_ptr_off = BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack_depth); 725 u8 *prog = *pprog, *start = *pprog; 726 int offset; 727 728 /* 729 * rdi - pointer to ctx 730 * rsi - pointer to bpf_array 731 * rdx - index in bpf_array 732 */ 733 734 /* 735 * if (index >= array->map.max_entries) 736 * goto out; 737 */ 738 EMIT2(0x89, 0xD2); /* mov edx, edx */ 739 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */ 740 offsetof(struct bpf_array, map.max_entries)); 741 742 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 743 EMIT2(X86_JBE, offset); /* jbe out */ 744 745 /* 746 * if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT) 747 * goto out; 748 */ 749 EMIT3_off32(0x48, 0x8B, 0x85, tcc_ptr_off); /* mov rax, qword ptr [rbp - tcc_ptr_off] */ 750 EMIT4(0x48, 0x83, 0x38, MAX_TAIL_CALL_CNT); /* cmp qword ptr [rax], MAX_TAIL_CALL_CNT */ 751 752 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 753 EMIT2(X86_JAE, offset); /* jae out */ 754 755 /* prog = array->ptrs[index]; */ 756 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */ 757 offsetof(struct bpf_array, ptrs)); 758 759 /* 760 * if (prog == NULL) 761 * goto out; 762 */ 763 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */ 764 765 offset = ctx->tail_call_indirect_label - (prog + 2 - start); 766 EMIT2(X86_JE, offset); /* je out */ 767 768 /* Inc tail_call_cnt if the slot is populated. */ 769 EMIT4(0x48, 0x83, 0x00, 0x01); /* add qword ptr [rax], 1 */ 770 771 if (bpf_prog->aux->exception_boundary) { 772 pop_callee_regs(&prog, all_callee_regs_used); 773 pop_r12(&prog); 774 } else { 775 pop_callee_regs(&prog, callee_regs_used); 776 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena)) 777 pop_r12(&prog); 778 } 779 780 /* Pop tail_call_cnt_ptr. */ 781 EMIT1(0x58); /* pop rax */ 782 /* Pop tail_call_cnt, if it's main prog. 783 * Pop tail_call_cnt_ptr, if it's subprog. 784 */ 785 EMIT1(0x58); /* pop rax */ 786 if (stack_depth) 787 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */ 788 round_up(stack_depth, 8)); 789 790 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */ 791 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */ 792 offsetof(struct bpf_prog, bpf_func)); 793 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */ 794 X86_TAIL_CALL_OFFSET); 795 /* 796 * Now we're ready to jump into next BPF program 797 * rdi == ctx (1st arg) 798 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET 799 */ 800 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start)); 801 802 /* out: */ 803 ctx->tail_call_indirect_label = prog - start; 804 *pprog = prog; 805 } 806 807 static void emit_bpf_tail_call_direct(struct bpf_prog *bpf_prog, 808 struct bpf_jit_poke_descriptor *poke, 809 u8 **pprog, u8 *ip, 810 bool *callee_regs_used, u32 stack_depth, 811 struct jit_context *ctx) 812 { 813 int tcc_ptr_off = BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack_depth); 814 u8 *prog = *pprog, *start = *pprog; 815 int offset; 816 817 /* 818 * if ((*tcc_ptr)++ >= MAX_TAIL_CALL_CNT) 819 * goto out; 820 */ 821 EMIT3_off32(0x48, 0x8B, 0x85, tcc_ptr_off); /* mov rax, qword ptr [rbp - tcc_ptr_off] */ 822 EMIT4(0x48, 0x83, 0x38, MAX_TAIL_CALL_CNT); /* cmp qword ptr [rax], MAX_TAIL_CALL_CNT */ 823 824 offset = ctx->tail_call_direct_label - (prog + 2 - start); 825 EMIT2(X86_JAE, offset); /* jae out */ 826 827 poke->tailcall_bypass = ip + (prog - start); 828 poke->adj_off = X86_TAIL_CALL_OFFSET; 829 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE; 830 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE; 831 832 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE, 833 poke->tailcall_bypass); 834 835 /* Inc tail_call_cnt if the slot is populated. */ 836 EMIT4(0x48, 0x83, 0x00, 0x01); /* add qword ptr [rax], 1 */ 837 838 if (bpf_prog->aux->exception_boundary) { 839 pop_callee_regs(&prog, all_callee_regs_used); 840 pop_r12(&prog); 841 } else { 842 pop_callee_regs(&prog, callee_regs_used); 843 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena)) 844 pop_r12(&prog); 845 } 846 847 /* Pop tail_call_cnt_ptr. */ 848 EMIT1(0x58); /* pop rax */ 849 /* Pop tail_call_cnt, if it's main prog. 850 * Pop tail_call_cnt_ptr, if it's subprog. 851 */ 852 EMIT1(0x58); /* pop rax */ 853 if (stack_depth) 854 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8)); 855 856 emit_nops(&prog, X86_PATCH_SIZE); 857 858 /* out: */ 859 ctx->tail_call_direct_label = prog - start; 860 861 *pprog = prog; 862 } 863 864 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog) 865 { 866 struct bpf_jit_poke_descriptor *poke; 867 struct bpf_array *array; 868 struct bpf_prog *target; 869 int i, ret; 870 871 for (i = 0; i < prog->aux->size_poke_tab; i++) { 872 poke = &prog->aux->poke_tab[i]; 873 if (poke->aux && poke->aux != prog->aux) 874 continue; 875 876 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable)); 877 878 if (poke->reason != BPF_POKE_REASON_TAIL_CALL) 879 continue; 880 881 array = container_of(poke->tail_call.map, struct bpf_array, map); 882 mutex_lock(&array->aux->poke_mutex); 883 target = array->ptrs[poke->tail_call.key]; 884 if (target) { 885 ret = __bpf_arch_text_poke(poke->tailcall_target, 886 BPF_MOD_JUMP, NULL, 887 (u8 *)target->bpf_func + 888 poke->adj_off); 889 BUG_ON(ret < 0); 890 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 891 BPF_MOD_JUMP, 892 (u8 *)poke->tailcall_target + 893 X86_PATCH_SIZE, NULL); 894 BUG_ON(ret < 0); 895 } 896 WRITE_ONCE(poke->tailcall_target_stable, true); 897 mutex_unlock(&array->aux->poke_mutex); 898 } 899 } 900 901 static void emit_mov_imm32(u8 **pprog, bool sign_propagate, 902 u32 dst_reg, const u32 imm32) 903 { 904 u8 *prog = *pprog; 905 u8 b1, b2, b3; 906 907 /* 908 * Optimization: if imm32 is positive, use 'mov %eax, imm32' 909 * (which zero-extends imm32) to save 2 bytes. 910 */ 911 if (sign_propagate && (s32)imm32 < 0) { 912 /* 'mov %rax, imm32' sign extends imm32 */ 913 b1 = add_1mod(0x48, dst_reg); 914 b2 = 0xC7; 915 b3 = 0xC0; 916 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32); 917 goto done; 918 } 919 920 /* 921 * Optimization: if imm32 is zero, use 'xor %eax, %eax' 922 * to save 3 bytes. 923 */ 924 if (imm32 == 0) { 925 if (is_ereg(dst_reg)) 926 EMIT1(add_2mod(0x40, dst_reg, dst_reg)); 927 b2 = 0x31; /* xor */ 928 b3 = 0xC0; 929 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg)); 930 goto done; 931 } 932 933 /* mov %eax, imm32 */ 934 if (is_ereg(dst_reg)) 935 EMIT1(add_1mod(0x40, dst_reg)); 936 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32); 937 done: 938 *pprog = prog; 939 } 940 941 static void emit_mov_imm64(u8 **pprog, u32 dst_reg, 942 const u32 imm32_hi, const u32 imm32_lo) 943 { 944 u64 imm64 = ((u64)imm32_hi << 32) | (u32)imm32_lo; 945 u8 *prog = *pprog; 946 947 if (is_uimm32(imm64)) { 948 /* 949 * For emitting plain u32, where sign bit must not be 950 * propagated LLVM tends to load imm64 over mov32 951 * directly, so save couple of bytes by just doing 952 * 'mov %eax, imm32' instead. 953 */ 954 emit_mov_imm32(&prog, false, dst_reg, imm32_lo); 955 } else if (is_simm32(imm64)) { 956 emit_mov_imm32(&prog, true, dst_reg, imm32_lo); 957 } else { 958 /* movabsq rax, imm64 */ 959 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg)); 960 EMIT(imm32_lo, 4); 961 EMIT(imm32_hi, 4); 962 } 963 964 *pprog = prog; 965 } 966 967 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg) 968 { 969 u8 *prog = *pprog; 970 971 if (is64) { 972 /* mov dst, src */ 973 EMIT_mov(dst_reg, src_reg); 974 } else { 975 /* mov32 dst, src */ 976 if (is_ereg(dst_reg) || is_ereg(src_reg)) 977 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 978 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg)); 979 } 980 981 *pprog = prog; 982 } 983 984 static void emit_movsx_reg(u8 **pprog, int num_bits, bool is64, u32 dst_reg, 985 u32 src_reg) 986 { 987 u8 *prog = *pprog; 988 989 if (is64) { 990 /* movs[b,w,l]q dst, src */ 991 if (num_bits == 8) 992 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbe, 993 add_2reg(0xC0, src_reg, dst_reg)); 994 else if (num_bits == 16) 995 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbf, 996 add_2reg(0xC0, src_reg, dst_reg)); 997 else if (num_bits == 32) 998 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x63, 999 add_2reg(0xC0, src_reg, dst_reg)); 1000 } else { 1001 /* movs[b,w]l dst, src */ 1002 if (num_bits == 8) { 1003 EMIT4(add_2mod(0x40, src_reg, dst_reg), 0x0f, 0xbe, 1004 add_2reg(0xC0, src_reg, dst_reg)); 1005 } else if (num_bits == 16) { 1006 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1007 EMIT1(add_2mod(0x40, src_reg, dst_reg)); 1008 EMIT3(add_2mod(0x0f, src_reg, dst_reg), 0xbf, 1009 add_2reg(0xC0, src_reg, dst_reg)); 1010 } 1011 } 1012 1013 *pprog = prog; 1014 } 1015 1016 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */ 1017 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off) 1018 { 1019 u8 *prog = *pprog; 1020 1021 if (is_imm8(off)) { 1022 /* 1-byte signed displacement. 1023 * 1024 * If off == 0 we could skip this and save one extra byte, but 1025 * special case of x86 R13 which always needs an offset is not 1026 * worth the hassle 1027 */ 1028 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off); 1029 } else { 1030 /* 4-byte signed displacement */ 1031 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off); 1032 } 1033 *pprog = prog; 1034 } 1035 1036 static void emit_insn_suffix_SIB(u8 **pprog, u32 ptr_reg, u32 val_reg, u32 index_reg, int off) 1037 { 1038 u8 *prog = *pprog; 1039 1040 if (is_imm8(off)) { 1041 EMIT3(add_2reg(0x44, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off); 1042 } else { 1043 EMIT2_off32(add_2reg(0x84, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off); 1044 } 1045 *pprog = prog; 1046 } 1047 1048 /* 1049 * Emit a REX byte if it will be necessary to address these registers 1050 */ 1051 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64) 1052 { 1053 u8 *prog = *pprog; 1054 1055 if (is64) 1056 EMIT1(add_2mod(0x48, dst_reg, src_reg)); 1057 else if (is_ereg(dst_reg) || is_ereg(src_reg)) 1058 EMIT1(add_2mod(0x40, dst_reg, src_reg)); 1059 *pprog = prog; 1060 } 1061 1062 /* 1063 * Similar version of maybe_emit_mod() for a single register 1064 */ 1065 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64) 1066 { 1067 u8 *prog = *pprog; 1068 1069 if (is64) 1070 EMIT1(add_1mod(0x48, reg)); 1071 else if (is_ereg(reg)) 1072 EMIT1(add_1mod(0x40, reg)); 1073 *pprog = prog; 1074 } 1075 1076 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 1077 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1078 { 1079 u8 *prog = *pprog; 1080 1081 switch (size) { 1082 case BPF_B: 1083 /* Emit 'movzx rax, byte ptr [rax + off]' */ 1084 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6); 1085 break; 1086 case BPF_H: 1087 /* Emit 'movzx rax, word ptr [rax + off]' */ 1088 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7); 1089 break; 1090 case BPF_W: 1091 /* Emit 'mov eax, dword ptr [rax+0x14]' */ 1092 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1093 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B); 1094 else 1095 EMIT1(0x8B); 1096 break; 1097 case BPF_DW: 1098 /* Emit 'mov rax, qword ptr [rax+0x14]' */ 1099 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B); 1100 break; 1101 } 1102 emit_insn_suffix(&prog, src_reg, dst_reg, off); 1103 *pprog = prog; 1104 } 1105 1106 /* LDSX: dst_reg = *(s8*)(src_reg + off) */ 1107 static void emit_ldsx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1108 { 1109 u8 *prog = *pprog; 1110 1111 switch (size) { 1112 case BPF_B: 1113 /* Emit 'movsx rax, byte ptr [rax + off]' */ 1114 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBE); 1115 break; 1116 case BPF_H: 1117 /* Emit 'movsx rax, word ptr [rax + off]' */ 1118 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBF); 1119 break; 1120 case BPF_W: 1121 /* Emit 'movsx rax, dword ptr [rax+0x14]' */ 1122 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x63); 1123 break; 1124 } 1125 emit_insn_suffix(&prog, src_reg, dst_reg, off); 1126 *pprog = prog; 1127 } 1128 1129 static void emit_ldx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1130 { 1131 u8 *prog = *pprog; 1132 1133 switch (size) { 1134 case BPF_B: 1135 /* movzx rax, byte ptr [rax + r12 + off] */ 1136 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB6); 1137 break; 1138 case BPF_H: 1139 /* movzx rax, word ptr [rax + r12 + off] */ 1140 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB7); 1141 break; 1142 case BPF_W: 1143 /* mov eax, dword ptr [rax + r12 + off] */ 1144 EMIT2(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x8B); 1145 break; 1146 case BPF_DW: 1147 /* mov rax, qword ptr [rax + r12 + off] */ 1148 EMIT2(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x8B); 1149 break; 1150 } 1151 emit_insn_suffix_SIB(&prog, src_reg, dst_reg, index_reg, off); 1152 *pprog = prog; 1153 } 1154 1155 static void emit_ldsx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1156 { 1157 u8 *prog = *pprog; 1158 1159 switch (size) { 1160 case BPF_B: 1161 /* movsx rax, byte ptr [rax + r12 + off] */ 1162 EMIT3(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x0F, 0xBE); 1163 break; 1164 case BPF_H: 1165 /* movsx rax, word ptr [rax + r12 + off] */ 1166 EMIT3(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x0F, 0xBF); 1167 break; 1168 case BPF_W: 1169 /* movsx rax, dword ptr [rax + r12 + off] */ 1170 EMIT2(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x63); 1171 break; 1172 } 1173 emit_insn_suffix_SIB(&prog, src_reg, dst_reg, index_reg, off); 1174 *pprog = prog; 1175 } 1176 1177 static void emit_ldx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1178 { 1179 emit_ldx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off); 1180 } 1181 1182 static void emit_ldsx_r12(u8 **prog, u32 size, u32 dst_reg, u32 src_reg, int off) 1183 { 1184 emit_ldsx_index(prog, size, dst_reg, src_reg, X86_REG_R12, off); 1185 } 1186 1187 /* STX: *(u8*)(dst_reg + off) = src_reg */ 1188 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1189 { 1190 u8 *prog = *pprog; 1191 1192 switch (size) { 1193 case BPF_B: 1194 /* Emit 'mov byte ptr [rax + off], al' */ 1195 if (is_ereg(dst_reg) || is_ereg_8l(src_reg)) 1196 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */ 1197 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88); 1198 else 1199 EMIT1(0x88); 1200 break; 1201 case BPF_H: 1202 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1203 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89); 1204 else 1205 EMIT2(0x66, 0x89); 1206 break; 1207 case BPF_W: 1208 if (is_ereg(dst_reg) || is_ereg(src_reg)) 1209 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89); 1210 else 1211 EMIT1(0x89); 1212 break; 1213 case BPF_DW: 1214 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89); 1215 break; 1216 } 1217 emit_insn_suffix(&prog, dst_reg, src_reg, off); 1218 *pprog = prog; 1219 } 1220 1221 /* STX: *(u8*)(dst_reg + index_reg + off) = src_reg */ 1222 static void emit_stx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off) 1223 { 1224 u8 *prog = *pprog; 1225 1226 switch (size) { 1227 case BPF_B: 1228 /* mov byte ptr [rax + r12 + off], al */ 1229 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x88); 1230 break; 1231 case BPF_H: 1232 /* mov word ptr [rax + r12 + off], ax */ 1233 EMIT3(0x66, add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89); 1234 break; 1235 case BPF_W: 1236 /* mov dword ptr [rax + r12 + 1], eax */ 1237 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89); 1238 break; 1239 case BPF_DW: 1240 /* mov qword ptr [rax + r12 + 1], rax */ 1241 EMIT2(add_3mod(0x48, dst_reg, src_reg, index_reg), 0x89); 1242 break; 1243 } 1244 emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off); 1245 *pprog = prog; 1246 } 1247 1248 static void emit_stx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off) 1249 { 1250 emit_stx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off); 1251 } 1252 1253 /* ST: *(u8*)(dst_reg + index_reg + off) = imm32 */ 1254 static void emit_st_index(u8 **pprog, u32 size, u32 dst_reg, u32 index_reg, int off, int imm) 1255 { 1256 u8 *prog = *pprog; 1257 1258 switch (size) { 1259 case BPF_B: 1260 /* mov byte ptr [rax + r12 + off], imm8 */ 1261 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC6); 1262 break; 1263 case BPF_H: 1264 /* mov word ptr [rax + r12 + off], imm16 */ 1265 EMIT3(0x66, add_3mod(0x40, dst_reg, 0, index_reg), 0xC7); 1266 break; 1267 case BPF_W: 1268 /* mov dword ptr [rax + r12 + 1], imm32 */ 1269 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC7); 1270 break; 1271 case BPF_DW: 1272 /* mov qword ptr [rax + r12 + 1], imm32 */ 1273 EMIT2(add_3mod(0x48, dst_reg, 0, index_reg), 0xC7); 1274 break; 1275 } 1276 emit_insn_suffix_SIB(&prog, dst_reg, 0, index_reg, off); 1277 EMIT(imm, bpf_size_to_x86_bytes(size)); 1278 *pprog = prog; 1279 } 1280 1281 static void emit_st_r12(u8 **pprog, u32 size, u32 dst_reg, int off, int imm) 1282 { 1283 emit_st_index(pprog, size, dst_reg, X86_REG_R12, off, imm); 1284 } 1285 1286 static int emit_atomic_rmw(u8 **pprog, u32 atomic_op, 1287 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size) 1288 { 1289 u8 *prog = *pprog; 1290 1291 EMIT1(0xF0); /* lock prefix */ 1292 1293 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW); 1294 1295 /* emit opcode */ 1296 switch (atomic_op) { 1297 case BPF_ADD: 1298 case BPF_AND: 1299 case BPF_OR: 1300 case BPF_XOR: 1301 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */ 1302 EMIT1(simple_alu_opcodes[atomic_op]); 1303 break; 1304 case BPF_ADD | BPF_FETCH: 1305 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */ 1306 EMIT2(0x0F, 0xC1); 1307 break; 1308 case BPF_XCHG: 1309 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */ 1310 EMIT1(0x87); 1311 break; 1312 case BPF_CMPXCHG: 1313 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */ 1314 EMIT2(0x0F, 0xB1); 1315 break; 1316 default: 1317 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 1318 return -EFAULT; 1319 } 1320 1321 emit_insn_suffix(&prog, dst_reg, src_reg, off); 1322 1323 *pprog = prog; 1324 return 0; 1325 } 1326 1327 static int emit_atomic_rmw_index(u8 **pprog, u32 atomic_op, u32 size, 1328 u32 dst_reg, u32 src_reg, u32 index_reg, 1329 int off) 1330 { 1331 u8 *prog = *pprog; 1332 1333 EMIT1(0xF0); /* lock prefix */ 1334 switch (size) { 1335 case BPF_W: 1336 EMIT1(add_3mod(0x40, dst_reg, src_reg, index_reg)); 1337 break; 1338 case BPF_DW: 1339 EMIT1(add_3mod(0x48, dst_reg, src_reg, index_reg)); 1340 break; 1341 default: 1342 pr_err("bpf_jit: 1- and 2-byte RMW atomics are not supported\n"); 1343 return -EFAULT; 1344 } 1345 1346 /* emit opcode */ 1347 switch (atomic_op) { 1348 case BPF_ADD: 1349 case BPF_AND: 1350 case BPF_OR: 1351 case BPF_XOR: 1352 /* lock *(u32/u64*)(dst_reg + idx_reg + off) <op>= src_reg */ 1353 EMIT1(simple_alu_opcodes[atomic_op]); 1354 break; 1355 case BPF_ADD | BPF_FETCH: 1356 /* src_reg = atomic_fetch_add(dst_reg + idx_reg + off, src_reg); */ 1357 EMIT2(0x0F, 0xC1); 1358 break; 1359 case BPF_XCHG: 1360 /* src_reg = atomic_xchg(dst_reg + idx_reg + off, src_reg); */ 1361 EMIT1(0x87); 1362 break; 1363 case BPF_CMPXCHG: 1364 /* r0 = atomic_cmpxchg(dst_reg + idx_reg + off, r0, src_reg); */ 1365 EMIT2(0x0F, 0xB1); 1366 break; 1367 default: 1368 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op); 1369 return -EFAULT; 1370 } 1371 emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off); 1372 *pprog = prog; 1373 return 0; 1374 } 1375 1376 static int emit_atomic_ld_st(u8 **pprog, u32 atomic_op, u32 dst_reg, 1377 u32 src_reg, s16 off, u8 bpf_size) 1378 { 1379 switch (atomic_op) { 1380 case BPF_LOAD_ACQ: 1381 /* dst_reg = smp_load_acquire(src_reg + off16) */ 1382 emit_ldx(pprog, bpf_size, dst_reg, src_reg, off); 1383 break; 1384 case BPF_STORE_REL: 1385 /* smp_store_release(dst_reg + off16, src_reg) */ 1386 emit_stx(pprog, bpf_size, dst_reg, src_reg, off); 1387 break; 1388 default: 1389 pr_err("bpf_jit: unknown atomic load/store opcode %02x\n", 1390 atomic_op); 1391 return -EFAULT; 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int emit_atomic_ld_st_index(u8 **pprog, u32 atomic_op, u32 size, 1398 u32 dst_reg, u32 src_reg, u32 index_reg, 1399 int off) 1400 { 1401 switch (atomic_op) { 1402 case BPF_LOAD_ACQ: 1403 /* dst_reg = smp_load_acquire(src_reg + idx_reg + off16) */ 1404 emit_ldx_index(pprog, size, dst_reg, src_reg, index_reg, off); 1405 break; 1406 case BPF_STORE_REL: 1407 /* smp_store_release(dst_reg + idx_reg + off16, src_reg) */ 1408 emit_stx_index(pprog, size, dst_reg, src_reg, index_reg, off); 1409 break; 1410 default: 1411 pr_err("bpf_jit: unknown atomic load/store opcode %02x\n", 1412 atomic_op); 1413 return -EFAULT; 1414 } 1415 1416 return 0; 1417 } 1418 1419 /* 1420 * Metadata encoding for exception handling in JITed code. 1421 * 1422 * Format of `fixup` and `data` fields in `struct exception_table_entry`: 1423 * 1424 * Bit layout of `fixup` (32-bit): 1425 * 1426 * +-----------+--------+-----------+---------+----------+ 1427 * | 31 | 30-24 | 23-16 | 15-8 | 7-0 | 1428 * | | | | | | 1429 * | ARENA_ACC | Unused | ARENA_REG | DST_REG | INSN_LEN | 1430 * +-----------+--------+-----------+---------+----------+ 1431 * 1432 * - INSN_LEN (8 bits): Length of faulting insn (max x86 insn = 15 bytes (fits in 8 bits)). 1433 * - DST_REG (8 bits): Offset of dst_reg from reg2pt_regs[] (max offset = 112 (fits in 8 bits)). 1434 * This is set to DONT_CLEAR if the insn is a store. 1435 * - ARENA_REG (8 bits): Offset of the register that is used to calculate the 1436 * address for load/store when accessing the arena region. 1437 * - ARENA_ACCESS (1 bit): This bit is set when the faulting instruction accessed the arena region. 1438 * 1439 * Bit layout of `data` (32-bit): 1440 * 1441 * +--------------+--------+--------------+ 1442 * | 31-16 | 15-8 | 7-0 | 1443 * | | | | 1444 * | ARENA_OFFSET | Unused | EX_TYPE_BPF | 1445 * +--------------+--------+--------------+ 1446 * 1447 * - ARENA_OFFSET (16 bits): Offset used to calculate the address for load/store when 1448 * accessing the arena region. 1449 */ 1450 1451 #define DONT_CLEAR 1 1452 #define FIXUP_INSN_LEN_MASK GENMASK(7, 0) 1453 #define FIXUP_REG_MASK GENMASK(15, 8) 1454 #define FIXUP_ARENA_REG_MASK GENMASK(23, 16) 1455 #define FIXUP_ARENA_ACCESS BIT(31) 1456 #define DATA_ARENA_OFFSET_MASK GENMASK(31, 16) 1457 1458 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs) 1459 { 1460 u32 reg = FIELD_GET(FIXUP_REG_MASK, x->fixup); 1461 u32 insn_len = FIELD_GET(FIXUP_INSN_LEN_MASK, x->fixup); 1462 bool is_arena = !!(x->fixup & FIXUP_ARENA_ACCESS); 1463 bool is_write = (reg == DONT_CLEAR); 1464 unsigned long addr; 1465 s16 off; 1466 u32 arena_reg; 1467 1468 if (is_arena) { 1469 arena_reg = FIELD_GET(FIXUP_ARENA_REG_MASK, x->fixup); 1470 off = FIELD_GET(DATA_ARENA_OFFSET_MASK, x->data); 1471 addr = *(unsigned long *)((void *)regs + arena_reg) + off; 1472 bpf_prog_report_arena_violation(is_write, addr, regs->ip); 1473 } 1474 1475 /* jump over faulting load and clear dest register */ 1476 if (reg != DONT_CLEAR) 1477 *(unsigned long *)((void *)regs + reg) = 0; 1478 regs->ip += insn_len; 1479 1480 return true; 1481 } 1482 1483 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt, 1484 bool *regs_used) 1485 { 1486 int i; 1487 1488 for (i = 1; i <= insn_cnt; i++, insn++) { 1489 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6) 1490 regs_used[0] = true; 1491 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7) 1492 regs_used[1] = true; 1493 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8) 1494 regs_used[2] = true; 1495 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9) 1496 regs_used[3] = true; 1497 } 1498 } 1499 1500 /* emit the 3-byte VEX prefix 1501 * 1502 * r: same as rex.r, extra bit for ModRM reg field 1503 * x: same as rex.x, extra bit for SIB index field 1504 * b: same as rex.b, extra bit for ModRM r/m, or SIB base 1505 * m: opcode map select, encoding escape bytes e.g. 0x0f38 1506 * w: same as rex.w (32 bit or 64 bit) or opcode specific 1507 * src_reg2: additional source reg (encoded as BPF reg) 1508 * l: vector length (128 bit or 256 bit) or reserved 1509 * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3) 1510 */ 1511 static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m, 1512 bool w, u8 src_reg2, bool l, u8 pp) 1513 { 1514 u8 *prog = *pprog; 1515 const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */ 1516 u8 b1, b2; 1517 u8 vvvv = reg2hex[src_reg2]; 1518 1519 /* reg2hex gives only the lower 3 bit of vvvv */ 1520 if (is_ereg(src_reg2)) 1521 vvvv |= 1 << 3; 1522 1523 /* 1524 * 2nd byte of 3-byte VEX prefix 1525 * ~ means bit inverted encoding 1526 * 1527 * 7 0 1528 * +---+---+---+---+---+---+---+---+ 1529 * |~R |~X |~B | m | 1530 * +---+---+---+---+---+---+---+---+ 1531 */ 1532 b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f); 1533 /* 1534 * 3rd byte of 3-byte VEX prefix 1535 * 1536 * 7 0 1537 * +---+---+---+---+---+---+---+---+ 1538 * | W | ~vvvv | L | pp | 1539 * +---+---+---+---+---+---+---+---+ 1540 */ 1541 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3); 1542 1543 EMIT3(b0, b1, b2); 1544 *pprog = prog; 1545 } 1546 1547 /* emit BMI2 shift instruction */ 1548 static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op) 1549 { 1550 u8 *prog = *pprog; 1551 bool r = is_ereg(dst_reg); 1552 u8 m = 2; /* escape code 0f38 */ 1553 1554 emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op); 1555 EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg)); 1556 *pprog = prog; 1557 } 1558 1559 static void emit_priv_frame_ptr(u8 **pprog, void __percpu *priv_frame_ptr) 1560 { 1561 u8 *prog = *pprog; 1562 1563 /* movabs r9, priv_frame_ptr */ 1564 emit_mov_imm64(&prog, X86_REG_R9, (__force long) priv_frame_ptr >> 32, 1565 (u32) (__force long) priv_frame_ptr); 1566 1567 #ifdef CONFIG_SMP 1568 /* add <r9>, gs:[<off>] */ 1569 EMIT2(0x65, 0x4c); 1570 EMIT3(0x03, 0x0c, 0x25); 1571 EMIT((u32)(unsigned long)&this_cpu_off, 4); 1572 #endif 1573 1574 *pprog = prog; 1575 } 1576 1577 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp))) 1578 1579 #define __LOAD_TCC_PTR(off) \ 1580 EMIT3_off32(0x48, 0x8B, 0x85, off) 1581 /* mov rax, qword ptr [rbp - rounded_stack_depth - 16] */ 1582 #define LOAD_TAIL_CALL_CNT_PTR(stack) \ 1583 __LOAD_TCC_PTR(BPF_TAIL_CALL_CNT_PTR_STACK_OFF(stack)) 1584 1585 /* Memory size/value to protect private stack overflow/underflow */ 1586 #define PRIV_STACK_GUARD_SZ 8 1587 #define PRIV_STACK_GUARD_VAL 0xEB9F12345678eb9fULL 1588 1589 static int emit_spectre_bhb_barrier(u8 **pprog, u8 *ip, 1590 struct bpf_prog *bpf_prog) 1591 { 1592 u8 *prog = *pprog; 1593 u8 *func; 1594 1595 if (cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_LOOP)) { 1596 /* The clearing sequence clobbers eax and ecx. */ 1597 EMIT1(0x50); /* push rax */ 1598 EMIT1(0x51); /* push rcx */ 1599 ip += 2; 1600 1601 func = (u8 *)clear_bhb_loop; 1602 ip += x86_call_depth_emit_accounting(&prog, func, ip); 1603 1604 if (emit_call(&prog, func, ip)) 1605 return -EINVAL; 1606 EMIT1(0x59); /* pop rcx */ 1607 EMIT1(0x58); /* pop rax */ 1608 } 1609 /* Insert IBHF instruction */ 1610 if ((cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_LOOP) && 1611 cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) || 1612 cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_HW)) { 1613 /* 1614 * Add an Indirect Branch History Fence (IBHF). IBHF acts as a 1615 * fence preventing branch history from before the fence from 1616 * affecting indirect branches after the fence. This is 1617 * specifically used in cBPF jitted code to prevent Intra-mode 1618 * BHI attacks. The IBHF instruction is designed to be a NOP on 1619 * hardware that doesn't need or support it. The REP and REX.W 1620 * prefixes are required by the microcode, and they also ensure 1621 * that the NOP is unlikely to be used in existing code. 1622 * 1623 * IBHF is not a valid instruction in 32-bit mode. 1624 */ 1625 EMIT5(0xF3, 0x48, 0x0F, 0x1E, 0xF8); /* ibhf */ 1626 } 1627 *pprog = prog; 1628 return 0; 1629 } 1630 1631 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image, 1632 int oldproglen, struct jit_context *ctx, bool jmp_padding) 1633 { 1634 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable; 1635 struct bpf_insn *insn = bpf_prog->insnsi; 1636 bool callee_regs_used[4] = {}; 1637 int insn_cnt = bpf_prog->len; 1638 bool seen_exit = false; 1639 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY]; 1640 void __percpu *priv_frame_ptr = NULL; 1641 u64 arena_vm_start, user_vm_start; 1642 void __percpu *priv_stack_ptr; 1643 int i, excnt = 0; 1644 int ilen, proglen = 0; 1645 u8 *prog = temp; 1646 u32 stack_depth; 1647 int err; 1648 1649 stack_depth = bpf_prog->aux->stack_depth; 1650 priv_stack_ptr = bpf_prog->aux->priv_stack_ptr; 1651 if (priv_stack_ptr) { 1652 priv_frame_ptr = priv_stack_ptr + PRIV_STACK_GUARD_SZ + round_up(stack_depth, 8); 1653 stack_depth = 0; 1654 } 1655 1656 arena_vm_start = bpf_arena_get_kern_vm_start(bpf_prog->aux->arena); 1657 user_vm_start = bpf_arena_get_user_vm_start(bpf_prog->aux->arena); 1658 1659 detect_reg_usage(insn, insn_cnt, callee_regs_used); 1660 1661 emit_prologue(&prog, image, stack_depth, 1662 bpf_prog_was_classic(bpf_prog), tail_call_reachable, 1663 bpf_is_subprog(bpf_prog), bpf_prog->aux->exception_cb); 1664 /* Exception callback will clobber callee regs for its own use, and 1665 * restore the original callee regs from main prog's stack frame. 1666 */ 1667 if (bpf_prog->aux->exception_boundary) { 1668 /* We also need to save r12, which is not mapped to any BPF 1669 * register, as we throw after entry into the kernel, which may 1670 * overwrite r12. 1671 */ 1672 push_r12(&prog); 1673 push_callee_regs(&prog, all_callee_regs_used); 1674 } else { 1675 if (arena_vm_start) 1676 push_r12(&prog); 1677 push_callee_regs(&prog, callee_regs_used); 1678 } 1679 if (arena_vm_start) 1680 emit_mov_imm64(&prog, X86_REG_R12, 1681 arena_vm_start >> 32, (u32) arena_vm_start); 1682 1683 if (priv_frame_ptr) 1684 emit_priv_frame_ptr(&prog, priv_frame_ptr); 1685 1686 ilen = prog - temp; 1687 if (rw_image) 1688 memcpy(rw_image + proglen, temp, ilen); 1689 proglen += ilen; 1690 addrs[0] = proglen; 1691 prog = temp; 1692 1693 for (i = 1; i <= insn_cnt; i++, insn++) { 1694 const s32 imm32 = insn->imm; 1695 u32 dst_reg = insn->dst_reg; 1696 u32 src_reg = insn->src_reg; 1697 u8 b2 = 0, b3 = 0; 1698 u8 *start_of_ldx; 1699 s64 jmp_offset; 1700 s16 insn_off; 1701 u8 jmp_cond; 1702 u8 *func; 1703 int nops; 1704 1705 if (priv_frame_ptr) { 1706 if (src_reg == BPF_REG_FP) 1707 src_reg = X86_REG_R9; 1708 1709 if (dst_reg == BPF_REG_FP) 1710 dst_reg = X86_REG_R9; 1711 } 1712 1713 switch (insn->code) { 1714 /* ALU */ 1715 case BPF_ALU | BPF_ADD | BPF_X: 1716 case BPF_ALU | BPF_SUB | BPF_X: 1717 case BPF_ALU | BPF_AND | BPF_X: 1718 case BPF_ALU | BPF_OR | BPF_X: 1719 case BPF_ALU | BPF_XOR | BPF_X: 1720 case BPF_ALU64 | BPF_ADD | BPF_X: 1721 case BPF_ALU64 | BPF_SUB | BPF_X: 1722 case BPF_ALU64 | BPF_AND | BPF_X: 1723 case BPF_ALU64 | BPF_OR | BPF_X: 1724 case BPF_ALU64 | BPF_XOR | BPF_X: 1725 maybe_emit_mod(&prog, dst_reg, src_reg, 1726 BPF_CLASS(insn->code) == BPF_ALU64); 1727 b2 = simple_alu_opcodes[BPF_OP(insn->code)]; 1728 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg)); 1729 break; 1730 1731 case BPF_ALU64 | BPF_MOV | BPF_X: 1732 if (insn_is_cast_user(insn)) { 1733 if (dst_reg != src_reg) 1734 /* 32-bit mov */ 1735 emit_mov_reg(&prog, false, dst_reg, src_reg); 1736 /* shl dst_reg, 32 */ 1737 maybe_emit_1mod(&prog, dst_reg, true); 1738 EMIT3(0xC1, add_1reg(0xE0, dst_reg), 32); 1739 1740 /* or dst_reg, user_vm_start */ 1741 maybe_emit_1mod(&prog, dst_reg, true); 1742 if (is_axreg(dst_reg)) 1743 EMIT1_off32(0x0D, user_vm_start >> 32); 1744 else 1745 EMIT2_off32(0x81, add_1reg(0xC8, dst_reg), user_vm_start >> 32); 1746 1747 /* rol dst_reg, 32 */ 1748 maybe_emit_1mod(&prog, dst_reg, true); 1749 EMIT3(0xC1, add_1reg(0xC0, dst_reg), 32); 1750 1751 /* xor r11, r11 */ 1752 EMIT3(0x4D, 0x31, 0xDB); 1753 1754 /* test dst_reg32, dst_reg32; check if lower 32-bit are zero */ 1755 maybe_emit_mod(&prog, dst_reg, dst_reg, false); 1756 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 1757 1758 /* cmove r11, dst_reg; if so, set dst_reg to zero */ 1759 /* WARNING: Intel swapped src/dst register encoding in CMOVcc !!! */ 1760 maybe_emit_mod(&prog, AUX_REG, dst_reg, true); 1761 EMIT3(0x0F, 0x44, add_2reg(0xC0, AUX_REG, dst_reg)); 1762 break; 1763 } else if (insn_is_mov_percpu_addr(insn)) { 1764 /* mov <dst>, <src> (if necessary) */ 1765 EMIT_mov(dst_reg, src_reg); 1766 #ifdef CONFIG_SMP 1767 /* add <dst>, gs:[<off>] */ 1768 EMIT2(0x65, add_1mod(0x48, dst_reg)); 1769 EMIT3(0x03, add_2reg(0x04, 0, dst_reg), 0x25); 1770 EMIT((u32)(unsigned long)&this_cpu_off, 4); 1771 #endif 1772 break; 1773 } 1774 fallthrough; 1775 case BPF_ALU | BPF_MOV | BPF_X: 1776 if (insn->off == 0) 1777 emit_mov_reg(&prog, 1778 BPF_CLASS(insn->code) == BPF_ALU64, 1779 dst_reg, src_reg); 1780 else 1781 emit_movsx_reg(&prog, insn->off, 1782 BPF_CLASS(insn->code) == BPF_ALU64, 1783 dst_reg, src_reg); 1784 break; 1785 1786 /* neg dst */ 1787 case BPF_ALU | BPF_NEG: 1788 case BPF_ALU64 | BPF_NEG: 1789 maybe_emit_1mod(&prog, dst_reg, 1790 BPF_CLASS(insn->code) == BPF_ALU64); 1791 EMIT2(0xF7, add_1reg(0xD8, dst_reg)); 1792 break; 1793 1794 case BPF_ALU | BPF_ADD | BPF_K: 1795 case BPF_ALU | BPF_SUB | BPF_K: 1796 case BPF_ALU | BPF_AND | BPF_K: 1797 case BPF_ALU | BPF_OR | BPF_K: 1798 case BPF_ALU | BPF_XOR | BPF_K: 1799 case BPF_ALU64 | BPF_ADD | BPF_K: 1800 case BPF_ALU64 | BPF_SUB | BPF_K: 1801 case BPF_ALU64 | BPF_AND | BPF_K: 1802 case BPF_ALU64 | BPF_OR | BPF_K: 1803 case BPF_ALU64 | BPF_XOR | BPF_K: 1804 maybe_emit_1mod(&prog, dst_reg, 1805 BPF_CLASS(insn->code) == BPF_ALU64); 1806 1807 /* 1808 * b3 holds 'normal' opcode, b2 short form only valid 1809 * in case dst is eax/rax. 1810 */ 1811 switch (BPF_OP(insn->code)) { 1812 case BPF_ADD: 1813 b3 = 0xC0; 1814 b2 = 0x05; 1815 break; 1816 case BPF_SUB: 1817 b3 = 0xE8; 1818 b2 = 0x2D; 1819 break; 1820 case BPF_AND: 1821 b3 = 0xE0; 1822 b2 = 0x25; 1823 break; 1824 case BPF_OR: 1825 b3 = 0xC8; 1826 b2 = 0x0D; 1827 break; 1828 case BPF_XOR: 1829 b3 = 0xF0; 1830 b2 = 0x35; 1831 break; 1832 } 1833 1834 if (is_imm8(imm32)) 1835 EMIT3(0x83, add_1reg(b3, dst_reg), imm32); 1836 else if (is_axreg(dst_reg)) 1837 EMIT1_off32(b2, imm32); 1838 else 1839 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32); 1840 break; 1841 1842 case BPF_ALU64 | BPF_MOV | BPF_K: 1843 case BPF_ALU | BPF_MOV | BPF_K: 1844 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64, 1845 dst_reg, imm32); 1846 break; 1847 1848 case BPF_LD | BPF_IMM | BPF_DW: 1849 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm); 1850 insn++; 1851 i++; 1852 break; 1853 1854 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */ 1855 case BPF_ALU | BPF_MOD | BPF_X: 1856 case BPF_ALU | BPF_DIV | BPF_X: 1857 case BPF_ALU | BPF_MOD | BPF_K: 1858 case BPF_ALU | BPF_DIV | BPF_K: 1859 case BPF_ALU64 | BPF_MOD | BPF_X: 1860 case BPF_ALU64 | BPF_DIV | BPF_X: 1861 case BPF_ALU64 | BPF_MOD | BPF_K: 1862 case BPF_ALU64 | BPF_DIV | BPF_K: { 1863 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64; 1864 1865 if (dst_reg != BPF_REG_0) 1866 EMIT1(0x50); /* push rax */ 1867 if (dst_reg != BPF_REG_3) 1868 EMIT1(0x52); /* push rdx */ 1869 1870 if (BPF_SRC(insn->code) == BPF_X) { 1871 if (src_reg == BPF_REG_0 || 1872 src_reg == BPF_REG_3) { 1873 /* mov r11, src_reg */ 1874 EMIT_mov(AUX_REG, src_reg); 1875 src_reg = AUX_REG; 1876 } 1877 } else { 1878 /* mov r11, imm32 */ 1879 EMIT3_off32(0x49, 0xC7, 0xC3, imm32); 1880 src_reg = AUX_REG; 1881 } 1882 1883 if (dst_reg != BPF_REG_0) 1884 /* mov rax, dst_reg */ 1885 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg); 1886 1887 if (insn->off == 0) { 1888 /* 1889 * xor edx, edx 1890 * equivalent to 'xor rdx, rdx', but one byte less 1891 */ 1892 EMIT2(0x31, 0xd2); 1893 1894 /* div src_reg */ 1895 maybe_emit_1mod(&prog, src_reg, is64); 1896 EMIT2(0xF7, add_1reg(0xF0, src_reg)); 1897 } else { 1898 if (BPF_CLASS(insn->code) == BPF_ALU) 1899 EMIT1(0x99); /* cdq */ 1900 else 1901 EMIT2(0x48, 0x99); /* cqo */ 1902 1903 /* idiv src_reg */ 1904 maybe_emit_1mod(&prog, src_reg, is64); 1905 EMIT2(0xF7, add_1reg(0xF8, src_reg)); 1906 } 1907 1908 if (BPF_OP(insn->code) == BPF_MOD && 1909 dst_reg != BPF_REG_3) 1910 /* mov dst_reg, rdx */ 1911 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3); 1912 else if (BPF_OP(insn->code) == BPF_DIV && 1913 dst_reg != BPF_REG_0) 1914 /* mov dst_reg, rax */ 1915 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0); 1916 1917 if (dst_reg != BPF_REG_3) 1918 EMIT1(0x5A); /* pop rdx */ 1919 if (dst_reg != BPF_REG_0) 1920 EMIT1(0x58); /* pop rax */ 1921 break; 1922 } 1923 1924 case BPF_ALU | BPF_MUL | BPF_K: 1925 case BPF_ALU64 | BPF_MUL | BPF_K: 1926 maybe_emit_mod(&prog, dst_reg, dst_reg, 1927 BPF_CLASS(insn->code) == BPF_ALU64); 1928 1929 if (is_imm8(imm32)) 1930 /* imul dst_reg, dst_reg, imm8 */ 1931 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg), 1932 imm32); 1933 else 1934 /* imul dst_reg, dst_reg, imm32 */ 1935 EMIT2_off32(0x69, 1936 add_2reg(0xC0, dst_reg, dst_reg), 1937 imm32); 1938 break; 1939 1940 case BPF_ALU | BPF_MUL | BPF_X: 1941 case BPF_ALU64 | BPF_MUL | BPF_X: 1942 maybe_emit_mod(&prog, src_reg, dst_reg, 1943 BPF_CLASS(insn->code) == BPF_ALU64); 1944 1945 /* imul dst_reg, src_reg */ 1946 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg)); 1947 break; 1948 1949 /* Shifts */ 1950 case BPF_ALU | BPF_LSH | BPF_K: 1951 case BPF_ALU | BPF_RSH | BPF_K: 1952 case BPF_ALU | BPF_ARSH | BPF_K: 1953 case BPF_ALU64 | BPF_LSH | BPF_K: 1954 case BPF_ALU64 | BPF_RSH | BPF_K: 1955 case BPF_ALU64 | BPF_ARSH | BPF_K: 1956 maybe_emit_1mod(&prog, dst_reg, 1957 BPF_CLASS(insn->code) == BPF_ALU64); 1958 1959 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 1960 if (imm32 == 1) 1961 EMIT2(0xD1, add_1reg(b3, dst_reg)); 1962 else 1963 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32); 1964 break; 1965 1966 case BPF_ALU | BPF_LSH | BPF_X: 1967 case BPF_ALU | BPF_RSH | BPF_X: 1968 case BPF_ALU | BPF_ARSH | BPF_X: 1969 case BPF_ALU64 | BPF_LSH | BPF_X: 1970 case BPF_ALU64 | BPF_RSH | BPF_X: 1971 case BPF_ALU64 | BPF_ARSH | BPF_X: 1972 /* BMI2 shifts aren't better when shift count is already in rcx */ 1973 if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) { 1974 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */ 1975 bool w = (BPF_CLASS(insn->code) == BPF_ALU64); 1976 u8 op; 1977 1978 switch (BPF_OP(insn->code)) { 1979 case BPF_LSH: 1980 op = 1; /* prefix 0x66 */ 1981 break; 1982 case BPF_RSH: 1983 op = 3; /* prefix 0xf2 */ 1984 break; 1985 case BPF_ARSH: 1986 op = 2; /* prefix 0xf3 */ 1987 break; 1988 } 1989 1990 emit_shiftx(&prog, dst_reg, src_reg, w, op); 1991 1992 break; 1993 } 1994 1995 if (src_reg != BPF_REG_4) { /* common case */ 1996 /* Check for bad case when dst_reg == rcx */ 1997 if (dst_reg == BPF_REG_4) { 1998 /* mov r11, dst_reg */ 1999 EMIT_mov(AUX_REG, dst_reg); 2000 dst_reg = AUX_REG; 2001 } else { 2002 EMIT1(0x51); /* push rcx */ 2003 } 2004 /* mov rcx, src_reg */ 2005 EMIT_mov(BPF_REG_4, src_reg); 2006 } 2007 2008 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */ 2009 maybe_emit_1mod(&prog, dst_reg, 2010 BPF_CLASS(insn->code) == BPF_ALU64); 2011 2012 b3 = simple_alu_opcodes[BPF_OP(insn->code)]; 2013 EMIT2(0xD3, add_1reg(b3, dst_reg)); 2014 2015 if (src_reg != BPF_REG_4) { 2016 if (insn->dst_reg == BPF_REG_4) 2017 /* mov dst_reg, r11 */ 2018 EMIT_mov(insn->dst_reg, AUX_REG); 2019 else 2020 EMIT1(0x59); /* pop rcx */ 2021 } 2022 2023 break; 2024 2025 case BPF_ALU | BPF_END | BPF_FROM_BE: 2026 case BPF_ALU64 | BPF_END | BPF_FROM_LE: 2027 switch (imm32) { 2028 case 16: 2029 /* Emit 'ror %ax, 8' to swap lower 2 bytes */ 2030 EMIT1(0x66); 2031 if (is_ereg(dst_reg)) 2032 EMIT1(0x41); 2033 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8); 2034 2035 /* Emit 'movzwl eax, ax' */ 2036 if (is_ereg(dst_reg)) 2037 EMIT3(0x45, 0x0F, 0xB7); 2038 else 2039 EMIT2(0x0F, 0xB7); 2040 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 2041 break; 2042 case 32: 2043 /* Emit 'bswap eax' to swap lower 4 bytes */ 2044 if (is_ereg(dst_reg)) 2045 EMIT2(0x41, 0x0F); 2046 else 2047 EMIT1(0x0F); 2048 EMIT1(add_1reg(0xC8, dst_reg)); 2049 break; 2050 case 64: 2051 /* Emit 'bswap rax' to swap 8 bytes */ 2052 EMIT3(add_1mod(0x48, dst_reg), 0x0F, 2053 add_1reg(0xC8, dst_reg)); 2054 break; 2055 } 2056 break; 2057 2058 case BPF_ALU | BPF_END | BPF_FROM_LE: 2059 switch (imm32) { 2060 case 16: 2061 /* 2062 * Emit 'movzwl eax, ax' to zero extend 16-bit 2063 * into 64 bit 2064 */ 2065 if (is_ereg(dst_reg)) 2066 EMIT3(0x45, 0x0F, 0xB7); 2067 else 2068 EMIT2(0x0F, 0xB7); 2069 EMIT1(add_2reg(0xC0, dst_reg, dst_reg)); 2070 break; 2071 case 32: 2072 /* Emit 'mov eax, eax' to clear upper 32-bits */ 2073 if (is_ereg(dst_reg)) 2074 EMIT1(0x45); 2075 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg)); 2076 break; 2077 case 64: 2078 /* nop */ 2079 break; 2080 } 2081 break; 2082 2083 /* speculation barrier */ 2084 case BPF_ST | BPF_NOSPEC: 2085 EMIT_LFENCE(); 2086 break; 2087 2088 /* ST: *(u8*)(dst_reg + off) = imm */ 2089 case BPF_ST | BPF_MEM | BPF_B: 2090 if (is_ereg(dst_reg)) 2091 EMIT2(0x41, 0xC6); 2092 else 2093 EMIT1(0xC6); 2094 goto st; 2095 case BPF_ST | BPF_MEM | BPF_H: 2096 if (is_ereg(dst_reg)) 2097 EMIT3(0x66, 0x41, 0xC7); 2098 else 2099 EMIT2(0x66, 0xC7); 2100 goto st; 2101 case BPF_ST | BPF_MEM | BPF_W: 2102 if (is_ereg(dst_reg)) 2103 EMIT2(0x41, 0xC7); 2104 else 2105 EMIT1(0xC7); 2106 goto st; 2107 case BPF_ST | BPF_MEM | BPF_DW: 2108 EMIT2(add_1mod(0x48, dst_reg), 0xC7); 2109 2110 st: if (is_imm8(insn->off)) 2111 EMIT2(add_1reg(0x40, dst_reg), insn->off); 2112 else 2113 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off); 2114 2115 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code))); 2116 break; 2117 2118 /* STX: *(u8*)(dst_reg + off) = src_reg */ 2119 case BPF_STX | BPF_MEM | BPF_B: 2120 case BPF_STX | BPF_MEM | BPF_H: 2121 case BPF_STX | BPF_MEM | BPF_W: 2122 case BPF_STX | BPF_MEM | BPF_DW: 2123 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2124 break; 2125 2126 case BPF_ST | BPF_PROBE_MEM32 | BPF_B: 2127 case BPF_ST | BPF_PROBE_MEM32 | BPF_H: 2128 case BPF_ST | BPF_PROBE_MEM32 | BPF_W: 2129 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW: 2130 start_of_ldx = prog; 2131 emit_st_r12(&prog, BPF_SIZE(insn->code), dst_reg, insn->off, insn->imm); 2132 goto populate_extable; 2133 2134 /* LDX: dst_reg = *(u8*)(src_reg + r12 + off) */ 2135 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B: 2136 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H: 2137 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W: 2138 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW: 2139 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_B: 2140 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_H: 2141 case BPF_LDX | BPF_PROBE_MEM32SX | BPF_W: 2142 case BPF_STX | BPF_PROBE_MEM32 | BPF_B: 2143 case BPF_STX | BPF_PROBE_MEM32 | BPF_H: 2144 case BPF_STX | BPF_PROBE_MEM32 | BPF_W: 2145 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW: 2146 start_of_ldx = prog; 2147 if (BPF_CLASS(insn->code) == BPF_LDX) { 2148 if (BPF_MODE(insn->code) == BPF_PROBE_MEM32SX) 2149 emit_ldsx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2150 else 2151 emit_ldx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2152 } else { 2153 emit_stx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off); 2154 } 2155 populate_extable: 2156 { 2157 struct exception_table_entry *ex; 2158 u8 *_insn = image + proglen + (start_of_ldx - temp); 2159 u32 arena_reg, fixup_reg; 2160 s64 delta; 2161 2162 if (!bpf_prog->aux->extable) 2163 break; 2164 2165 if (excnt >= bpf_prog->aux->num_exentries) { 2166 pr_err("mem32 extable bug\n"); 2167 return -EFAULT; 2168 } 2169 ex = &bpf_prog->aux->extable[excnt++]; 2170 2171 delta = _insn - (u8 *)&ex->insn; 2172 /* switch ex to rw buffer for writes */ 2173 ex = (void *)rw_image + ((void *)ex - (void *)image); 2174 2175 ex->insn = delta; 2176 2177 ex->data = EX_TYPE_BPF; 2178 2179 /* 2180 * src_reg/dst_reg holds the address in the arena region with upper 2181 * 32-bits being zero because of a preceding addr_space_cast(r<n>, 2182 * 0x0, 0x1) instruction. This address is adjusted with the addition 2183 * of arena_vm_start (see the implementation of BPF_PROBE_MEM32 and 2184 * BPF_PROBE_ATOMIC) before being used for the memory access. Pass 2185 * the reg holding the unmodified 32-bit address to 2186 * ex_handler_bpf(). 2187 */ 2188 if (BPF_CLASS(insn->code) == BPF_LDX) { 2189 arena_reg = reg2pt_regs[src_reg]; 2190 fixup_reg = reg2pt_regs[dst_reg]; 2191 } else { 2192 arena_reg = reg2pt_regs[dst_reg]; 2193 fixup_reg = DONT_CLEAR; 2194 } 2195 2196 ex->fixup = FIELD_PREP(FIXUP_INSN_LEN_MASK, prog - start_of_ldx) | 2197 FIELD_PREP(FIXUP_ARENA_REG_MASK, arena_reg) | 2198 FIELD_PREP(FIXUP_REG_MASK, fixup_reg); 2199 ex->fixup |= FIXUP_ARENA_ACCESS; 2200 2201 ex->data |= FIELD_PREP(DATA_ARENA_OFFSET_MASK, insn->off); 2202 } 2203 break; 2204 2205 /* LDX: dst_reg = *(u8*)(src_reg + off) */ 2206 case BPF_LDX | BPF_MEM | BPF_B: 2207 case BPF_LDX | BPF_PROBE_MEM | BPF_B: 2208 case BPF_LDX | BPF_MEM | BPF_H: 2209 case BPF_LDX | BPF_PROBE_MEM | BPF_H: 2210 case BPF_LDX | BPF_MEM | BPF_W: 2211 case BPF_LDX | BPF_PROBE_MEM | BPF_W: 2212 case BPF_LDX | BPF_MEM | BPF_DW: 2213 case BPF_LDX | BPF_PROBE_MEM | BPF_DW: 2214 /* LDXS: dst_reg = *(s8*)(src_reg + off) */ 2215 case BPF_LDX | BPF_MEMSX | BPF_B: 2216 case BPF_LDX | BPF_MEMSX | BPF_H: 2217 case BPF_LDX | BPF_MEMSX | BPF_W: 2218 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B: 2219 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H: 2220 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W: 2221 insn_off = insn->off; 2222 2223 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 2224 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 2225 /* Conservatively check that src_reg + insn->off is a kernel address: 2226 * src_reg + insn->off > TASK_SIZE_MAX + PAGE_SIZE 2227 * and 2228 * src_reg + insn->off < VSYSCALL_ADDR 2229 */ 2230 2231 u64 limit = TASK_SIZE_MAX + PAGE_SIZE - VSYSCALL_ADDR; 2232 u8 *end_of_jmp; 2233 2234 /* movabsq r10, VSYSCALL_ADDR */ 2235 emit_mov_imm64(&prog, BPF_REG_AX, (long)VSYSCALL_ADDR >> 32, 2236 (u32)(long)VSYSCALL_ADDR); 2237 2238 /* mov src_reg, r11 */ 2239 EMIT_mov(AUX_REG, src_reg); 2240 2241 if (insn->off) { 2242 /* add r11, insn->off */ 2243 maybe_emit_1mod(&prog, AUX_REG, true); 2244 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off); 2245 } 2246 2247 /* sub r11, r10 */ 2248 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true); 2249 EMIT2(0x29, add_2reg(0xC0, AUX_REG, BPF_REG_AX)); 2250 2251 /* movabsq r10, limit */ 2252 emit_mov_imm64(&prog, BPF_REG_AX, (long)limit >> 32, 2253 (u32)(long)limit); 2254 2255 /* cmp r10, r11 */ 2256 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true); 2257 EMIT2(0x39, add_2reg(0xC0, AUX_REG, BPF_REG_AX)); 2258 2259 /* if unsigned '>', goto load */ 2260 EMIT2(X86_JA, 0); 2261 end_of_jmp = prog; 2262 2263 /* xor dst_reg, dst_reg */ 2264 emit_mov_imm32(&prog, false, dst_reg, 0); 2265 /* jmp byte_after_ldx */ 2266 EMIT2(0xEB, 0); 2267 2268 /* populate jmp_offset for JAE above to jump to start_of_ldx */ 2269 start_of_ldx = prog; 2270 end_of_jmp[-1] = start_of_ldx - end_of_jmp; 2271 } 2272 if (BPF_MODE(insn->code) == BPF_PROBE_MEMSX || 2273 BPF_MODE(insn->code) == BPF_MEMSX) 2274 emit_ldsx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 2275 else 2276 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off); 2277 if (BPF_MODE(insn->code) == BPF_PROBE_MEM || 2278 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) { 2279 struct exception_table_entry *ex; 2280 u8 *_insn = image + proglen + (start_of_ldx - temp); 2281 s64 delta; 2282 2283 /* populate jmp_offset for JMP above */ 2284 start_of_ldx[-1] = prog - start_of_ldx; 2285 2286 if (!bpf_prog->aux->extable) 2287 break; 2288 2289 if (excnt >= bpf_prog->aux->num_exentries) { 2290 pr_err("ex gen bug\n"); 2291 return -EFAULT; 2292 } 2293 ex = &bpf_prog->aux->extable[excnt++]; 2294 2295 delta = _insn - (u8 *)&ex->insn; 2296 if (!is_simm32(delta)) { 2297 pr_err("extable->insn doesn't fit into 32-bit\n"); 2298 return -EFAULT; 2299 } 2300 /* switch ex to rw buffer for writes */ 2301 ex = (void *)rw_image + ((void *)ex - (void *)image); 2302 2303 ex->insn = delta; 2304 2305 ex->data = EX_TYPE_BPF; 2306 2307 if (dst_reg > BPF_REG_9) { 2308 pr_err("verifier error\n"); 2309 return -EFAULT; 2310 } 2311 /* 2312 * Compute size of x86 insn and its target dest x86 register. 2313 * ex_handler_bpf() will use lower 8 bits to adjust 2314 * pt_regs->ip to jump over this x86 instruction 2315 * and upper bits to figure out which pt_regs to zero out. 2316 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]" 2317 * of 4 bytes will be ignored and rbx will be zero inited. 2318 */ 2319 ex->fixup = FIELD_PREP(FIXUP_INSN_LEN_MASK, prog - start_of_ldx) | 2320 FIELD_PREP(FIXUP_REG_MASK, reg2pt_regs[dst_reg]); 2321 } 2322 break; 2323 2324 case BPF_STX | BPF_ATOMIC | BPF_B: 2325 case BPF_STX | BPF_ATOMIC | BPF_H: 2326 if (!bpf_atomic_is_load_store(insn)) { 2327 pr_err("bpf_jit: 1- and 2-byte RMW atomics are not supported\n"); 2328 return -EFAULT; 2329 } 2330 fallthrough; 2331 case BPF_STX | BPF_ATOMIC | BPF_W: 2332 case BPF_STX | BPF_ATOMIC | BPF_DW: 2333 if (insn->imm == (BPF_AND | BPF_FETCH) || 2334 insn->imm == (BPF_OR | BPF_FETCH) || 2335 insn->imm == (BPF_XOR | BPF_FETCH)) { 2336 bool is64 = BPF_SIZE(insn->code) == BPF_DW; 2337 u32 real_src_reg = src_reg; 2338 u32 real_dst_reg = dst_reg; 2339 u8 *branch_target; 2340 2341 /* 2342 * Can't be implemented with a single x86 insn. 2343 * Need to do a CMPXCHG loop. 2344 */ 2345 2346 /* Will need RAX as a CMPXCHG operand so save R0 */ 2347 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0); 2348 if (src_reg == BPF_REG_0) 2349 real_src_reg = BPF_REG_AX; 2350 if (dst_reg == BPF_REG_0) 2351 real_dst_reg = BPF_REG_AX; 2352 2353 branch_target = prog; 2354 /* Load old value */ 2355 emit_ldx(&prog, BPF_SIZE(insn->code), 2356 BPF_REG_0, real_dst_reg, insn->off); 2357 /* 2358 * Perform the (commutative) operation locally, 2359 * put the result in the AUX_REG. 2360 */ 2361 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0); 2362 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64); 2363 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)], 2364 add_2reg(0xC0, AUX_REG, real_src_reg)); 2365 /* Attempt to swap in new value */ 2366 err = emit_atomic_rmw(&prog, BPF_CMPXCHG, 2367 real_dst_reg, AUX_REG, 2368 insn->off, 2369 BPF_SIZE(insn->code)); 2370 if (WARN_ON(err)) 2371 return err; 2372 /* 2373 * ZF tells us whether we won the race. If it's 2374 * cleared we need to try again. 2375 */ 2376 EMIT2(X86_JNE, -(prog - branch_target) - 2); 2377 /* Return the pre-modification value */ 2378 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0); 2379 /* Restore R0 after clobbering RAX */ 2380 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX); 2381 break; 2382 } 2383 2384 if (bpf_atomic_is_load_store(insn)) 2385 err = emit_atomic_ld_st(&prog, insn->imm, dst_reg, src_reg, 2386 insn->off, BPF_SIZE(insn->code)); 2387 else 2388 err = emit_atomic_rmw(&prog, insn->imm, dst_reg, src_reg, 2389 insn->off, BPF_SIZE(insn->code)); 2390 if (err) 2391 return err; 2392 break; 2393 2394 case BPF_STX | BPF_PROBE_ATOMIC | BPF_B: 2395 case BPF_STX | BPF_PROBE_ATOMIC | BPF_H: 2396 if (!bpf_atomic_is_load_store(insn)) { 2397 pr_err("bpf_jit: 1- and 2-byte RMW atomics are not supported\n"); 2398 return -EFAULT; 2399 } 2400 fallthrough; 2401 case BPF_STX | BPF_PROBE_ATOMIC | BPF_W: 2402 case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW: 2403 start_of_ldx = prog; 2404 2405 if (bpf_atomic_is_load_store(insn)) 2406 err = emit_atomic_ld_st_index(&prog, insn->imm, 2407 BPF_SIZE(insn->code), dst_reg, 2408 src_reg, X86_REG_R12, insn->off); 2409 else 2410 err = emit_atomic_rmw_index(&prog, insn->imm, BPF_SIZE(insn->code), 2411 dst_reg, src_reg, X86_REG_R12, 2412 insn->off); 2413 if (err) 2414 return err; 2415 goto populate_extable; 2416 2417 /* call */ 2418 case BPF_JMP | BPF_CALL: { 2419 u8 *ip = image + addrs[i - 1]; 2420 2421 func = (u8 *) __bpf_call_base + imm32; 2422 if (src_reg == BPF_PSEUDO_CALL && tail_call_reachable) { 2423 LOAD_TAIL_CALL_CNT_PTR(stack_depth); 2424 ip += 7; 2425 } 2426 if (!imm32) 2427 return -EINVAL; 2428 if (priv_frame_ptr) { 2429 push_r9(&prog); 2430 ip += 2; 2431 } 2432 ip += x86_call_depth_emit_accounting(&prog, func, ip); 2433 if (emit_call(&prog, func, ip)) 2434 return -EINVAL; 2435 if (priv_frame_ptr) 2436 pop_r9(&prog); 2437 break; 2438 } 2439 2440 case BPF_JMP | BPF_TAIL_CALL: 2441 if (imm32) 2442 emit_bpf_tail_call_direct(bpf_prog, 2443 &bpf_prog->aux->poke_tab[imm32 - 1], 2444 &prog, image + addrs[i - 1], 2445 callee_regs_used, 2446 stack_depth, 2447 ctx); 2448 else 2449 emit_bpf_tail_call_indirect(bpf_prog, 2450 &prog, 2451 callee_regs_used, 2452 stack_depth, 2453 image + addrs[i - 1], 2454 ctx); 2455 break; 2456 2457 /* cond jump */ 2458 case BPF_JMP | BPF_JEQ | BPF_X: 2459 case BPF_JMP | BPF_JNE | BPF_X: 2460 case BPF_JMP | BPF_JGT | BPF_X: 2461 case BPF_JMP | BPF_JLT | BPF_X: 2462 case BPF_JMP | BPF_JGE | BPF_X: 2463 case BPF_JMP | BPF_JLE | BPF_X: 2464 case BPF_JMP | BPF_JSGT | BPF_X: 2465 case BPF_JMP | BPF_JSLT | BPF_X: 2466 case BPF_JMP | BPF_JSGE | BPF_X: 2467 case BPF_JMP | BPF_JSLE | BPF_X: 2468 case BPF_JMP32 | BPF_JEQ | BPF_X: 2469 case BPF_JMP32 | BPF_JNE | BPF_X: 2470 case BPF_JMP32 | BPF_JGT | BPF_X: 2471 case BPF_JMP32 | BPF_JLT | BPF_X: 2472 case BPF_JMP32 | BPF_JGE | BPF_X: 2473 case BPF_JMP32 | BPF_JLE | BPF_X: 2474 case BPF_JMP32 | BPF_JSGT | BPF_X: 2475 case BPF_JMP32 | BPF_JSLT | BPF_X: 2476 case BPF_JMP32 | BPF_JSGE | BPF_X: 2477 case BPF_JMP32 | BPF_JSLE | BPF_X: 2478 /* cmp dst_reg, src_reg */ 2479 maybe_emit_mod(&prog, dst_reg, src_reg, 2480 BPF_CLASS(insn->code) == BPF_JMP); 2481 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg)); 2482 goto emit_cond_jmp; 2483 2484 case BPF_JMP | BPF_JSET | BPF_X: 2485 case BPF_JMP32 | BPF_JSET | BPF_X: 2486 /* test dst_reg, src_reg */ 2487 maybe_emit_mod(&prog, dst_reg, src_reg, 2488 BPF_CLASS(insn->code) == BPF_JMP); 2489 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg)); 2490 goto emit_cond_jmp; 2491 2492 case BPF_JMP | BPF_JSET | BPF_K: 2493 case BPF_JMP32 | BPF_JSET | BPF_K: 2494 /* test dst_reg, imm32 */ 2495 maybe_emit_1mod(&prog, dst_reg, 2496 BPF_CLASS(insn->code) == BPF_JMP); 2497 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32); 2498 goto emit_cond_jmp; 2499 2500 case BPF_JMP | BPF_JEQ | BPF_K: 2501 case BPF_JMP | BPF_JNE | BPF_K: 2502 case BPF_JMP | BPF_JGT | BPF_K: 2503 case BPF_JMP | BPF_JLT | BPF_K: 2504 case BPF_JMP | BPF_JGE | BPF_K: 2505 case BPF_JMP | BPF_JLE | BPF_K: 2506 case BPF_JMP | BPF_JSGT | BPF_K: 2507 case BPF_JMP | BPF_JSLT | BPF_K: 2508 case BPF_JMP | BPF_JSGE | BPF_K: 2509 case BPF_JMP | BPF_JSLE | BPF_K: 2510 case BPF_JMP32 | BPF_JEQ | BPF_K: 2511 case BPF_JMP32 | BPF_JNE | BPF_K: 2512 case BPF_JMP32 | BPF_JGT | BPF_K: 2513 case BPF_JMP32 | BPF_JLT | BPF_K: 2514 case BPF_JMP32 | BPF_JGE | BPF_K: 2515 case BPF_JMP32 | BPF_JLE | BPF_K: 2516 case BPF_JMP32 | BPF_JSGT | BPF_K: 2517 case BPF_JMP32 | BPF_JSLT | BPF_K: 2518 case BPF_JMP32 | BPF_JSGE | BPF_K: 2519 case BPF_JMP32 | BPF_JSLE | BPF_K: 2520 /* test dst_reg, dst_reg to save one extra byte */ 2521 if (imm32 == 0) { 2522 maybe_emit_mod(&prog, dst_reg, dst_reg, 2523 BPF_CLASS(insn->code) == BPF_JMP); 2524 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg)); 2525 goto emit_cond_jmp; 2526 } 2527 2528 /* cmp dst_reg, imm8/32 */ 2529 maybe_emit_1mod(&prog, dst_reg, 2530 BPF_CLASS(insn->code) == BPF_JMP); 2531 2532 if (is_imm8(imm32)) 2533 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32); 2534 else 2535 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32); 2536 2537 emit_cond_jmp: /* Convert BPF opcode to x86 */ 2538 switch (BPF_OP(insn->code)) { 2539 case BPF_JEQ: 2540 jmp_cond = X86_JE; 2541 break; 2542 case BPF_JSET: 2543 case BPF_JNE: 2544 jmp_cond = X86_JNE; 2545 break; 2546 case BPF_JGT: 2547 /* GT is unsigned '>', JA in x86 */ 2548 jmp_cond = X86_JA; 2549 break; 2550 case BPF_JLT: 2551 /* LT is unsigned '<', JB in x86 */ 2552 jmp_cond = X86_JB; 2553 break; 2554 case BPF_JGE: 2555 /* GE is unsigned '>=', JAE in x86 */ 2556 jmp_cond = X86_JAE; 2557 break; 2558 case BPF_JLE: 2559 /* LE is unsigned '<=', JBE in x86 */ 2560 jmp_cond = X86_JBE; 2561 break; 2562 case BPF_JSGT: 2563 /* Signed '>', GT in x86 */ 2564 jmp_cond = X86_JG; 2565 break; 2566 case BPF_JSLT: 2567 /* Signed '<', LT in x86 */ 2568 jmp_cond = X86_JL; 2569 break; 2570 case BPF_JSGE: 2571 /* Signed '>=', GE in x86 */ 2572 jmp_cond = X86_JGE; 2573 break; 2574 case BPF_JSLE: 2575 /* Signed '<=', LE in x86 */ 2576 jmp_cond = X86_JLE; 2577 break; 2578 default: /* to silence GCC warning */ 2579 return -EFAULT; 2580 } 2581 jmp_offset = addrs[i + insn->off] - addrs[i]; 2582 if (is_imm8_jmp_offset(jmp_offset)) { 2583 if (jmp_padding) { 2584 /* To keep the jmp_offset valid, the extra bytes are 2585 * padded before the jump insn, so we subtract the 2586 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF. 2587 * 2588 * If the previous pass already emits an imm8 2589 * jmp_cond, then this BPF insn won't shrink, so 2590 * "nops" is 0. 2591 * 2592 * On the other hand, if the previous pass emits an 2593 * imm32 jmp_cond, the extra 4 bytes(*) is padded to 2594 * keep the image from shrinking further. 2595 * 2596 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond 2597 * is 2 bytes, so the size difference is 4 bytes. 2598 */ 2599 nops = INSN_SZ_DIFF - 2; 2600 if (nops != 0 && nops != 4) { 2601 pr_err("unexpected jmp_cond padding: %d bytes\n", 2602 nops); 2603 return -EFAULT; 2604 } 2605 emit_nops(&prog, nops); 2606 } 2607 EMIT2(jmp_cond, jmp_offset); 2608 } else if (is_simm32(jmp_offset)) { 2609 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset); 2610 } else { 2611 pr_err("cond_jmp gen bug %llx\n", jmp_offset); 2612 return -EFAULT; 2613 } 2614 2615 break; 2616 2617 case BPF_JMP | BPF_JA: 2618 case BPF_JMP32 | BPF_JA: 2619 if (BPF_CLASS(insn->code) == BPF_JMP) { 2620 if (insn->off == -1) 2621 /* -1 jmp instructions will always jump 2622 * backwards two bytes. Explicitly handling 2623 * this case avoids wasting too many passes 2624 * when there are long sequences of replaced 2625 * dead code. 2626 */ 2627 jmp_offset = -2; 2628 else 2629 jmp_offset = addrs[i + insn->off] - addrs[i]; 2630 } else { 2631 if (insn->imm == -1) 2632 jmp_offset = -2; 2633 else 2634 jmp_offset = addrs[i + insn->imm] - addrs[i]; 2635 } 2636 2637 if (!jmp_offset) { 2638 /* 2639 * If jmp_padding is enabled, the extra nops will 2640 * be inserted. Otherwise, optimize out nop jumps. 2641 */ 2642 if (jmp_padding) { 2643 /* There are 3 possible conditions. 2644 * (1) This BPF_JA is already optimized out in 2645 * the previous run, so there is no need 2646 * to pad any extra byte (0 byte). 2647 * (2) The previous pass emits an imm8 jmp, 2648 * so we pad 2 bytes to match the previous 2649 * insn size. 2650 * (3) Similarly, the previous pass emits an 2651 * imm32 jmp, and 5 bytes is padded. 2652 */ 2653 nops = INSN_SZ_DIFF; 2654 if (nops != 0 && nops != 2 && nops != 5) { 2655 pr_err("unexpected nop jump padding: %d bytes\n", 2656 nops); 2657 return -EFAULT; 2658 } 2659 emit_nops(&prog, nops); 2660 } 2661 break; 2662 } 2663 emit_jmp: 2664 if (is_imm8_jmp_offset(jmp_offset)) { 2665 if (jmp_padding) { 2666 /* To avoid breaking jmp_offset, the extra bytes 2667 * are padded before the actual jmp insn, so 2668 * 2 bytes is subtracted from INSN_SZ_DIFF. 2669 * 2670 * If the previous pass already emits an imm8 2671 * jmp, there is nothing to pad (0 byte). 2672 * 2673 * If it emits an imm32 jmp (5 bytes) previously 2674 * and now an imm8 jmp (2 bytes), then we pad 2675 * (5 - 2 = 3) bytes to stop the image from 2676 * shrinking further. 2677 */ 2678 nops = INSN_SZ_DIFF - 2; 2679 if (nops != 0 && nops != 3) { 2680 pr_err("unexpected jump padding: %d bytes\n", 2681 nops); 2682 return -EFAULT; 2683 } 2684 emit_nops(&prog, INSN_SZ_DIFF - 2); 2685 } 2686 EMIT2(0xEB, jmp_offset); 2687 } else if (is_simm32(jmp_offset)) { 2688 EMIT1_off32(0xE9, jmp_offset); 2689 } else { 2690 pr_err("jmp gen bug %llx\n", jmp_offset); 2691 return -EFAULT; 2692 } 2693 break; 2694 2695 case BPF_JMP | BPF_EXIT: 2696 if (seen_exit) { 2697 jmp_offset = ctx->cleanup_addr - addrs[i]; 2698 goto emit_jmp; 2699 } 2700 seen_exit = true; 2701 /* Update cleanup_addr */ 2702 ctx->cleanup_addr = proglen; 2703 if (bpf_prog_was_classic(bpf_prog) && 2704 !capable(CAP_SYS_ADMIN)) { 2705 u8 *ip = image + addrs[i - 1]; 2706 2707 if (emit_spectre_bhb_barrier(&prog, ip, bpf_prog)) 2708 return -EINVAL; 2709 } 2710 if (bpf_prog->aux->exception_boundary) { 2711 pop_callee_regs(&prog, all_callee_regs_used); 2712 pop_r12(&prog); 2713 } else { 2714 pop_callee_regs(&prog, callee_regs_used); 2715 if (arena_vm_start) 2716 pop_r12(&prog); 2717 } 2718 EMIT1(0xC9); /* leave */ 2719 emit_return(&prog, image + addrs[i - 1] + (prog - temp)); 2720 break; 2721 2722 default: 2723 /* 2724 * By design x86-64 JIT should support all BPF instructions. 2725 * This error will be seen if new instruction was added 2726 * to the interpreter, but not to the JIT, or if there is 2727 * junk in bpf_prog. 2728 */ 2729 pr_err("bpf_jit: unknown opcode %02x\n", insn->code); 2730 return -EINVAL; 2731 } 2732 2733 ilen = prog - temp; 2734 if (ilen > BPF_MAX_INSN_SIZE) { 2735 pr_err("bpf_jit: fatal insn size error\n"); 2736 return -EFAULT; 2737 } 2738 2739 if (image) { 2740 /* 2741 * When populating the image, assert that: 2742 * 2743 * i) We do not write beyond the allocated space, and 2744 * ii) addrs[i] did not change from the prior run, in order 2745 * to validate assumptions made for computing branch 2746 * displacements. 2747 */ 2748 if (unlikely(proglen + ilen > oldproglen || 2749 proglen + ilen != addrs[i])) { 2750 pr_err("bpf_jit: fatal error\n"); 2751 return -EFAULT; 2752 } 2753 memcpy(rw_image + proglen, temp, ilen); 2754 } 2755 proglen += ilen; 2756 addrs[i] = proglen; 2757 prog = temp; 2758 } 2759 2760 if (image && excnt != bpf_prog->aux->num_exentries) { 2761 pr_err("extable is not populated\n"); 2762 return -EFAULT; 2763 } 2764 return proglen; 2765 } 2766 2767 static void clean_stack_garbage(const struct btf_func_model *m, 2768 u8 **pprog, int nr_stack_slots, 2769 int stack_size) 2770 { 2771 int arg_size, off; 2772 u8 *prog; 2773 2774 /* Generally speaking, the compiler will pass the arguments 2775 * on-stack with "push" instruction, which will take 8-byte 2776 * on the stack. In this case, there won't be garbage values 2777 * while we copy the arguments from origin stack frame to current 2778 * in BPF_DW. 2779 * 2780 * However, sometimes the compiler will only allocate 4-byte on 2781 * the stack for the arguments. For now, this case will only 2782 * happen if there is only one argument on-stack and its size 2783 * not more than 4 byte. In this case, there will be garbage 2784 * values on the upper 4-byte where we store the argument on 2785 * current stack frame. 2786 * 2787 * arguments on origin stack: 2788 * 2789 * stack_arg_1(4-byte) xxx(4-byte) 2790 * 2791 * what we copy: 2792 * 2793 * stack_arg_1(8-byte): stack_arg_1(origin) xxx 2794 * 2795 * and the xxx is the garbage values which we should clean here. 2796 */ 2797 if (nr_stack_slots != 1) 2798 return; 2799 2800 /* the size of the last argument */ 2801 arg_size = m->arg_size[m->nr_args - 1]; 2802 if (arg_size <= 4) { 2803 off = -(stack_size - 4); 2804 prog = *pprog; 2805 /* mov DWORD PTR [rbp + off], 0 */ 2806 if (!is_imm8(off)) 2807 EMIT2_off32(0xC7, 0x85, off); 2808 else 2809 EMIT3(0xC7, 0x45, off); 2810 EMIT(0, 4); 2811 *pprog = prog; 2812 } 2813 } 2814 2815 /* get the count of the regs that are used to pass arguments */ 2816 static int get_nr_used_regs(const struct btf_func_model *m) 2817 { 2818 int i, arg_regs, nr_used_regs = 0; 2819 2820 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2821 arg_regs = (m->arg_size[i] + 7) / 8; 2822 if (nr_used_regs + arg_regs <= 6) 2823 nr_used_regs += arg_regs; 2824 2825 if (nr_used_regs >= 6) 2826 break; 2827 } 2828 2829 return nr_used_regs; 2830 } 2831 2832 static void save_args(const struct btf_func_model *m, u8 **prog, 2833 int stack_size, bool for_call_origin) 2834 { 2835 int arg_regs, first_off = 0, nr_regs = 0, nr_stack_slots = 0; 2836 int i, j; 2837 2838 /* Store function arguments to stack. 2839 * For a function that accepts two pointers the sequence will be: 2840 * mov QWORD PTR [rbp-0x10],rdi 2841 * mov QWORD PTR [rbp-0x8],rsi 2842 */ 2843 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2844 arg_regs = (m->arg_size[i] + 7) / 8; 2845 2846 /* According to the research of Yonghong, struct members 2847 * should be all in register or all on the stack. 2848 * Meanwhile, the compiler will pass the argument on regs 2849 * if the remaining regs can hold the argument. 2850 * 2851 * Disorder of the args can happen. For example: 2852 * 2853 * struct foo_struct { 2854 * long a; 2855 * int b; 2856 * }; 2857 * int foo(char, char, char, char, char, struct foo_struct, 2858 * char); 2859 * 2860 * the arg1-5,arg7 will be passed by regs, and arg6 will 2861 * by stack. 2862 */ 2863 if (nr_regs + arg_regs > 6) { 2864 /* copy function arguments from origin stack frame 2865 * into current stack frame. 2866 * 2867 * The starting address of the arguments on-stack 2868 * is: 2869 * rbp + 8(push rbp) + 2870 * 8(return addr of origin call) + 2871 * 8(return addr of the caller) 2872 * which means: rbp + 24 2873 */ 2874 for (j = 0; j < arg_regs; j++) { 2875 emit_ldx(prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 2876 nr_stack_slots * 8 + 0x18); 2877 emit_stx(prog, BPF_DW, BPF_REG_FP, BPF_REG_0, 2878 -stack_size); 2879 2880 if (!nr_stack_slots) 2881 first_off = stack_size; 2882 stack_size -= 8; 2883 nr_stack_slots++; 2884 } 2885 } else { 2886 /* Only copy the arguments on-stack to current 2887 * 'stack_size' and ignore the regs, used to 2888 * prepare the arguments on-stack for origin call. 2889 */ 2890 if (for_call_origin) { 2891 nr_regs += arg_regs; 2892 continue; 2893 } 2894 2895 /* copy the arguments from regs into stack */ 2896 for (j = 0; j < arg_regs; j++) { 2897 emit_stx(prog, BPF_DW, BPF_REG_FP, 2898 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2899 -stack_size); 2900 stack_size -= 8; 2901 nr_regs++; 2902 } 2903 } 2904 } 2905 2906 clean_stack_garbage(m, prog, nr_stack_slots, first_off); 2907 } 2908 2909 static void restore_regs(const struct btf_func_model *m, u8 **prog, 2910 int stack_size) 2911 { 2912 int i, j, arg_regs, nr_regs = 0; 2913 2914 /* Restore function arguments from stack. 2915 * For a function that accepts two pointers the sequence will be: 2916 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10] 2917 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8] 2918 * 2919 * The logic here is similar to what we do in save_args() 2920 */ 2921 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) { 2922 arg_regs = (m->arg_size[i] + 7) / 8; 2923 if (nr_regs + arg_regs <= 6) { 2924 for (j = 0; j < arg_regs; j++) { 2925 emit_ldx(prog, BPF_DW, 2926 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs, 2927 BPF_REG_FP, 2928 -stack_size); 2929 stack_size -= 8; 2930 nr_regs++; 2931 } 2932 } else { 2933 stack_size -= 8 * arg_regs; 2934 } 2935 2936 if (nr_regs >= 6) 2937 break; 2938 } 2939 } 2940 2941 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog, 2942 struct bpf_tramp_link *l, int stack_size, 2943 int run_ctx_off, bool save_ret, 2944 void *image, void *rw_image) 2945 { 2946 u8 *prog = *pprog; 2947 u8 *jmp_insn; 2948 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie); 2949 struct bpf_prog *p = l->link.prog; 2950 u64 cookie = l->cookie; 2951 2952 /* mov rdi, cookie */ 2953 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie); 2954 2955 /* Prepare struct bpf_tramp_run_ctx. 2956 * 2957 * bpf_tramp_run_ctx is already preserved by 2958 * arch_prepare_bpf_trampoline(). 2959 * 2960 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi 2961 */ 2962 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off); 2963 2964 /* arg1: mov rdi, progs[i] */ 2965 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 2966 /* arg2: lea rsi, [rbp - ctx_cookie_off] */ 2967 if (!is_imm8(-run_ctx_off)) 2968 EMIT3_off32(0x48, 0x8D, 0xB5, -run_ctx_off); 2969 else 2970 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off); 2971 2972 if (emit_rsb_call(&prog, bpf_trampoline_enter(p), image + (prog - (u8 *)rw_image))) 2973 return -EINVAL; 2974 /* remember prog start time returned by __bpf_prog_enter */ 2975 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0); 2976 2977 /* if (__bpf_prog_enter*(prog) == 0) 2978 * goto skip_exec_of_prog; 2979 */ 2980 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */ 2981 /* emit 2 nops that will be replaced with JE insn */ 2982 jmp_insn = prog; 2983 emit_nops(&prog, 2); 2984 2985 /* arg1: lea rdi, [rbp - stack_size] */ 2986 if (!is_imm8(-stack_size)) 2987 EMIT3_off32(0x48, 0x8D, 0xBD, -stack_size); 2988 else 2989 EMIT4(0x48, 0x8D, 0x7D, -stack_size); 2990 /* arg2: progs[i]->insnsi for interpreter */ 2991 if (!p->jited) 2992 emit_mov_imm64(&prog, BPF_REG_2, 2993 (long) p->insnsi >> 32, 2994 (u32) (long) p->insnsi); 2995 /* call JITed bpf program or interpreter */ 2996 if (emit_rsb_call(&prog, p->bpf_func, image + (prog - (u8 *)rw_image))) 2997 return -EINVAL; 2998 2999 /* 3000 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return 3001 * of the previous call which is then passed on the stack to 3002 * the next BPF program. 3003 * 3004 * BPF_TRAMP_FENTRY trampoline may need to return the return 3005 * value of BPF_PROG_TYPE_STRUCT_OPS prog. 3006 */ 3007 if (save_ret) 3008 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 3009 3010 /* replace 2 nops with JE insn, since jmp target is known */ 3011 jmp_insn[0] = X86_JE; 3012 jmp_insn[1] = prog - jmp_insn - 2; 3013 3014 /* arg1: mov rdi, progs[i] */ 3015 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p); 3016 /* arg2: mov rsi, rbx <- start time in nsec */ 3017 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6); 3018 /* arg3: lea rdx, [rbp - run_ctx_off] */ 3019 if (!is_imm8(-run_ctx_off)) 3020 EMIT3_off32(0x48, 0x8D, 0x95, -run_ctx_off); 3021 else 3022 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off); 3023 if (emit_rsb_call(&prog, bpf_trampoline_exit(p), image + (prog - (u8 *)rw_image))) 3024 return -EINVAL; 3025 3026 *pprog = prog; 3027 return 0; 3028 } 3029 3030 static void emit_align(u8 **pprog, u32 align) 3031 { 3032 u8 *target, *prog = *pprog; 3033 3034 target = PTR_ALIGN(prog, align); 3035 if (target != prog) 3036 emit_nops(&prog, target - prog); 3037 3038 *pprog = prog; 3039 } 3040 3041 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond) 3042 { 3043 u8 *prog = *pprog; 3044 s64 offset; 3045 3046 offset = func - (ip + 2 + 4); 3047 if (!is_simm32(offset)) { 3048 pr_err("Target %p is out of range\n", func); 3049 return -EINVAL; 3050 } 3051 EMIT2_off32(0x0F, jmp_cond + 0x10, offset); 3052 *pprog = prog; 3053 return 0; 3054 } 3055 3056 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog, 3057 struct bpf_tramp_links *tl, int stack_size, 3058 int run_ctx_off, bool save_ret, 3059 void *image, void *rw_image) 3060 { 3061 int i; 3062 u8 *prog = *pprog; 3063 3064 for (i = 0; i < tl->nr_links; i++) { 3065 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, 3066 run_ctx_off, save_ret, image, rw_image)) 3067 return -EINVAL; 3068 } 3069 *pprog = prog; 3070 return 0; 3071 } 3072 3073 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog, 3074 struct bpf_tramp_links *tl, int stack_size, 3075 int run_ctx_off, u8 **branches, 3076 void *image, void *rw_image) 3077 { 3078 u8 *prog = *pprog; 3079 int i; 3080 3081 /* The first fmod_ret program will receive a garbage return value. 3082 * Set this to 0 to avoid confusing the program. 3083 */ 3084 emit_mov_imm32(&prog, false, BPF_REG_0, 0); 3085 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 3086 for (i = 0; i < tl->nr_links; i++) { 3087 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true, 3088 image, rw_image)) 3089 return -EINVAL; 3090 3091 /* mod_ret prog stored return value into [rbp - 8]. Emit: 3092 * if (*(u64 *)(rbp - 8) != 0) 3093 * goto do_fexit; 3094 */ 3095 /* cmp QWORD PTR [rbp - 0x8], 0x0 */ 3096 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00); 3097 3098 /* Save the location of the branch and Generate 6 nops 3099 * (4 bytes for an offset and 2 bytes for the jump) These nops 3100 * are replaced with a conditional jump once do_fexit (i.e. the 3101 * start of the fexit invocation) is finalized. 3102 */ 3103 branches[i] = prog; 3104 emit_nops(&prog, 4 + 2); 3105 } 3106 3107 *pprog = prog; 3108 return 0; 3109 } 3110 3111 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */ 3112 #define LOAD_TRAMP_TAIL_CALL_CNT_PTR(stack) \ 3113 __LOAD_TCC_PTR(-round_up(stack, 8) - 8) 3114 3115 /* Example: 3116 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev); 3117 * its 'struct btf_func_model' will be nr_args=2 3118 * The assembly code when eth_type_trans is executing after trampoline: 3119 * 3120 * push rbp 3121 * mov rbp, rsp 3122 * sub rsp, 16 // space for skb and dev 3123 * push rbx // temp regs to pass start time 3124 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack 3125 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack 3126 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 3127 * mov rbx, rax // remember start time in bpf stats are enabled 3128 * lea rdi, [rbp - 16] // R1==ctx of bpf prog 3129 * call addr_of_jited_FENTRY_prog 3130 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 3131 * mov rsi, rbx // prog start time 3132 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 3133 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack 3134 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack 3135 * pop rbx 3136 * leave 3137 * ret 3138 * 3139 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be 3140 * replaced with 'call generated_bpf_trampoline'. When it returns 3141 * eth_type_trans will continue executing with original skb and dev pointers. 3142 * 3143 * The assembly code when eth_type_trans is called from trampoline: 3144 * 3145 * push rbp 3146 * mov rbp, rsp 3147 * sub rsp, 24 // space for skb, dev, return value 3148 * push rbx // temp regs to pass start time 3149 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack 3150 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack 3151 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 3152 * mov rbx, rax // remember start time if bpf stats are enabled 3153 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 3154 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev 3155 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 3156 * mov rsi, rbx // prog start time 3157 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 3158 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack 3159 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack 3160 * call eth_type_trans+5 // execute body of eth_type_trans 3161 * mov qword ptr [rbp - 8], rax // save return value 3162 * call __bpf_prog_enter // rcu_read_lock and preempt_disable 3163 * mov rbx, rax // remember start time in bpf stats are enabled 3164 * lea rdi, [rbp - 24] // R1==ctx of bpf prog 3165 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value 3166 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off 3167 * mov rsi, rbx // prog start time 3168 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math 3169 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value 3170 * pop rbx 3171 * leave 3172 * add rsp, 8 // skip eth_type_trans's frame 3173 * ret // return to its caller 3174 */ 3175 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *rw_image, 3176 void *rw_image_end, void *image, 3177 const struct btf_func_model *m, u32 flags, 3178 struct bpf_tramp_links *tlinks, 3179 void *func_addr) 3180 { 3181 int i, ret, nr_regs = m->nr_args, stack_size = 0; 3182 int regs_off, nregs_off, ip_off, run_ctx_off, arg_stack_off, rbx_off; 3183 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY]; 3184 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT]; 3185 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN]; 3186 void *orig_call = func_addr; 3187 u8 **branches = NULL; 3188 u8 *prog; 3189 bool save_ret; 3190 3191 /* 3192 * F_INDIRECT is only compatible with F_RET_FENTRY_RET, it is 3193 * explicitly incompatible with F_CALL_ORIG | F_SKIP_FRAME | F_IP_ARG 3194 * because @func_addr. 3195 */ 3196 WARN_ON_ONCE((flags & BPF_TRAMP_F_INDIRECT) && 3197 (flags & ~(BPF_TRAMP_F_INDIRECT | BPF_TRAMP_F_RET_FENTRY_RET))); 3198 3199 /* extra registers for struct arguments */ 3200 for (i = 0; i < m->nr_args; i++) { 3201 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) 3202 nr_regs += (m->arg_size[i] + 7) / 8 - 1; 3203 } 3204 3205 /* x86-64 supports up to MAX_BPF_FUNC_ARGS arguments. 1-6 3206 * are passed through regs, the remains are through stack. 3207 */ 3208 if (nr_regs > MAX_BPF_FUNC_ARGS) 3209 return -ENOTSUPP; 3210 3211 /* Generated trampoline stack layout: 3212 * 3213 * RBP + 8 [ return address ] 3214 * RBP + 0 [ RBP ] 3215 * 3216 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or 3217 * BPF_TRAMP_F_RET_FENTRY_RET flags 3218 * 3219 * [ reg_argN ] always 3220 * [ ... ] 3221 * RBP - regs_off [ reg_arg1 ] program's ctx pointer 3222 * 3223 * RBP - nregs_off [ regs count ] always 3224 * 3225 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag 3226 * 3227 * RBP - rbx_off [ rbx value ] always 3228 * 3229 * RBP - run_ctx_off [ bpf_tramp_run_ctx ] 3230 * 3231 * [ stack_argN ] BPF_TRAMP_F_CALL_ORIG 3232 * [ ... ] 3233 * [ stack_arg2 ] 3234 * RBP - arg_stack_off [ stack_arg1 ] 3235 * RSP [ tail_call_cnt_ptr ] BPF_TRAMP_F_TAIL_CALL_CTX 3236 */ 3237 3238 /* room for return value of orig_call or fentry prog */ 3239 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET); 3240 if (save_ret) 3241 stack_size += 8; 3242 3243 stack_size += nr_regs * 8; 3244 regs_off = stack_size; 3245 3246 /* regs count */ 3247 stack_size += 8; 3248 nregs_off = stack_size; 3249 3250 if (flags & BPF_TRAMP_F_IP_ARG) 3251 stack_size += 8; /* room for IP address argument */ 3252 3253 ip_off = stack_size; 3254 3255 stack_size += 8; 3256 rbx_off = stack_size; 3257 3258 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7; 3259 run_ctx_off = stack_size; 3260 3261 if (nr_regs > 6 && (flags & BPF_TRAMP_F_CALL_ORIG)) { 3262 /* the space that used to pass arguments on-stack */ 3263 stack_size += (nr_regs - get_nr_used_regs(m)) * 8; 3264 /* make sure the stack pointer is 16-byte aligned if we 3265 * need pass arguments on stack, which means 3266 * [stack_size + 8(rbp) + 8(rip) + 8(origin rip)] 3267 * should be 16-byte aligned. Following code depend on 3268 * that stack_size is already 8-byte aligned. 3269 */ 3270 stack_size += (stack_size % 16) ? 0 : 8; 3271 } 3272 3273 arg_stack_off = stack_size; 3274 3275 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 3276 /* skip patched call instruction and point orig_call to actual 3277 * body of the kernel function. 3278 */ 3279 if (is_endbr(orig_call)) 3280 orig_call += ENDBR_INSN_SIZE; 3281 orig_call += X86_PATCH_SIZE; 3282 } 3283 3284 prog = rw_image; 3285 3286 if (flags & BPF_TRAMP_F_INDIRECT) { 3287 /* 3288 * Indirect call for bpf_struct_ops 3289 */ 3290 emit_cfi(&prog, image, 3291 cfi_get_func_hash(func_addr), 3292 cfi_get_func_arity(func_addr)); 3293 } else { 3294 /* 3295 * Direct-call fentry stub, as such it needs accounting for the 3296 * __fentry__ call. 3297 */ 3298 x86_call_depth_emit_accounting(&prog, NULL, image); 3299 } 3300 EMIT1(0x55); /* push rbp */ 3301 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ 3302 if (!is_imm8(stack_size)) { 3303 /* sub rsp, stack_size */ 3304 EMIT3_off32(0x48, 0x81, 0xEC, stack_size); 3305 } else { 3306 /* sub rsp, stack_size */ 3307 EMIT4(0x48, 0x83, 0xEC, stack_size); 3308 } 3309 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) 3310 EMIT1(0x50); /* push rax */ 3311 /* mov QWORD PTR [rbp - rbx_off], rbx */ 3312 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_6, -rbx_off); 3313 3314 /* Store number of argument registers of the traced function: 3315 * mov rax, nr_regs 3316 * mov QWORD PTR [rbp - nregs_off], rax 3317 */ 3318 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs); 3319 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off); 3320 3321 if (flags & BPF_TRAMP_F_IP_ARG) { 3322 /* Store IP address of the traced function: 3323 * movabsq rax, func_addr 3324 * mov QWORD PTR [rbp - ip_off], rax 3325 */ 3326 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr); 3327 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off); 3328 } 3329 3330 save_args(m, &prog, regs_off, false); 3331 3332 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3333 /* arg1: mov rdi, im */ 3334 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 3335 if (emit_rsb_call(&prog, __bpf_tramp_enter, 3336 image + (prog - (u8 *)rw_image))) { 3337 ret = -EINVAL; 3338 goto cleanup; 3339 } 3340 } 3341 3342 if (fentry->nr_links) { 3343 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off, 3344 flags & BPF_TRAMP_F_RET_FENTRY_RET, image, rw_image)) 3345 return -EINVAL; 3346 } 3347 3348 if (fmod_ret->nr_links) { 3349 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *), 3350 GFP_KERNEL); 3351 if (!branches) 3352 return -ENOMEM; 3353 3354 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off, 3355 run_ctx_off, branches, image, rw_image)) { 3356 ret = -EINVAL; 3357 goto cleanup; 3358 } 3359 } 3360 3361 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3362 restore_regs(m, &prog, regs_off); 3363 save_args(m, &prog, arg_stack_off, true); 3364 3365 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) { 3366 /* Before calling the original function, load the 3367 * tail_call_cnt_ptr from stack to rax. 3368 */ 3369 LOAD_TRAMP_TAIL_CALL_CNT_PTR(stack_size); 3370 } 3371 3372 if (flags & BPF_TRAMP_F_ORIG_STACK) { 3373 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, 8); 3374 EMIT2(0xff, 0xd3); /* call *rbx */ 3375 } else { 3376 /* call original function */ 3377 if (emit_rsb_call(&prog, orig_call, image + (prog - (u8 *)rw_image))) { 3378 ret = -EINVAL; 3379 goto cleanup; 3380 } 3381 } 3382 /* remember return value in a stack for bpf prog to access */ 3383 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8); 3384 im->ip_after_call = image + (prog - (u8 *)rw_image); 3385 emit_nops(&prog, X86_PATCH_SIZE); 3386 } 3387 3388 if (fmod_ret->nr_links) { 3389 /* From Intel 64 and IA-32 Architectures Optimization 3390 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 3391 * Coding Rule 11: All branch targets should be 16-byte 3392 * aligned. 3393 */ 3394 emit_align(&prog, 16); 3395 /* Update the branches saved in invoke_bpf_mod_ret with the 3396 * aligned address of do_fexit. 3397 */ 3398 for (i = 0; i < fmod_ret->nr_links; i++) { 3399 emit_cond_near_jump(&branches[i], image + (prog - (u8 *)rw_image), 3400 image + (branches[i] - (u8 *)rw_image), X86_JNE); 3401 } 3402 } 3403 3404 if (fexit->nr_links) { 3405 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, 3406 false, image, rw_image)) { 3407 ret = -EINVAL; 3408 goto cleanup; 3409 } 3410 } 3411 3412 if (flags & BPF_TRAMP_F_RESTORE_REGS) 3413 restore_regs(m, &prog, regs_off); 3414 3415 /* This needs to be done regardless. If there were fmod_ret programs, 3416 * the return value is only updated on the stack and still needs to be 3417 * restored to R0. 3418 */ 3419 if (flags & BPF_TRAMP_F_CALL_ORIG) { 3420 im->ip_epilogue = image + (prog - (u8 *)rw_image); 3421 /* arg1: mov rdi, im */ 3422 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im); 3423 if (emit_rsb_call(&prog, __bpf_tramp_exit, image + (prog - (u8 *)rw_image))) { 3424 ret = -EINVAL; 3425 goto cleanup; 3426 } 3427 } else if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) { 3428 /* Before running the original function, load the 3429 * tail_call_cnt_ptr from stack to rax. 3430 */ 3431 LOAD_TRAMP_TAIL_CALL_CNT_PTR(stack_size); 3432 } 3433 3434 /* restore return value of orig_call or fentry prog back into RAX */ 3435 if (save_ret) 3436 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8); 3437 3438 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, -rbx_off); 3439 EMIT1(0xC9); /* leave */ 3440 if (flags & BPF_TRAMP_F_SKIP_FRAME) { 3441 /* skip our return address and return to parent */ 3442 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */ 3443 } 3444 emit_return(&prog, image + (prog - (u8 *)rw_image)); 3445 /* Make sure the trampoline generation logic doesn't overflow */ 3446 if (WARN_ON_ONCE(prog > (u8 *)rw_image_end - BPF_INSN_SAFETY)) { 3447 ret = -EFAULT; 3448 goto cleanup; 3449 } 3450 ret = prog - (u8 *)rw_image + BPF_INSN_SAFETY; 3451 3452 cleanup: 3453 kfree(branches); 3454 return ret; 3455 } 3456 3457 void *arch_alloc_bpf_trampoline(unsigned int size) 3458 { 3459 return bpf_prog_pack_alloc(size, jit_fill_hole); 3460 } 3461 3462 void arch_free_bpf_trampoline(void *image, unsigned int size) 3463 { 3464 bpf_prog_pack_free(image, size); 3465 } 3466 3467 int arch_protect_bpf_trampoline(void *image, unsigned int size) 3468 { 3469 return 0; 3470 } 3471 3472 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end, 3473 const struct btf_func_model *m, u32 flags, 3474 struct bpf_tramp_links *tlinks, 3475 void *func_addr) 3476 { 3477 void *rw_image, *tmp; 3478 int ret; 3479 u32 size = image_end - image; 3480 3481 /* rw_image doesn't need to be in module memory range, so we can 3482 * use kvmalloc. 3483 */ 3484 rw_image = kvmalloc(size, GFP_KERNEL); 3485 if (!rw_image) 3486 return -ENOMEM; 3487 3488 ret = __arch_prepare_bpf_trampoline(im, rw_image, rw_image + size, image, m, 3489 flags, tlinks, func_addr); 3490 if (ret < 0) 3491 goto out; 3492 3493 tmp = bpf_arch_text_copy(image, rw_image, size); 3494 if (IS_ERR(tmp)) 3495 ret = PTR_ERR(tmp); 3496 out: 3497 kvfree(rw_image); 3498 return ret; 3499 } 3500 3501 int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags, 3502 struct bpf_tramp_links *tlinks, void *func_addr) 3503 { 3504 struct bpf_tramp_image im; 3505 void *image; 3506 int ret; 3507 3508 /* Allocate a temporary buffer for __arch_prepare_bpf_trampoline(). 3509 * This will NOT cause fragmentation in direct map, as we do not 3510 * call set_memory_*() on this buffer. 3511 * 3512 * We cannot use kvmalloc here, because we need image to be in 3513 * module memory range. 3514 */ 3515 image = bpf_jit_alloc_exec(PAGE_SIZE); 3516 if (!image) 3517 return -ENOMEM; 3518 3519 ret = __arch_prepare_bpf_trampoline(&im, image, image + PAGE_SIZE, image, 3520 m, flags, tlinks, func_addr); 3521 bpf_jit_free_exec(image); 3522 return ret; 3523 } 3524 3525 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf) 3526 { 3527 u8 *jg_reloc, *prog = *pprog; 3528 int pivot, err, jg_bytes = 1; 3529 s64 jg_offset; 3530 3531 if (a == b) { 3532 /* Leaf node of recursion, i.e. not a range of indices 3533 * anymore. 3534 */ 3535 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 3536 if (!is_simm32(progs[a])) 3537 return -1; 3538 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), 3539 progs[a]); 3540 err = emit_cond_near_jump(&prog, /* je func */ 3541 (void *)progs[a], image + (prog - buf), 3542 X86_JE); 3543 if (err) 3544 return err; 3545 3546 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf)); 3547 3548 *pprog = prog; 3549 return 0; 3550 } 3551 3552 /* Not a leaf node, so we pivot, and recursively descend into 3553 * the lower and upper ranges. 3554 */ 3555 pivot = (b - a) / 2; 3556 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */ 3557 if (!is_simm32(progs[a + pivot])) 3558 return -1; 3559 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]); 3560 3561 if (pivot > 2) { /* jg upper_part */ 3562 /* Require near jump. */ 3563 jg_bytes = 4; 3564 EMIT2_off32(0x0F, X86_JG + 0x10, 0); 3565 } else { 3566 EMIT2(X86_JG, 0); 3567 } 3568 jg_reloc = prog; 3569 3570 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */ 3571 progs, image, buf); 3572 if (err) 3573 return err; 3574 3575 /* From Intel 64 and IA-32 Architectures Optimization 3576 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler 3577 * Coding Rule 11: All branch targets should be 16-byte 3578 * aligned. 3579 */ 3580 emit_align(&prog, 16); 3581 jg_offset = prog - jg_reloc; 3582 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes); 3583 3584 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */ 3585 b, progs, image, buf); 3586 if (err) 3587 return err; 3588 3589 *pprog = prog; 3590 return 0; 3591 } 3592 3593 static int cmp_ips(const void *a, const void *b) 3594 { 3595 const s64 *ipa = a; 3596 const s64 *ipb = b; 3597 3598 if (*ipa > *ipb) 3599 return 1; 3600 if (*ipa < *ipb) 3601 return -1; 3602 return 0; 3603 } 3604 3605 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs) 3606 { 3607 u8 *prog = buf; 3608 3609 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL); 3610 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf); 3611 } 3612 3613 static void priv_stack_init_guard(void __percpu *priv_stack_ptr, int alloc_size) 3614 { 3615 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 3616 u64 *stack_ptr; 3617 3618 for_each_possible_cpu(cpu) { 3619 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 3620 stack_ptr[0] = PRIV_STACK_GUARD_VAL; 3621 stack_ptr[underflow_idx] = PRIV_STACK_GUARD_VAL; 3622 } 3623 } 3624 3625 static void priv_stack_check_guard(void __percpu *priv_stack_ptr, int alloc_size, 3626 struct bpf_prog *prog) 3627 { 3628 int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3; 3629 u64 *stack_ptr; 3630 3631 for_each_possible_cpu(cpu) { 3632 stack_ptr = per_cpu_ptr(priv_stack_ptr, cpu); 3633 if (stack_ptr[0] != PRIV_STACK_GUARD_VAL || 3634 stack_ptr[underflow_idx] != PRIV_STACK_GUARD_VAL) { 3635 pr_err("BPF private stack overflow/underflow detected for prog %sx\n", 3636 bpf_jit_get_prog_name(prog)); 3637 break; 3638 } 3639 } 3640 } 3641 3642 struct x64_jit_data { 3643 struct bpf_binary_header *rw_header; 3644 struct bpf_binary_header *header; 3645 int *addrs; 3646 u8 *image; 3647 int proglen; 3648 struct jit_context ctx; 3649 }; 3650 3651 #define MAX_PASSES 20 3652 #define PADDING_PASSES (MAX_PASSES - 5) 3653 3654 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) 3655 { 3656 struct bpf_binary_header *rw_header = NULL; 3657 struct bpf_binary_header *header = NULL; 3658 struct bpf_prog *tmp, *orig_prog = prog; 3659 void __percpu *priv_stack_ptr = NULL; 3660 struct x64_jit_data *jit_data; 3661 int priv_stack_alloc_sz; 3662 int proglen, oldproglen = 0; 3663 struct jit_context ctx = {}; 3664 bool tmp_blinded = false; 3665 bool extra_pass = false; 3666 bool padding = false; 3667 u8 *rw_image = NULL; 3668 u8 *image = NULL; 3669 int *addrs; 3670 int pass; 3671 int i; 3672 3673 if (!prog->jit_requested) 3674 return orig_prog; 3675 3676 tmp = bpf_jit_blind_constants(prog); 3677 /* 3678 * If blinding was requested and we failed during blinding, 3679 * we must fall back to the interpreter. 3680 */ 3681 if (IS_ERR(tmp)) 3682 return orig_prog; 3683 if (tmp != prog) { 3684 tmp_blinded = true; 3685 prog = tmp; 3686 } 3687 3688 jit_data = prog->aux->jit_data; 3689 if (!jit_data) { 3690 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); 3691 if (!jit_data) { 3692 prog = orig_prog; 3693 goto out; 3694 } 3695 prog->aux->jit_data = jit_data; 3696 } 3697 priv_stack_ptr = prog->aux->priv_stack_ptr; 3698 if (!priv_stack_ptr && prog->aux->jits_use_priv_stack) { 3699 /* Allocate actual private stack size with verifier-calculated 3700 * stack size plus two memory guards to protect overflow and 3701 * underflow. 3702 */ 3703 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 8) + 3704 2 * PRIV_STACK_GUARD_SZ; 3705 priv_stack_ptr = __alloc_percpu_gfp(priv_stack_alloc_sz, 8, GFP_KERNEL); 3706 if (!priv_stack_ptr) { 3707 prog = orig_prog; 3708 goto out_priv_stack; 3709 } 3710 3711 priv_stack_init_guard(priv_stack_ptr, priv_stack_alloc_sz); 3712 prog->aux->priv_stack_ptr = priv_stack_ptr; 3713 } 3714 addrs = jit_data->addrs; 3715 if (addrs) { 3716 ctx = jit_data->ctx; 3717 oldproglen = jit_data->proglen; 3718 image = jit_data->image; 3719 header = jit_data->header; 3720 rw_header = jit_data->rw_header; 3721 rw_image = (void *)rw_header + ((void *)image - (void *)header); 3722 extra_pass = true; 3723 padding = true; 3724 goto skip_init_addrs; 3725 } 3726 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL); 3727 if (!addrs) { 3728 prog = orig_prog; 3729 goto out_addrs; 3730 } 3731 3732 /* 3733 * Before first pass, make a rough estimation of addrs[] 3734 * each BPF instruction is translated to less than 64 bytes 3735 */ 3736 for (proglen = 0, i = 0; i <= prog->len; i++) { 3737 proglen += 64; 3738 addrs[i] = proglen; 3739 } 3740 ctx.cleanup_addr = proglen; 3741 skip_init_addrs: 3742 3743 /* 3744 * JITed image shrinks with every pass and the loop iterates 3745 * until the image stops shrinking. Very large BPF programs 3746 * may converge on the last pass. In such case do one more 3747 * pass to emit the final image. 3748 */ 3749 for (pass = 0; pass < MAX_PASSES || image; pass++) { 3750 if (!padding && pass >= PADDING_PASSES) 3751 padding = true; 3752 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding); 3753 if (proglen <= 0) { 3754 out_image: 3755 image = NULL; 3756 if (header) { 3757 bpf_arch_text_copy(&header->size, &rw_header->size, 3758 sizeof(rw_header->size)); 3759 bpf_jit_binary_pack_free(header, rw_header); 3760 } 3761 /* Fall back to interpreter mode */ 3762 prog = orig_prog; 3763 if (extra_pass) { 3764 prog->bpf_func = NULL; 3765 prog->jited = 0; 3766 prog->jited_len = 0; 3767 } 3768 goto out_addrs; 3769 } 3770 if (image) { 3771 if (proglen != oldproglen) { 3772 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n", 3773 proglen, oldproglen); 3774 goto out_image; 3775 } 3776 break; 3777 } 3778 if (proglen == oldproglen) { 3779 /* 3780 * The number of entries in extable is the number of BPF_LDX 3781 * insns that access kernel memory via "pointer to BTF type". 3782 * The verifier changed their opcode from LDX|MEM|size 3783 * to LDX|PROBE_MEM|size to make JITing easier. 3784 */ 3785 u32 align = __alignof__(struct exception_table_entry); 3786 u32 extable_size = prog->aux->num_exentries * 3787 sizeof(struct exception_table_entry); 3788 3789 /* allocate module memory for x86 insns and extable */ 3790 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size, 3791 &image, align, &rw_header, &rw_image, 3792 jit_fill_hole); 3793 if (!header) { 3794 prog = orig_prog; 3795 goto out_addrs; 3796 } 3797 prog->aux->extable = (void *) image + roundup(proglen, align); 3798 } 3799 oldproglen = proglen; 3800 cond_resched(); 3801 } 3802 3803 if (bpf_jit_enable > 1) 3804 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image); 3805 3806 if (image) { 3807 if (!prog->is_func || extra_pass) { 3808 /* 3809 * bpf_jit_binary_pack_finalize fails in two scenarios: 3810 * 1) header is not pointing to proper module memory; 3811 * 2) the arch doesn't support bpf_arch_text_copy(). 3812 * 3813 * Both cases are serious bugs and justify WARN_ON. 3814 */ 3815 if (WARN_ON(bpf_jit_binary_pack_finalize(header, rw_header))) { 3816 /* header has been freed */ 3817 header = NULL; 3818 goto out_image; 3819 } 3820 3821 bpf_tail_call_direct_fixup(prog); 3822 } else { 3823 jit_data->addrs = addrs; 3824 jit_data->ctx = ctx; 3825 jit_data->proglen = proglen; 3826 jit_data->image = image; 3827 jit_data->header = header; 3828 jit_data->rw_header = rw_header; 3829 } 3830 /* 3831 * ctx.prog_offset is used when CFI preambles put code *before* 3832 * the function. See emit_cfi(). For FineIBT specifically this code 3833 * can also be executed and bpf_prog_kallsyms_add() will 3834 * generate an additional symbol to cover this, hence also 3835 * decrement proglen. 3836 */ 3837 prog->bpf_func = (void *)image + cfi_get_offset(); 3838 prog->jited = 1; 3839 prog->jited_len = proglen - cfi_get_offset(); 3840 } else { 3841 prog = orig_prog; 3842 } 3843 3844 if (!image || !prog->is_func || extra_pass) { 3845 if (image) 3846 bpf_prog_fill_jited_linfo(prog, addrs + 1); 3847 out_addrs: 3848 kvfree(addrs); 3849 if (!image && priv_stack_ptr) { 3850 free_percpu(priv_stack_ptr); 3851 prog->aux->priv_stack_ptr = NULL; 3852 } 3853 out_priv_stack: 3854 kfree(jit_data); 3855 prog->aux->jit_data = NULL; 3856 } 3857 out: 3858 if (tmp_blinded) 3859 bpf_jit_prog_release_other(prog, prog == orig_prog ? 3860 tmp : orig_prog); 3861 return prog; 3862 } 3863 3864 bool bpf_jit_supports_kfunc_call(void) 3865 { 3866 return true; 3867 } 3868 3869 void *bpf_arch_text_copy(void *dst, void *src, size_t len) 3870 { 3871 if (text_poke_copy(dst, src, len) == NULL) 3872 return ERR_PTR(-EINVAL); 3873 return dst; 3874 } 3875 3876 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */ 3877 bool bpf_jit_supports_subprog_tailcalls(void) 3878 { 3879 return true; 3880 } 3881 3882 bool bpf_jit_supports_percpu_insn(void) 3883 { 3884 return true; 3885 } 3886 3887 void bpf_jit_free(struct bpf_prog *prog) 3888 { 3889 if (prog->jited) { 3890 struct x64_jit_data *jit_data = prog->aux->jit_data; 3891 struct bpf_binary_header *hdr; 3892 void __percpu *priv_stack_ptr; 3893 int priv_stack_alloc_sz; 3894 3895 /* 3896 * If we fail the final pass of JIT (from jit_subprogs), 3897 * the program may not be finalized yet. Call finalize here 3898 * before freeing it. 3899 */ 3900 if (jit_data) { 3901 bpf_jit_binary_pack_finalize(jit_data->header, 3902 jit_data->rw_header); 3903 kvfree(jit_data->addrs); 3904 kfree(jit_data); 3905 } 3906 prog->bpf_func = (void *)prog->bpf_func - cfi_get_offset(); 3907 hdr = bpf_jit_binary_pack_hdr(prog); 3908 bpf_jit_binary_pack_free(hdr, NULL); 3909 priv_stack_ptr = prog->aux->priv_stack_ptr; 3910 if (priv_stack_ptr) { 3911 priv_stack_alloc_sz = round_up(prog->aux->stack_depth, 8) + 3912 2 * PRIV_STACK_GUARD_SZ; 3913 priv_stack_check_guard(priv_stack_ptr, priv_stack_alloc_sz, prog); 3914 free_percpu(prog->aux->priv_stack_ptr); 3915 } 3916 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog)); 3917 } 3918 3919 bpf_prog_unlock_free(prog); 3920 } 3921 3922 bool bpf_jit_supports_exceptions(void) 3923 { 3924 /* We unwind through both kernel frames (starting from within bpf_throw 3925 * call) and BPF frames. Therefore we require ORC unwinder to be enabled 3926 * to walk kernel frames and reach BPF frames in the stack trace. 3927 */ 3928 return IS_ENABLED(CONFIG_UNWINDER_ORC); 3929 } 3930 3931 bool bpf_jit_supports_private_stack(void) 3932 { 3933 return true; 3934 } 3935 3936 void arch_bpf_stack_walk(bool (*consume_fn)(void *cookie, u64 ip, u64 sp, u64 bp), void *cookie) 3937 { 3938 #if defined(CONFIG_UNWINDER_ORC) 3939 struct unwind_state state; 3940 unsigned long addr; 3941 3942 for (unwind_start(&state, current, NULL, NULL); !unwind_done(&state); 3943 unwind_next_frame(&state)) { 3944 addr = unwind_get_return_address(&state); 3945 if (!addr || !consume_fn(cookie, (u64)addr, (u64)state.sp, (u64)state.bp)) 3946 break; 3947 } 3948 return; 3949 #endif 3950 } 3951 3952 void bpf_arch_poke_desc_update(struct bpf_jit_poke_descriptor *poke, 3953 struct bpf_prog *new, struct bpf_prog *old) 3954 { 3955 u8 *old_addr, *new_addr, *old_bypass_addr; 3956 int ret; 3957 3958 old_bypass_addr = old ? NULL : poke->bypass_addr; 3959 old_addr = old ? (u8 *)old->bpf_func + poke->adj_off : NULL; 3960 new_addr = new ? (u8 *)new->bpf_func + poke->adj_off : NULL; 3961 3962 /* 3963 * On program loading or teardown, the program's kallsym entry 3964 * might not be in place, so we use __bpf_arch_text_poke to skip 3965 * the kallsyms check. 3966 */ 3967 if (new) { 3968 ret = __bpf_arch_text_poke(poke->tailcall_target, 3969 BPF_MOD_JUMP, 3970 old_addr, new_addr); 3971 BUG_ON(ret < 0); 3972 if (!old) { 3973 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 3974 BPF_MOD_JUMP, 3975 poke->bypass_addr, 3976 NULL); 3977 BUG_ON(ret < 0); 3978 } 3979 } else { 3980 ret = __bpf_arch_text_poke(poke->tailcall_bypass, 3981 BPF_MOD_JUMP, 3982 old_bypass_addr, 3983 poke->bypass_addr); 3984 BUG_ON(ret < 0); 3985 /* let other CPUs finish the execution of program 3986 * so that it will not possible to expose them 3987 * to invalid nop, stack unwind, nop state 3988 */ 3989 if (!ret) 3990 synchronize_rcu(); 3991 ret = __bpf_arch_text_poke(poke->tailcall_target, 3992 BPF_MOD_JUMP, 3993 old_addr, NULL); 3994 BUG_ON(ret < 0); 3995 } 3996 } 3997 3998 bool bpf_jit_supports_arena(void) 3999 { 4000 return true; 4001 } 4002 4003 bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena) 4004 { 4005 if (!in_arena) 4006 return true; 4007 switch (insn->code) { 4008 case BPF_STX | BPF_ATOMIC | BPF_W: 4009 case BPF_STX | BPF_ATOMIC | BPF_DW: 4010 if (insn->imm == (BPF_AND | BPF_FETCH) || 4011 insn->imm == (BPF_OR | BPF_FETCH) || 4012 insn->imm == (BPF_XOR | BPF_FETCH)) 4013 return false; 4014 } 4015 return true; 4016 } 4017 4018 bool bpf_jit_supports_ptr_xchg(void) 4019 { 4020 return true; 4021 } 4022 4023 /* x86-64 JIT emits its own code to filter user addresses so return 0 here */ 4024 u64 bpf_arch_uaddress_limit(void) 4025 { 4026 return 0; 4027 } 4028 4029 bool bpf_jit_supports_timed_may_goto(void) 4030 { 4031 return true; 4032 } 4033