xref: /linux/arch/x86/mm/mem_encrypt_identity.c (revision 4e95bc268b915c3a19ec8b9110f61e4ea41a1ed0)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * AMD Memory Encryption Support
4  *
5  * Copyright (C) 2016 Advanced Micro Devices, Inc.
6  *
7  * Author: Tom Lendacky <thomas.lendacky@amd.com>
8  */
9 
10 #define DISABLE_BRANCH_PROFILING
11 
12 /*
13  * Since we're dealing with identity mappings, physical and virtual
14  * addresses are the same, so override these defines which are ultimately
15  * used by the headers in misc.h.
16  */
17 #define __pa(x)  ((unsigned long)(x))
18 #define __va(x)  ((void *)((unsigned long)(x)))
19 
20 /*
21  * Special hack: we have to be careful, because no indirections are
22  * allowed here, and paravirt_ops is a kind of one. As it will only run in
23  * baremetal anyway, we just keep it from happening. (This list needs to
24  * be extended when new paravirt and debugging variants are added.)
25  */
26 #undef CONFIG_PARAVIRT
27 #undef CONFIG_PARAVIRT_XXL
28 #undef CONFIG_PARAVIRT_SPINLOCKS
29 
30 #include <linux/kernel.h>
31 #include <linux/mm.h>
32 #include <linux/mem_encrypt.h>
33 
34 #include <asm/setup.h>
35 #include <asm/sections.h>
36 #include <asm/cmdline.h>
37 
38 #include "mm_internal.h"
39 
40 #define PGD_FLAGS		_KERNPG_TABLE_NOENC
41 #define P4D_FLAGS		_KERNPG_TABLE_NOENC
42 #define PUD_FLAGS		_KERNPG_TABLE_NOENC
43 #define PMD_FLAGS		_KERNPG_TABLE_NOENC
44 
45 #define PMD_FLAGS_LARGE		(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)
46 
47 #define PMD_FLAGS_DEC		PMD_FLAGS_LARGE
48 #define PMD_FLAGS_DEC_WP	((PMD_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
49 				 (_PAGE_PAT | _PAGE_PWT))
50 
51 #define PMD_FLAGS_ENC		(PMD_FLAGS_LARGE | _PAGE_ENC)
52 
53 #define PTE_FLAGS		(__PAGE_KERNEL_EXEC & ~_PAGE_GLOBAL)
54 
55 #define PTE_FLAGS_DEC		PTE_FLAGS
56 #define PTE_FLAGS_DEC_WP	((PTE_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
57 				 (_PAGE_PAT | _PAGE_PWT))
58 
59 #define PTE_FLAGS_ENC		(PTE_FLAGS | _PAGE_ENC)
60 
61 struct sme_populate_pgd_data {
62 	void    *pgtable_area;
63 	pgd_t   *pgd;
64 
65 	pmdval_t pmd_flags;
66 	pteval_t pte_flags;
67 	unsigned long paddr;
68 
69 	unsigned long vaddr;
70 	unsigned long vaddr_end;
71 };
72 
73 static char sme_cmdline_arg[] __initdata = "mem_encrypt";
74 static char sme_cmdline_on[]  __initdata = "on";
75 static char sme_cmdline_off[] __initdata = "off";
76 
77 static void __init sme_clear_pgd(struct sme_populate_pgd_data *ppd)
78 {
79 	unsigned long pgd_start, pgd_end, pgd_size;
80 	pgd_t *pgd_p;
81 
82 	pgd_start = ppd->vaddr & PGDIR_MASK;
83 	pgd_end = ppd->vaddr_end & PGDIR_MASK;
84 
85 	pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1) * sizeof(pgd_t);
86 
87 	pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
88 
89 	memset(pgd_p, 0, pgd_size);
90 }
91 
92 static pud_t __init *sme_prepare_pgd(struct sme_populate_pgd_data *ppd)
93 {
94 	pgd_t *pgd;
95 	p4d_t *p4d;
96 	pud_t *pud;
97 	pmd_t *pmd;
98 
99 	pgd = ppd->pgd + pgd_index(ppd->vaddr);
100 	if (pgd_none(*pgd)) {
101 		p4d = ppd->pgtable_area;
102 		memset(p4d, 0, sizeof(*p4d) * PTRS_PER_P4D);
103 		ppd->pgtable_area += sizeof(*p4d) * PTRS_PER_P4D;
104 		set_pgd(pgd, __pgd(PGD_FLAGS | __pa(p4d)));
105 	}
106 
107 	p4d = p4d_offset(pgd, ppd->vaddr);
108 	if (p4d_none(*p4d)) {
109 		pud = ppd->pgtable_area;
110 		memset(pud, 0, sizeof(*pud) * PTRS_PER_PUD);
111 		ppd->pgtable_area += sizeof(*pud) * PTRS_PER_PUD;
112 		set_p4d(p4d, __p4d(P4D_FLAGS | __pa(pud)));
113 	}
114 
115 	pud = pud_offset(p4d, ppd->vaddr);
116 	if (pud_none(*pud)) {
117 		pmd = ppd->pgtable_area;
118 		memset(pmd, 0, sizeof(*pmd) * PTRS_PER_PMD);
119 		ppd->pgtable_area += sizeof(*pmd) * PTRS_PER_PMD;
120 		set_pud(pud, __pud(PUD_FLAGS | __pa(pmd)));
121 	}
122 
123 	if (pud_large(*pud))
124 		return NULL;
125 
126 	return pud;
127 }
128 
129 static void __init sme_populate_pgd_large(struct sme_populate_pgd_data *ppd)
130 {
131 	pud_t *pud;
132 	pmd_t *pmd;
133 
134 	pud = sme_prepare_pgd(ppd);
135 	if (!pud)
136 		return;
137 
138 	pmd = pmd_offset(pud, ppd->vaddr);
139 	if (pmd_large(*pmd))
140 		return;
141 
142 	set_pmd(pmd, __pmd(ppd->paddr | ppd->pmd_flags));
143 }
144 
145 static void __init sme_populate_pgd(struct sme_populate_pgd_data *ppd)
146 {
147 	pud_t *pud;
148 	pmd_t *pmd;
149 	pte_t *pte;
150 
151 	pud = sme_prepare_pgd(ppd);
152 	if (!pud)
153 		return;
154 
155 	pmd = pmd_offset(pud, ppd->vaddr);
156 	if (pmd_none(*pmd)) {
157 		pte = ppd->pgtable_area;
158 		memset(pte, 0, sizeof(*pte) * PTRS_PER_PTE);
159 		ppd->pgtable_area += sizeof(*pte) * PTRS_PER_PTE;
160 		set_pmd(pmd, __pmd(PMD_FLAGS | __pa(pte)));
161 	}
162 
163 	if (pmd_large(*pmd))
164 		return;
165 
166 	pte = pte_offset_map(pmd, ppd->vaddr);
167 	if (pte_none(*pte))
168 		set_pte(pte, __pte(ppd->paddr | ppd->pte_flags));
169 }
170 
171 static void __init __sme_map_range_pmd(struct sme_populate_pgd_data *ppd)
172 {
173 	while (ppd->vaddr < ppd->vaddr_end) {
174 		sme_populate_pgd_large(ppd);
175 
176 		ppd->vaddr += PMD_PAGE_SIZE;
177 		ppd->paddr += PMD_PAGE_SIZE;
178 	}
179 }
180 
181 static void __init __sme_map_range_pte(struct sme_populate_pgd_data *ppd)
182 {
183 	while (ppd->vaddr < ppd->vaddr_end) {
184 		sme_populate_pgd(ppd);
185 
186 		ppd->vaddr += PAGE_SIZE;
187 		ppd->paddr += PAGE_SIZE;
188 	}
189 }
190 
191 static void __init __sme_map_range(struct sme_populate_pgd_data *ppd,
192 				   pmdval_t pmd_flags, pteval_t pte_flags)
193 {
194 	unsigned long vaddr_end;
195 
196 	ppd->pmd_flags = pmd_flags;
197 	ppd->pte_flags = pte_flags;
198 
199 	/* Save original end value since we modify the struct value */
200 	vaddr_end = ppd->vaddr_end;
201 
202 	/* If start is not 2MB aligned, create PTE entries */
203 	ppd->vaddr_end = ALIGN(ppd->vaddr, PMD_PAGE_SIZE);
204 	__sme_map_range_pte(ppd);
205 
206 	/* Create PMD entries */
207 	ppd->vaddr_end = vaddr_end & PMD_PAGE_MASK;
208 	__sme_map_range_pmd(ppd);
209 
210 	/* If end is not 2MB aligned, create PTE entries */
211 	ppd->vaddr_end = vaddr_end;
212 	__sme_map_range_pte(ppd);
213 }
214 
215 static void __init sme_map_range_encrypted(struct sme_populate_pgd_data *ppd)
216 {
217 	__sme_map_range(ppd, PMD_FLAGS_ENC, PTE_FLAGS_ENC);
218 }
219 
220 static void __init sme_map_range_decrypted(struct sme_populate_pgd_data *ppd)
221 {
222 	__sme_map_range(ppd, PMD_FLAGS_DEC, PTE_FLAGS_DEC);
223 }
224 
225 static void __init sme_map_range_decrypted_wp(struct sme_populate_pgd_data *ppd)
226 {
227 	__sme_map_range(ppd, PMD_FLAGS_DEC_WP, PTE_FLAGS_DEC_WP);
228 }
229 
230 static unsigned long __init sme_pgtable_calc(unsigned long len)
231 {
232 	unsigned long entries = 0, tables = 0;
233 
234 	/*
235 	 * Perform a relatively simplistic calculation of the pagetable
236 	 * entries that are needed. Those mappings will be covered mostly
237 	 * by 2MB PMD entries so we can conservatively calculate the required
238 	 * number of P4D, PUD and PMD structures needed to perform the
239 	 * mappings.  For mappings that are not 2MB aligned, PTE mappings
240 	 * would be needed for the start and end portion of the address range
241 	 * that fall outside of the 2MB alignment.  This results in, at most,
242 	 * two extra pages to hold PTE entries for each range that is mapped.
243 	 * Incrementing the count for each covers the case where the addresses
244 	 * cross entries.
245 	 */
246 
247 	/* PGDIR_SIZE is equal to P4D_SIZE on 4-level machine. */
248 	if (PTRS_PER_P4D > 1)
249 		entries += (DIV_ROUND_UP(len, PGDIR_SIZE) + 1) * sizeof(p4d_t) * PTRS_PER_P4D;
250 	entries += (DIV_ROUND_UP(len, P4D_SIZE) + 1) * sizeof(pud_t) * PTRS_PER_PUD;
251 	entries += (DIV_ROUND_UP(len, PUD_SIZE) + 1) * sizeof(pmd_t) * PTRS_PER_PMD;
252 	entries += 2 * sizeof(pte_t) * PTRS_PER_PTE;
253 
254 	/*
255 	 * Now calculate the added pagetable structures needed to populate
256 	 * the new pagetables.
257 	 */
258 
259 	if (PTRS_PER_P4D > 1)
260 		tables += DIV_ROUND_UP(entries, PGDIR_SIZE) * sizeof(p4d_t) * PTRS_PER_P4D;
261 	tables += DIV_ROUND_UP(entries, P4D_SIZE) * sizeof(pud_t) * PTRS_PER_PUD;
262 	tables += DIV_ROUND_UP(entries, PUD_SIZE) * sizeof(pmd_t) * PTRS_PER_PMD;
263 
264 	return entries + tables;
265 }
266 
267 void __init sme_encrypt_kernel(struct boot_params *bp)
268 {
269 	unsigned long workarea_start, workarea_end, workarea_len;
270 	unsigned long execute_start, execute_end, execute_len;
271 	unsigned long kernel_start, kernel_end, kernel_len;
272 	unsigned long initrd_start, initrd_end, initrd_len;
273 	struct sme_populate_pgd_data ppd;
274 	unsigned long pgtable_area_len;
275 	unsigned long decrypted_base;
276 
277 	if (!sme_active())
278 		return;
279 
280 	/*
281 	 * Prepare for encrypting the kernel and initrd by building new
282 	 * pagetables with the necessary attributes needed to encrypt the
283 	 * kernel in place.
284 	 *
285 	 *   One range of virtual addresses will map the memory occupied
286 	 *   by the kernel and initrd as encrypted.
287 	 *
288 	 *   Another range of virtual addresses will map the memory occupied
289 	 *   by the kernel and initrd as decrypted and write-protected.
290 	 *
291 	 *     The use of write-protect attribute will prevent any of the
292 	 *     memory from being cached.
293 	 */
294 
295 	/* Physical addresses gives us the identity mapped virtual addresses */
296 	kernel_start = __pa_symbol(_text);
297 	kernel_end = ALIGN(__pa_symbol(_end), PMD_PAGE_SIZE);
298 	kernel_len = kernel_end - kernel_start;
299 
300 	initrd_start = 0;
301 	initrd_end = 0;
302 	initrd_len = 0;
303 #ifdef CONFIG_BLK_DEV_INITRD
304 	initrd_len = (unsigned long)bp->hdr.ramdisk_size |
305 		     ((unsigned long)bp->ext_ramdisk_size << 32);
306 	if (initrd_len) {
307 		initrd_start = (unsigned long)bp->hdr.ramdisk_image |
308 			       ((unsigned long)bp->ext_ramdisk_image << 32);
309 		initrd_end = PAGE_ALIGN(initrd_start + initrd_len);
310 		initrd_len = initrd_end - initrd_start;
311 	}
312 #endif
313 
314 	/* Set the encryption workarea to be immediately after the kernel */
315 	workarea_start = kernel_end;
316 
317 	/*
318 	 * Calculate required number of workarea bytes needed:
319 	 *   executable encryption area size:
320 	 *     stack page (PAGE_SIZE)
321 	 *     encryption routine page (PAGE_SIZE)
322 	 *     intermediate copy buffer (PMD_PAGE_SIZE)
323 	 *   pagetable structures for the encryption of the kernel
324 	 *   pagetable structures for workarea (in case not currently mapped)
325 	 */
326 	execute_start = workarea_start;
327 	execute_end = execute_start + (PAGE_SIZE * 2) + PMD_PAGE_SIZE;
328 	execute_len = execute_end - execute_start;
329 
330 	/*
331 	 * One PGD for both encrypted and decrypted mappings and a set of
332 	 * PUDs and PMDs for each of the encrypted and decrypted mappings.
333 	 */
334 	pgtable_area_len = sizeof(pgd_t) * PTRS_PER_PGD;
335 	pgtable_area_len += sme_pgtable_calc(execute_end - kernel_start) * 2;
336 	if (initrd_len)
337 		pgtable_area_len += sme_pgtable_calc(initrd_len) * 2;
338 
339 	/* PUDs and PMDs needed in the current pagetables for the workarea */
340 	pgtable_area_len += sme_pgtable_calc(execute_len + pgtable_area_len);
341 
342 	/*
343 	 * The total workarea includes the executable encryption area and
344 	 * the pagetable area. The start of the workarea is already 2MB
345 	 * aligned, align the end of the workarea on a 2MB boundary so that
346 	 * we don't try to create/allocate PTE entries from the workarea
347 	 * before it is mapped.
348 	 */
349 	workarea_len = execute_len + pgtable_area_len;
350 	workarea_end = ALIGN(workarea_start + workarea_len, PMD_PAGE_SIZE);
351 
352 	/*
353 	 * Set the address to the start of where newly created pagetable
354 	 * structures (PGDs, PUDs and PMDs) will be allocated. New pagetable
355 	 * structures are created when the workarea is added to the current
356 	 * pagetables and when the new encrypted and decrypted kernel
357 	 * mappings are populated.
358 	 */
359 	ppd.pgtable_area = (void *)execute_end;
360 
361 	/*
362 	 * Make sure the current pagetable structure has entries for
363 	 * addressing the workarea.
364 	 */
365 	ppd.pgd = (pgd_t *)native_read_cr3_pa();
366 	ppd.paddr = workarea_start;
367 	ppd.vaddr = workarea_start;
368 	ppd.vaddr_end = workarea_end;
369 	sme_map_range_decrypted(&ppd);
370 
371 	/* Flush the TLB - no globals so cr3 is enough */
372 	native_write_cr3(__native_read_cr3());
373 
374 	/*
375 	 * A new pagetable structure is being built to allow for the kernel
376 	 * and initrd to be encrypted. It starts with an empty PGD that will
377 	 * then be populated with new PUDs and PMDs as the encrypted and
378 	 * decrypted kernel mappings are created.
379 	 */
380 	ppd.pgd = ppd.pgtable_area;
381 	memset(ppd.pgd, 0, sizeof(pgd_t) * PTRS_PER_PGD);
382 	ppd.pgtable_area += sizeof(pgd_t) * PTRS_PER_PGD;
383 
384 	/*
385 	 * A different PGD index/entry must be used to get different
386 	 * pagetable entries for the decrypted mapping. Choose the next
387 	 * PGD index and convert it to a virtual address to be used as
388 	 * the base of the mapping.
389 	 */
390 	decrypted_base = (pgd_index(workarea_end) + 1) & (PTRS_PER_PGD - 1);
391 	if (initrd_len) {
392 		unsigned long check_base;
393 
394 		check_base = (pgd_index(initrd_end) + 1) & (PTRS_PER_PGD - 1);
395 		decrypted_base = max(decrypted_base, check_base);
396 	}
397 	decrypted_base <<= PGDIR_SHIFT;
398 
399 	/* Add encrypted kernel (identity) mappings */
400 	ppd.paddr = kernel_start;
401 	ppd.vaddr = kernel_start;
402 	ppd.vaddr_end = kernel_end;
403 	sme_map_range_encrypted(&ppd);
404 
405 	/* Add decrypted, write-protected kernel (non-identity) mappings */
406 	ppd.paddr = kernel_start;
407 	ppd.vaddr = kernel_start + decrypted_base;
408 	ppd.vaddr_end = kernel_end + decrypted_base;
409 	sme_map_range_decrypted_wp(&ppd);
410 
411 	if (initrd_len) {
412 		/* Add encrypted initrd (identity) mappings */
413 		ppd.paddr = initrd_start;
414 		ppd.vaddr = initrd_start;
415 		ppd.vaddr_end = initrd_end;
416 		sme_map_range_encrypted(&ppd);
417 		/*
418 		 * Add decrypted, write-protected initrd (non-identity) mappings
419 		 */
420 		ppd.paddr = initrd_start;
421 		ppd.vaddr = initrd_start + decrypted_base;
422 		ppd.vaddr_end = initrd_end + decrypted_base;
423 		sme_map_range_decrypted_wp(&ppd);
424 	}
425 
426 	/* Add decrypted workarea mappings to both kernel mappings */
427 	ppd.paddr = workarea_start;
428 	ppd.vaddr = workarea_start;
429 	ppd.vaddr_end = workarea_end;
430 	sme_map_range_decrypted(&ppd);
431 
432 	ppd.paddr = workarea_start;
433 	ppd.vaddr = workarea_start + decrypted_base;
434 	ppd.vaddr_end = workarea_end + decrypted_base;
435 	sme_map_range_decrypted(&ppd);
436 
437 	/* Perform the encryption */
438 	sme_encrypt_execute(kernel_start, kernel_start + decrypted_base,
439 			    kernel_len, workarea_start, (unsigned long)ppd.pgd);
440 
441 	if (initrd_len)
442 		sme_encrypt_execute(initrd_start, initrd_start + decrypted_base,
443 				    initrd_len, workarea_start,
444 				    (unsigned long)ppd.pgd);
445 
446 	/*
447 	 * At this point we are running encrypted.  Remove the mappings for
448 	 * the decrypted areas - all that is needed for this is to remove
449 	 * the PGD entry/entries.
450 	 */
451 	ppd.vaddr = kernel_start + decrypted_base;
452 	ppd.vaddr_end = kernel_end + decrypted_base;
453 	sme_clear_pgd(&ppd);
454 
455 	if (initrd_len) {
456 		ppd.vaddr = initrd_start + decrypted_base;
457 		ppd.vaddr_end = initrd_end + decrypted_base;
458 		sme_clear_pgd(&ppd);
459 	}
460 
461 	ppd.vaddr = workarea_start + decrypted_base;
462 	ppd.vaddr_end = workarea_end + decrypted_base;
463 	sme_clear_pgd(&ppd);
464 
465 	/* Flush the TLB - no globals so cr3 is enough */
466 	native_write_cr3(__native_read_cr3());
467 }
468 
469 void __init sme_enable(struct boot_params *bp)
470 {
471 	const char *cmdline_ptr, *cmdline_arg, *cmdline_on, *cmdline_off;
472 	unsigned int eax, ebx, ecx, edx;
473 	unsigned long feature_mask;
474 	bool active_by_default;
475 	unsigned long me_mask;
476 	char buffer[16];
477 	u64 msr;
478 
479 	/* Check for the SME/SEV support leaf */
480 	eax = 0x80000000;
481 	ecx = 0;
482 	native_cpuid(&eax, &ebx, &ecx, &edx);
483 	if (eax < 0x8000001f)
484 		return;
485 
486 #define AMD_SME_BIT	BIT(0)
487 #define AMD_SEV_BIT	BIT(1)
488 	/*
489 	 * Set the feature mask (SME or SEV) based on whether we are
490 	 * running under a hypervisor.
491 	 */
492 	eax = 1;
493 	ecx = 0;
494 	native_cpuid(&eax, &ebx, &ecx, &edx);
495 	feature_mask = (ecx & BIT(31)) ? AMD_SEV_BIT : AMD_SME_BIT;
496 
497 	/*
498 	 * Check for the SME/SEV feature:
499 	 *   CPUID Fn8000_001F[EAX]
500 	 *   - Bit 0 - Secure Memory Encryption support
501 	 *   - Bit 1 - Secure Encrypted Virtualization support
502 	 *   CPUID Fn8000_001F[EBX]
503 	 *   - Bits 5:0 - Pagetable bit position used to indicate encryption
504 	 */
505 	eax = 0x8000001f;
506 	ecx = 0;
507 	native_cpuid(&eax, &ebx, &ecx, &edx);
508 	if (!(eax & feature_mask))
509 		return;
510 
511 	me_mask = 1UL << (ebx & 0x3f);
512 
513 	/* Check if memory encryption is enabled */
514 	if (feature_mask == AMD_SME_BIT) {
515 		/* For SME, check the SYSCFG MSR */
516 		msr = __rdmsr(MSR_K8_SYSCFG);
517 		if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
518 			return;
519 	} else {
520 		/* For SEV, check the SEV MSR */
521 		msr = __rdmsr(MSR_AMD64_SEV);
522 		if (!(msr & MSR_AMD64_SEV_ENABLED))
523 			return;
524 
525 		/* SEV state cannot be controlled by a command line option */
526 		sme_me_mask = me_mask;
527 		sev_enabled = true;
528 		physical_mask &= ~sme_me_mask;
529 		return;
530 	}
531 
532 	/*
533 	 * Fixups have not been applied to phys_base yet and we're running
534 	 * identity mapped, so we must obtain the address to the SME command
535 	 * line argument data using rip-relative addressing.
536 	 */
537 	asm ("lea sme_cmdline_arg(%%rip), %0"
538 	     : "=r" (cmdline_arg)
539 	     : "p" (sme_cmdline_arg));
540 	asm ("lea sme_cmdline_on(%%rip), %0"
541 	     : "=r" (cmdline_on)
542 	     : "p" (sme_cmdline_on));
543 	asm ("lea sme_cmdline_off(%%rip), %0"
544 	     : "=r" (cmdline_off)
545 	     : "p" (sme_cmdline_off));
546 
547 	if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT))
548 		active_by_default = true;
549 	else
550 		active_by_default = false;
551 
552 	cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr |
553 				     ((u64)bp->ext_cmd_line_ptr << 32));
554 
555 	cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer));
556 
557 	if (!strncmp(buffer, cmdline_on, sizeof(buffer)))
558 		sme_me_mask = me_mask;
559 	else if (!strncmp(buffer, cmdline_off, sizeof(buffer)))
560 		sme_me_mask = 0;
561 	else
562 		sme_me_mask = active_by_default ? me_mask : 0;
563 
564 	physical_mask &= ~sme_me_mask;
565 }
566