1 #include <linux/gfp.h> 2 #include <linux/initrd.h> 3 #include <linux/ioport.h> 4 #include <linux/swap.h> 5 #include <linux/memblock.h> 6 #include <linux/swapfile.h> 7 #include <linux/swapops.h> 8 #include <linux/kmemleak.h> 9 #include <linux/sched/task.h> 10 #include <linux/execmem.h> 11 12 #include <asm/set_memory.h> 13 #include <asm/cpu_device_id.h> 14 #include <asm/e820/api.h> 15 #include <asm/init.h> 16 #include <asm/page.h> 17 #include <asm/page_types.h> 18 #include <asm/sections.h> 19 #include <asm/setup.h> 20 #include <asm/tlbflush.h> 21 #include <asm/tlb.h> 22 #include <asm/proto.h> 23 #include <asm/dma.h> /* for MAX_DMA_PFN */ 24 #include <asm/kaslr.h> 25 #include <asm/hypervisor.h> 26 #include <asm/cpufeature.h> 27 #include <asm/pti.h> 28 #include <asm/text-patching.h> 29 #include <asm/memtype.h> 30 #include <asm/paravirt.h> 31 #include <asm/mmu_context.h> 32 33 /* 34 * We need to define the tracepoints somewhere, and tlb.c 35 * is only compiled when SMP=y. 36 */ 37 #include <trace/events/tlb.h> 38 39 #include "mm_internal.h" 40 41 /* 42 * Tables translating between page_cache_type_t and pte encoding. 43 * 44 * The default values are defined statically as minimal supported mode; 45 * WC and WT fall back to UC-. pat_init() updates these values to support 46 * more cache modes, WC and WT, when it is safe to do so. See pat_init() 47 * for the details. Note, __early_ioremap() used during early boot-time 48 * takes pgprot_t (pte encoding) and does not use these tables. 49 * 50 * Index into __cachemode2pte_tbl[] is the cachemode. 51 * 52 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte 53 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2. 54 */ 55 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = { 56 [_PAGE_CACHE_MODE_WB ] = 0 | 0 , 57 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD, 58 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD, 59 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD, 60 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD, 61 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD, 62 }; 63 64 unsigned long cachemode2protval(enum page_cache_mode pcm) 65 { 66 if (likely(pcm == 0)) 67 return 0; 68 return __cachemode2pte_tbl[pcm]; 69 } 70 EXPORT_SYMBOL(cachemode2protval); 71 72 static uint8_t __pte2cachemode_tbl[8] = { 73 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB, 74 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 75 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 76 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC, 77 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB, 78 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 79 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 80 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC, 81 }; 82 83 /* 84 * Check that the write-protect PAT entry is set for write-protect. 85 * To do this without making assumptions how PAT has been set up (Xen has 86 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache 87 * mode via the __cachemode2pte_tbl[] into protection bits (those protection 88 * bits will select a cache mode of WP or better), and then translate the 89 * protection bits back into the cache mode using __pte2cm_idx() and the 90 * __pte2cachemode_tbl[] array. This will return the really used cache mode. 91 */ 92 bool x86_has_pat_wp(void) 93 { 94 uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]; 95 96 return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP; 97 } 98 99 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) 100 { 101 unsigned long masked; 102 103 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK; 104 if (likely(masked == 0)) 105 return 0; 106 return __pte2cachemode_tbl[__pte2cm_idx(masked)]; 107 } 108 109 static unsigned long __initdata pgt_buf_start; 110 static unsigned long __initdata pgt_buf_end; 111 static unsigned long __initdata pgt_buf_top; 112 113 static unsigned long min_pfn_mapped; 114 115 static bool __initdata can_use_brk_pgt = true; 116 117 /* 118 * Pages returned are already directly mapped. 119 * 120 * Changing that is likely to break Xen, see commit: 121 * 122 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve 123 * 124 * for detailed information. 125 */ 126 __ref void *alloc_low_pages(unsigned int num) 127 { 128 unsigned long pfn; 129 int i; 130 131 if (after_bootmem) { 132 unsigned int order; 133 134 order = get_order((unsigned long)num << PAGE_SHIFT); 135 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 136 } 137 138 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) { 139 unsigned long ret = 0; 140 141 if (min_pfn_mapped < max_pfn_mapped) { 142 ret = memblock_phys_alloc_range( 143 PAGE_SIZE * num, PAGE_SIZE, 144 min_pfn_mapped << PAGE_SHIFT, 145 max_pfn_mapped << PAGE_SHIFT); 146 } 147 if (!ret && can_use_brk_pgt) 148 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE)); 149 150 if (!ret) 151 panic("alloc_low_pages: can not alloc memory"); 152 153 pfn = ret >> PAGE_SHIFT; 154 } else { 155 pfn = pgt_buf_end; 156 pgt_buf_end += num; 157 } 158 159 for (i = 0; i < num; i++) { 160 void *adr; 161 162 adr = __va((pfn + i) << PAGE_SHIFT); 163 clear_page(adr); 164 } 165 166 return __va(pfn << PAGE_SHIFT); 167 } 168 169 /* 170 * By default need to be able to allocate page tables below PGD firstly for 171 * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping. 172 * With KASLR memory randomization, depending on the machine e820 memory and the 173 * PUD alignment, twice that many pages may be needed when KASLR memory 174 * randomization is enabled. 175 */ 176 177 #ifndef CONFIG_X86_5LEVEL 178 #define INIT_PGD_PAGE_TABLES 3 179 #else 180 #define INIT_PGD_PAGE_TABLES 4 181 #endif 182 183 #ifndef CONFIG_RANDOMIZE_MEMORY 184 #define INIT_PGD_PAGE_COUNT (2 * INIT_PGD_PAGE_TABLES) 185 #else 186 #define INIT_PGD_PAGE_COUNT (4 * INIT_PGD_PAGE_TABLES) 187 #endif 188 189 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE) 190 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE); 191 void __init early_alloc_pgt_buf(void) 192 { 193 unsigned long tables = INIT_PGT_BUF_SIZE; 194 phys_addr_t base; 195 196 base = __pa(extend_brk(tables, PAGE_SIZE)); 197 198 pgt_buf_start = base >> PAGE_SHIFT; 199 pgt_buf_end = pgt_buf_start; 200 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT); 201 } 202 203 int after_bootmem; 204 205 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES); 206 207 struct map_range { 208 unsigned long start; 209 unsigned long end; 210 unsigned page_size_mask; 211 }; 212 213 static int page_size_mask; 214 215 /* 216 * Save some of cr4 feature set we're using (e.g. Pentium 4MB 217 * enable and PPro Global page enable), so that any CPU's that boot 218 * up after us can get the correct flags. Invoked on the boot CPU. 219 */ 220 static inline void cr4_set_bits_and_update_boot(unsigned long mask) 221 { 222 mmu_cr4_features |= mask; 223 if (trampoline_cr4_features) 224 *trampoline_cr4_features = mmu_cr4_features; 225 cr4_set_bits(mask); 226 } 227 228 static void __init probe_page_size_mask(void) 229 { 230 /* 231 * For pagealloc debugging, identity mapping will use small pages. 232 * This will simplify cpa(), which otherwise needs to support splitting 233 * large pages into small in interrupt context, etc. 234 */ 235 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled()) 236 page_size_mask |= 1 << PG_LEVEL_2M; 237 else 238 direct_gbpages = 0; 239 240 /* Enable PSE if available */ 241 if (boot_cpu_has(X86_FEATURE_PSE)) 242 cr4_set_bits_and_update_boot(X86_CR4_PSE); 243 244 /* Enable PGE if available */ 245 __supported_pte_mask &= ~_PAGE_GLOBAL; 246 if (boot_cpu_has(X86_FEATURE_PGE)) { 247 cr4_set_bits_and_update_boot(X86_CR4_PGE); 248 __supported_pte_mask |= _PAGE_GLOBAL; 249 } 250 251 /* By the default is everything supported: */ 252 __default_kernel_pte_mask = __supported_pte_mask; 253 /* Except when with PTI where the kernel is mostly non-Global: */ 254 if (cpu_feature_enabled(X86_FEATURE_PTI)) 255 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 256 257 /* Enable 1 GB linear kernel mappings if available: */ 258 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) { 259 printk(KERN_INFO "Using GB pages for direct mapping\n"); 260 page_size_mask |= 1 << PG_LEVEL_1G; 261 } else { 262 direct_gbpages = 0; 263 } 264 } 265 266 /* 267 * INVLPG may not properly flush Global entries on 268 * these CPUs. New microcode fixes the issue. 269 */ 270 static const struct x86_cpu_id invlpg_miss_ids[] = { 271 X86_MATCH_VFM(INTEL_ALDERLAKE, 0x2e), 272 X86_MATCH_VFM(INTEL_ALDERLAKE_L, 0x42c), 273 X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, 0x11), 274 X86_MATCH_VFM(INTEL_RAPTORLAKE, 0x118), 275 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, 0x4117), 276 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, 0x2e), 277 {} 278 }; 279 280 static void setup_pcid(void) 281 { 282 const struct x86_cpu_id *invlpg_miss_match; 283 284 if (!IS_ENABLED(CONFIG_X86_64)) 285 return; 286 287 if (!boot_cpu_has(X86_FEATURE_PCID)) 288 return; 289 290 invlpg_miss_match = x86_match_cpu(invlpg_miss_ids); 291 292 if (invlpg_miss_match && 293 boot_cpu_data.microcode < invlpg_miss_match->driver_data) { 294 pr_info("Incomplete global flushes, disabling PCID"); 295 setup_clear_cpu_cap(X86_FEATURE_PCID); 296 return; 297 } 298 299 if (boot_cpu_has(X86_FEATURE_PGE)) { 300 /* 301 * This can't be cr4_set_bits_and_update_boot() -- the 302 * trampoline code can't handle CR4.PCIDE and it wouldn't 303 * do any good anyway. Despite the name, 304 * cr4_set_bits_and_update_boot() doesn't actually cause 305 * the bits in question to remain set all the way through 306 * the secondary boot asm. 307 * 308 * Instead, we brute-force it and set CR4.PCIDE manually in 309 * start_secondary(). 310 */ 311 cr4_set_bits(X86_CR4_PCIDE); 312 } else { 313 /* 314 * flush_tlb_all(), as currently implemented, won't work if 315 * PCID is on but PGE is not. Since that combination 316 * doesn't exist on real hardware, there's no reason to try 317 * to fully support it, but it's polite to avoid corrupting 318 * data if we're on an improperly configured VM. 319 */ 320 setup_clear_cpu_cap(X86_FEATURE_PCID); 321 } 322 } 323 324 #ifdef CONFIG_X86_32 325 #define NR_RANGE_MR 3 326 #else /* CONFIG_X86_64 */ 327 #define NR_RANGE_MR 5 328 #endif 329 330 static int __meminit save_mr(struct map_range *mr, int nr_range, 331 unsigned long start_pfn, unsigned long end_pfn, 332 unsigned long page_size_mask) 333 { 334 if (start_pfn < end_pfn) { 335 if (nr_range >= NR_RANGE_MR) 336 panic("run out of range for init_memory_mapping\n"); 337 mr[nr_range].start = start_pfn<<PAGE_SHIFT; 338 mr[nr_range].end = end_pfn<<PAGE_SHIFT; 339 mr[nr_range].page_size_mask = page_size_mask; 340 nr_range++; 341 } 342 343 return nr_range; 344 } 345 346 /* 347 * adjust the page_size_mask for small range to go with 348 * big page size instead small one if nearby are ram too. 349 */ 350 static void __ref adjust_range_page_size_mask(struct map_range *mr, 351 int nr_range) 352 { 353 int i; 354 355 for (i = 0; i < nr_range; i++) { 356 if ((page_size_mask & (1<<PG_LEVEL_2M)) && 357 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) { 358 unsigned long start = round_down(mr[i].start, PMD_SIZE); 359 unsigned long end = round_up(mr[i].end, PMD_SIZE); 360 361 #ifdef CONFIG_X86_32 362 if ((end >> PAGE_SHIFT) > max_low_pfn) 363 continue; 364 #endif 365 366 if (memblock_is_region_memory(start, end - start)) 367 mr[i].page_size_mask |= 1<<PG_LEVEL_2M; 368 } 369 if ((page_size_mask & (1<<PG_LEVEL_1G)) && 370 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) { 371 unsigned long start = round_down(mr[i].start, PUD_SIZE); 372 unsigned long end = round_up(mr[i].end, PUD_SIZE); 373 374 if (memblock_is_region_memory(start, end - start)) 375 mr[i].page_size_mask |= 1<<PG_LEVEL_1G; 376 } 377 } 378 } 379 380 static const char *page_size_string(struct map_range *mr) 381 { 382 static const char str_1g[] = "1G"; 383 static const char str_2m[] = "2M"; 384 static const char str_4m[] = "4M"; 385 static const char str_4k[] = "4k"; 386 387 if (mr->page_size_mask & (1<<PG_LEVEL_1G)) 388 return str_1g; 389 /* 390 * 32-bit without PAE has a 4M large page size. 391 * PG_LEVEL_2M is misnamed, but we can at least 392 * print out the right size in the string. 393 */ 394 if (IS_ENABLED(CONFIG_X86_32) && 395 !IS_ENABLED(CONFIG_X86_PAE) && 396 mr->page_size_mask & (1<<PG_LEVEL_2M)) 397 return str_4m; 398 399 if (mr->page_size_mask & (1<<PG_LEVEL_2M)) 400 return str_2m; 401 402 return str_4k; 403 } 404 405 static int __meminit split_mem_range(struct map_range *mr, int nr_range, 406 unsigned long start, 407 unsigned long end) 408 { 409 unsigned long start_pfn, end_pfn, limit_pfn; 410 unsigned long pfn; 411 int i; 412 413 limit_pfn = PFN_DOWN(end); 414 415 /* head if not big page alignment ? */ 416 pfn = start_pfn = PFN_DOWN(start); 417 #ifdef CONFIG_X86_32 418 /* 419 * Don't use a large page for the first 2/4MB of memory 420 * because there are often fixed size MTRRs in there 421 * and overlapping MTRRs into large pages can cause 422 * slowdowns. 423 */ 424 if (pfn == 0) 425 end_pfn = PFN_DOWN(PMD_SIZE); 426 else 427 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 428 #else /* CONFIG_X86_64 */ 429 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 430 #endif 431 if (end_pfn > limit_pfn) 432 end_pfn = limit_pfn; 433 if (start_pfn < end_pfn) { 434 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 435 pfn = end_pfn; 436 } 437 438 /* big page (2M) range */ 439 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 440 #ifdef CONFIG_X86_32 441 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 442 #else /* CONFIG_X86_64 */ 443 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 444 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE))) 445 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 446 #endif 447 448 if (start_pfn < end_pfn) { 449 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 450 page_size_mask & (1<<PG_LEVEL_2M)); 451 pfn = end_pfn; 452 } 453 454 #ifdef CONFIG_X86_64 455 /* big page (1G) range */ 456 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 457 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE)); 458 if (start_pfn < end_pfn) { 459 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 460 page_size_mask & 461 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); 462 pfn = end_pfn; 463 } 464 465 /* tail is not big page (1G) alignment */ 466 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 467 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 468 if (start_pfn < end_pfn) { 469 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 470 page_size_mask & (1<<PG_LEVEL_2M)); 471 pfn = end_pfn; 472 } 473 #endif 474 475 /* tail is not big page (2M) alignment */ 476 start_pfn = pfn; 477 end_pfn = limit_pfn; 478 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 479 480 if (!after_bootmem) 481 adjust_range_page_size_mask(mr, nr_range); 482 483 /* try to merge same page size and continuous */ 484 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { 485 unsigned long old_start; 486 if (mr[i].end != mr[i+1].start || 487 mr[i].page_size_mask != mr[i+1].page_size_mask) 488 continue; 489 /* move it */ 490 old_start = mr[i].start; 491 memmove(&mr[i], &mr[i+1], 492 (nr_range - 1 - i) * sizeof(struct map_range)); 493 mr[i--].start = old_start; 494 nr_range--; 495 } 496 497 for (i = 0; i < nr_range; i++) 498 pr_debug(" [mem %#010lx-%#010lx] page %s\n", 499 mr[i].start, mr[i].end - 1, 500 page_size_string(&mr[i])); 501 502 return nr_range; 503 } 504 505 struct range pfn_mapped[E820_MAX_ENTRIES]; 506 int nr_pfn_mapped; 507 508 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn) 509 { 510 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES, 511 nr_pfn_mapped, start_pfn, end_pfn); 512 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES); 513 514 max_pfn_mapped = max(max_pfn_mapped, end_pfn); 515 516 if (start_pfn < (1UL<<(32-PAGE_SHIFT))) 517 max_low_pfn_mapped = max(max_low_pfn_mapped, 518 min(end_pfn, 1UL<<(32-PAGE_SHIFT))); 519 } 520 521 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn) 522 { 523 int i; 524 525 for (i = 0; i < nr_pfn_mapped; i++) 526 if ((start_pfn >= pfn_mapped[i].start) && 527 (end_pfn <= pfn_mapped[i].end)) 528 return true; 529 530 return false; 531 } 532 533 /* 534 * Setup the direct mapping of the physical memory at PAGE_OFFSET. 535 * This runs before bootmem is initialized and gets pages directly from 536 * the physical memory. To access them they are temporarily mapped. 537 */ 538 unsigned long __ref init_memory_mapping(unsigned long start, 539 unsigned long end, pgprot_t prot) 540 { 541 struct map_range mr[NR_RANGE_MR]; 542 unsigned long ret = 0; 543 int nr_range, i; 544 545 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n", 546 start, end - 1); 547 548 memset(mr, 0, sizeof(mr)); 549 nr_range = split_mem_range(mr, 0, start, end); 550 551 for (i = 0; i < nr_range; i++) 552 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end, 553 mr[i].page_size_mask, 554 prot); 555 556 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT); 557 558 return ret >> PAGE_SHIFT; 559 } 560 561 /* 562 * We need to iterate through the E820 memory map and create direct mappings 563 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply 564 * create direct mappings for all pfns from [0 to max_low_pfn) and 565 * [4GB to max_pfn) because of possible memory holes in high addresses 566 * that cannot be marked as UC by fixed/variable range MTRRs. 567 * Depending on the alignment of E820 ranges, this may possibly result 568 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables. 569 * 570 * init_mem_mapping() calls init_range_memory_mapping() with big range. 571 * That range would have hole in the middle or ends, and only ram parts 572 * will be mapped in init_range_memory_mapping(). 573 */ 574 static unsigned long __init init_range_memory_mapping( 575 unsigned long r_start, 576 unsigned long r_end) 577 { 578 unsigned long start_pfn, end_pfn; 579 unsigned long mapped_ram_size = 0; 580 int i; 581 582 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 583 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end); 584 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end); 585 if (start >= end) 586 continue; 587 588 /* 589 * if it is overlapping with brk pgt, we need to 590 * alloc pgt buf from memblock instead. 591 */ 592 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >= 593 min(end, (u64)pgt_buf_top<<PAGE_SHIFT); 594 init_memory_mapping(start, end, PAGE_KERNEL); 595 mapped_ram_size += end - start; 596 can_use_brk_pgt = true; 597 } 598 599 return mapped_ram_size; 600 } 601 602 static unsigned long __init get_new_step_size(unsigned long step_size) 603 { 604 /* 605 * Initial mapped size is PMD_SIZE (2M). 606 * We can not set step_size to be PUD_SIZE (1G) yet. 607 * In worse case, when we cross the 1G boundary, and 608 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k) 609 * to map 1G range with PTE. Hence we use one less than the 610 * difference of page table level shifts. 611 * 612 * Don't need to worry about overflow in the top-down case, on 32bit, 613 * when step_size is 0, round_down() returns 0 for start, and that 614 * turns it into 0x100000000ULL. 615 * In the bottom-up case, round_up(x, 0) returns 0 though too, which 616 * needs to be taken into consideration by the code below. 617 */ 618 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1); 619 } 620 621 /** 622 * memory_map_top_down - Map [map_start, map_end) top down 623 * @map_start: start address of the target memory range 624 * @map_end: end address of the target memory range 625 * 626 * This function will setup direct mapping for memory range 627 * [map_start, map_end) in top-down. That said, the page tables 628 * will be allocated at the end of the memory, and we map the 629 * memory in top-down. 630 */ 631 static void __init memory_map_top_down(unsigned long map_start, 632 unsigned long map_end) 633 { 634 unsigned long real_end, last_start; 635 unsigned long step_size; 636 unsigned long addr; 637 unsigned long mapped_ram_size = 0; 638 639 /* 640 * Systems that have many reserved areas near top of the memory, 641 * e.g. QEMU with less than 1G RAM and EFI enabled, or Xen, will 642 * require lots of 4K mappings which may exhaust pgt_buf. 643 * Start with top-most PMD_SIZE range aligned at PMD_SIZE to ensure 644 * there is enough mapped memory that can be allocated from 645 * memblock. 646 */ 647 addr = memblock_phys_alloc_range(PMD_SIZE, PMD_SIZE, map_start, 648 map_end); 649 if (!addr) { 650 pr_warn("Failed to release memory for alloc_low_pages()"); 651 real_end = max(map_start, ALIGN_DOWN(map_end, PMD_SIZE)); 652 } else { 653 memblock_phys_free(addr, PMD_SIZE); 654 real_end = addr + PMD_SIZE; 655 } 656 657 /* step_size need to be small so pgt_buf from BRK could cover it */ 658 step_size = PMD_SIZE; 659 max_pfn_mapped = 0; /* will get exact value next */ 660 min_pfn_mapped = real_end >> PAGE_SHIFT; 661 last_start = real_end; 662 663 /* 664 * We start from the top (end of memory) and go to the bottom. 665 * The memblock_find_in_range() gets us a block of RAM from the 666 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 667 * for page table. 668 */ 669 while (last_start > map_start) { 670 unsigned long start; 671 672 if (last_start > step_size) { 673 start = round_down(last_start - 1, step_size); 674 if (start < map_start) 675 start = map_start; 676 } else 677 start = map_start; 678 mapped_ram_size += init_range_memory_mapping(start, 679 last_start); 680 last_start = start; 681 min_pfn_mapped = last_start >> PAGE_SHIFT; 682 if (mapped_ram_size >= step_size) 683 step_size = get_new_step_size(step_size); 684 } 685 686 if (real_end < map_end) 687 init_range_memory_mapping(real_end, map_end); 688 } 689 690 /** 691 * memory_map_bottom_up - Map [map_start, map_end) bottom up 692 * @map_start: start address of the target memory range 693 * @map_end: end address of the target memory range 694 * 695 * This function will setup direct mapping for memory range 696 * [map_start, map_end) in bottom-up. Since we have limited the 697 * bottom-up allocation above the kernel, the page tables will 698 * be allocated just above the kernel and we map the memory 699 * in [map_start, map_end) in bottom-up. 700 */ 701 static void __init memory_map_bottom_up(unsigned long map_start, 702 unsigned long map_end) 703 { 704 unsigned long next, start; 705 unsigned long mapped_ram_size = 0; 706 /* step_size need to be small so pgt_buf from BRK could cover it */ 707 unsigned long step_size = PMD_SIZE; 708 709 start = map_start; 710 min_pfn_mapped = start >> PAGE_SHIFT; 711 712 /* 713 * We start from the bottom (@map_start) and go to the top (@map_end). 714 * The memblock_find_in_range() gets us a block of RAM from the 715 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 716 * for page table. 717 */ 718 while (start < map_end) { 719 if (step_size && map_end - start > step_size) { 720 next = round_up(start + 1, step_size); 721 if (next > map_end) 722 next = map_end; 723 } else { 724 next = map_end; 725 } 726 727 mapped_ram_size += init_range_memory_mapping(start, next); 728 start = next; 729 730 if (mapped_ram_size >= step_size) 731 step_size = get_new_step_size(step_size); 732 } 733 } 734 735 /* 736 * The real mode trampoline, which is required for bootstrapping CPUs 737 * occupies only a small area under the low 1MB. See reserve_real_mode() 738 * for details. 739 * 740 * If KASLR is disabled the first PGD entry of the direct mapping is copied 741 * to map the real mode trampoline. 742 * 743 * If KASLR is enabled, copy only the PUD which covers the low 1MB 744 * area. This limits the randomization granularity to 1GB for both 4-level 745 * and 5-level paging. 746 */ 747 static void __init init_trampoline(void) 748 { 749 #ifdef CONFIG_X86_64 750 /* 751 * The code below will alias kernel page-tables in the user-range of the 752 * address space, including the Global bit. So global TLB entries will 753 * be created when using the trampoline page-table. 754 */ 755 if (!kaslr_memory_enabled()) 756 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)]; 757 else 758 init_trampoline_kaslr(); 759 #endif 760 } 761 762 void __init init_mem_mapping(void) 763 { 764 unsigned long end; 765 766 pti_check_boottime_disable(); 767 probe_page_size_mask(); 768 setup_pcid(); 769 770 #ifdef CONFIG_X86_64 771 end = max_pfn << PAGE_SHIFT; 772 #else 773 end = max_low_pfn << PAGE_SHIFT; 774 #endif 775 776 /* the ISA range is always mapped regardless of memory holes */ 777 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL); 778 779 /* Init the trampoline, possibly with KASLR memory offset */ 780 init_trampoline(); 781 782 /* 783 * If the allocation is in bottom-up direction, we setup direct mapping 784 * in bottom-up, otherwise we setup direct mapping in top-down. 785 */ 786 if (memblock_bottom_up()) { 787 unsigned long kernel_end = __pa_symbol(_end); 788 789 /* 790 * we need two separate calls here. This is because we want to 791 * allocate page tables above the kernel. So we first map 792 * [kernel_end, end) to make memory above the kernel be mapped 793 * as soon as possible. And then use page tables allocated above 794 * the kernel to map [ISA_END_ADDRESS, kernel_end). 795 */ 796 memory_map_bottom_up(kernel_end, end); 797 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end); 798 } else { 799 memory_map_top_down(ISA_END_ADDRESS, end); 800 } 801 802 #ifdef CONFIG_X86_64 803 if (max_pfn > max_low_pfn) { 804 /* can we preserve max_low_pfn ?*/ 805 max_low_pfn = max_pfn; 806 } 807 #else 808 early_ioremap_page_table_range_init(); 809 #endif 810 811 load_cr3(swapper_pg_dir); 812 __flush_tlb_all(); 813 814 x86_init.hyper.init_mem_mapping(); 815 816 early_memtest(0, max_pfn_mapped << PAGE_SHIFT); 817 } 818 819 /* 820 * Initialize an mm_struct to be used during poking and a pointer to be used 821 * during patching. 822 */ 823 void __init poking_init(void) 824 { 825 spinlock_t *ptl; 826 pte_t *ptep; 827 828 text_poke_mm = mm_alloc(); 829 BUG_ON(!text_poke_mm); 830 831 /* Xen PV guests need the PGD to be pinned. */ 832 paravirt_enter_mmap(text_poke_mm); 833 834 set_notrack_mm(text_poke_mm); 835 836 /* 837 * Randomize the poking address, but make sure that the following page 838 * will be mapped at the same PMD. We need 2 pages, so find space for 3, 839 * and adjust the address if the PMD ends after the first one. 840 */ 841 text_poke_mm_addr = TASK_UNMAPPED_BASE; 842 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 843 text_poke_mm_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) % 844 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE); 845 846 if (((text_poke_mm_addr + PAGE_SIZE) & ~PMD_MASK) == 0) 847 text_poke_mm_addr += PAGE_SIZE; 848 849 /* 850 * We need to trigger the allocation of the page-tables that will be 851 * needed for poking now. Later, poking may be performed in an atomic 852 * section, which might cause allocation to fail. 853 */ 854 ptep = get_locked_pte(text_poke_mm, text_poke_mm_addr, &ptl); 855 BUG_ON(!ptep); 856 pte_unmap_unlock(ptep, ptl); 857 } 858 859 /* 860 * devmem_is_allowed() checks to see if /dev/mem access to a certain address 861 * is valid. The argument is a physical page number. 862 * 863 * On x86, access has to be given to the first megabyte of RAM because that 864 * area traditionally contains BIOS code and data regions used by X, dosemu, 865 * and similar apps. Since they map the entire memory range, the whole range 866 * must be allowed (for mapping), but any areas that would otherwise be 867 * disallowed are flagged as being "zero filled" instead of rejected. 868 * Access has to be given to non-kernel-ram areas as well, these contain the 869 * PCI mmio resources as well as potential bios/acpi data regions. 870 */ 871 int devmem_is_allowed(unsigned long pagenr) 872 { 873 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE, 874 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE) 875 != REGION_DISJOINT) { 876 /* 877 * For disallowed memory regions in the low 1MB range, 878 * request that the page be shown as all zeros. 879 */ 880 if (pagenr < 256) 881 return 2; 882 883 return 0; 884 } 885 886 /* 887 * This must follow RAM test, since System RAM is considered a 888 * restricted resource under CONFIG_STRICT_DEVMEM. 889 */ 890 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) { 891 /* Low 1MB bypasses iomem restrictions. */ 892 if (pagenr < 256) 893 return 1; 894 895 return 0; 896 } 897 898 return 1; 899 } 900 901 void free_init_pages(const char *what, unsigned long begin, unsigned long end) 902 { 903 unsigned long begin_aligned, end_aligned; 904 905 /* Make sure boundaries are page aligned */ 906 begin_aligned = PAGE_ALIGN(begin); 907 end_aligned = end & PAGE_MASK; 908 909 if (WARN_ON(begin_aligned != begin || end_aligned != end)) { 910 begin = begin_aligned; 911 end = end_aligned; 912 } 913 914 if (begin >= end) 915 return; 916 917 /* 918 * If debugging page accesses then do not free this memory but 919 * mark them not present - any buggy init-section access will 920 * create a kernel page fault: 921 */ 922 if (debug_pagealloc_enabled()) { 923 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n", 924 begin, end - 1); 925 /* 926 * Inform kmemleak about the hole in the memory since the 927 * corresponding pages will be unmapped. 928 */ 929 kmemleak_free_part((void *)begin, end - begin); 930 set_memory_np(begin, (end - begin) >> PAGE_SHIFT); 931 } else { 932 /* 933 * We just marked the kernel text read only above, now that 934 * we are going to free part of that, we need to make that 935 * writeable and non-executable first. 936 */ 937 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT); 938 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT); 939 940 free_reserved_area((void *)begin, (void *)end, 941 POISON_FREE_INITMEM, what); 942 } 943 } 944 945 /* 946 * begin/end can be in the direct map or the "high kernel mapping" 947 * used for the kernel image only. free_init_pages() will do the 948 * right thing for either kind of address. 949 */ 950 void free_kernel_image_pages(const char *what, void *begin, void *end) 951 { 952 unsigned long begin_ul = (unsigned long)begin; 953 unsigned long end_ul = (unsigned long)end; 954 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT; 955 956 free_init_pages(what, begin_ul, end_ul); 957 958 /* 959 * PTI maps some of the kernel into userspace. For performance, 960 * this includes some kernel areas that do not contain secrets. 961 * Those areas might be adjacent to the parts of the kernel image 962 * being freed, which may contain secrets. Remove the "high kernel 963 * image mapping" for these freed areas, ensuring they are not even 964 * potentially vulnerable to Meltdown regardless of the specific 965 * optimizations PTI is currently using. 966 * 967 * The "noalias" prevents unmapping the direct map alias which is 968 * needed to access the freed pages. 969 * 970 * This is only valid for 64bit kernels. 32bit has only one mapping 971 * which can't be treated in this way for obvious reasons. 972 */ 973 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI)) 974 set_memory_np_noalias(begin_ul, len_pages); 975 } 976 977 void __ref free_initmem(void) 978 { 979 e820__reallocate_tables(); 980 981 mem_encrypt_free_decrypted_mem(); 982 983 free_kernel_image_pages("unused kernel image (initmem)", 984 &__init_begin, &__init_end); 985 } 986 987 #ifdef CONFIG_BLK_DEV_INITRD 988 void __init free_initrd_mem(unsigned long start, unsigned long end) 989 { 990 /* 991 * end could be not aligned, and We can not align that, 992 * decompressor could be confused by aligned initrd_end 993 * We already reserve the end partial page before in 994 * - i386_start_kernel() 995 * - x86_64_start_kernel() 996 * - relocate_initrd() 997 * So here We can do PAGE_ALIGN() safely to get partial page to be freed 998 */ 999 free_init_pages("initrd", start, PAGE_ALIGN(end)); 1000 } 1001 #endif 1002 1003 void __init zone_sizes_init(void) 1004 { 1005 unsigned long max_zone_pfns[MAX_NR_ZONES]; 1006 1007 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 1008 1009 #ifdef CONFIG_ZONE_DMA 1010 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn); 1011 #endif 1012 #ifdef CONFIG_ZONE_DMA32 1013 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn); 1014 #endif 1015 max_zone_pfns[ZONE_NORMAL] = max_low_pfn; 1016 #ifdef CONFIG_HIGHMEM 1017 max_zone_pfns[ZONE_HIGHMEM] = max_pfn; 1018 #endif 1019 1020 free_area_init(max_zone_pfns); 1021 } 1022 1023 __visible DEFINE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate) = { 1024 .loaded_mm = &init_mm, 1025 .next_asid = 1, 1026 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */ 1027 }; 1028 1029 #ifdef CONFIG_ADDRESS_MASKING 1030 DEFINE_PER_CPU(u64, tlbstate_untag_mask); 1031 EXPORT_PER_CPU_SYMBOL(tlbstate_untag_mask); 1032 #endif 1033 1034 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) 1035 { 1036 /* entry 0 MUST be WB (hardwired to speed up translations) */ 1037 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB); 1038 1039 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry); 1040 __pte2cachemode_tbl[entry] = cache; 1041 } 1042 1043 #ifdef CONFIG_SWAP 1044 unsigned long arch_max_swapfile_size(void) 1045 { 1046 unsigned long pages; 1047 1048 pages = generic_max_swapfile_size(); 1049 1050 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) { 1051 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */ 1052 unsigned long long l1tf_limit = l1tf_pfn_limit(); 1053 /* 1054 * We encode swap offsets also with 3 bits below those for pfn 1055 * which makes the usable limit higher. 1056 */ 1057 #if CONFIG_PGTABLE_LEVELS > 2 1058 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT; 1059 #endif 1060 pages = min_t(unsigned long long, l1tf_limit, pages); 1061 } 1062 return pages; 1063 } 1064 #endif 1065 1066 #ifdef CONFIG_EXECMEM 1067 static struct execmem_info execmem_info __ro_after_init; 1068 1069 #ifdef CONFIG_ARCH_HAS_EXECMEM_ROX 1070 void execmem_fill_trapping_insns(void *ptr, size_t size, bool writeable) 1071 { 1072 /* fill memory with INT3 instructions */ 1073 if (writeable) 1074 memset(ptr, INT3_INSN_OPCODE, size); 1075 else 1076 text_poke_set(ptr, INT3_INSN_OPCODE, size); 1077 } 1078 #endif 1079 1080 struct execmem_info __init *execmem_arch_setup(void) 1081 { 1082 unsigned long start, offset = 0; 1083 enum execmem_range_flags flags; 1084 pgprot_t pgprot; 1085 1086 if (kaslr_enabled()) 1087 offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE; 1088 1089 start = MODULES_VADDR + offset; 1090 1091 if (IS_ENABLED(CONFIG_ARCH_HAS_EXECMEM_ROX) && 1092 cpu_feature_enabled(X86_FEATURE_PSE)) { 1093 pgprot = PAGE_KERNEL_ROX; 1094 flags = EXECMEM_KASAN_SHADOW | EXECMEM_ROX_CACHE; 1095 } else { 1096 pgprot = PAGE_KERNEL; 1097 flags = EXECMEM_KASAN_SHADOW; 1098 } 1099 1100 execmem_info = (struct execmem_info){ 1101 .ranges = { 1102 [EXECMEM_MODULE_TEXT] = { 1103 .flags = flags, 1104 .start = start, 1105 .end = MODULES_END, 1106 .pgprot = pgprot, 1107 .alignment = MODULE_ALIGN, 1108 }, 1109 [EXECMEM_KPROBES ... EXECMEM_BPF] = { 1110 .flags = EXECMEM_KASAN_SHADOW, 1111 .start = start, 1112 .end = MODULES_END, 1113 .pgprot = PAGE_KERNEL, 1114 .alignment = MODULE_ALIGN, 1115 }, 1116 [EXECMEM_MODULE_DATA] = { 1117 .flags = EXECMEM_KASAN_SHADOW, 1118 .start = start, 1119 .end = MODULES_END, 1120 .pgprot = PAGE_KERNEL, 1121 .alignment = MODULE_ALIGN, 1122 }, 1123 }, 1124 }; 1125 1126 return &execmem_info; 1127 } 1128 #endif /* CONFIG_EXECMEM */ 1129