1 #include <linux/gfp.h> 2 #include <linux/initrd.h> 3 #include <linux/ioport.h> 4 #include <linux/swap.h> 5 #include <linux/memblock.h> 6 #include <linux/swapfile.h> 7 #include <linux/swapops.h> 8 #include <linux/kmemleak.h> 9 #include <linux/sched/task.h> 10 11 #include <asm/set_memory.h> 12 #include <asm/e820/api.h> 13 #include <asm/init.h> 14 #include <asm/page.h> 15 #include <asm/page_types.h> 16 #include <asm/sections.h> 17 #include <asm/setup.h> 18 #include <asm/tlbflush.h> 19 #include <asm/tlb.h> 20 #include <asm/proto.h> 21 #include <asm/dma.h> /* for MAX_DMA_PFN */ 22 #include <asm/microcode.h> 23 #include <asm/kaslr.h> 24 #include <asm/hypervisor.h> 25 #include <asm/cpufeature.h> 26 #include <asm/pti.h> 27 #include <asm/text-patching.h> 28 29 /* 30 * We need to define the tracepoints somewhere, and tlb.c 31 * is only compied when SMP=y. 32 */ 33 #define CREATE_TRACE_POINTS 34 #include <trace/events/tlb.h> 35 36 #include "mm_internal.h" 37 38 /* 39 * Tables translating between page_cache_type_t and pte encoding. 40 * 41 * The default values are defined statically as minimal supported mode; 42 * WC and WT fall back to UC-. pat_init() updates these values to support 43 * more cache modes, WC and WT, when it is safe to do so. See pat_init() 44 * for the details. Note, __early_ioremap() used during early boot-time 45 * takes pgprot_t (pte encoding) and does not use these tables. 46 * 47 * Index into __cachemode2pte_tbl[] is the cachemode. 48 * 49 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte 50 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2. 51 */ 52 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = { 53 [_PAGE_CACHE_MODE_WB ] = 0 | 0 , 54 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD, 55 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD, 56 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD, 57 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD, 58 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD, 59 }; 60 61 unsigned long cachemode2protval(enum page_cache_mode pcm) 62 { 63 if (likely(pcm == 0)) 64 return 0; 65 return __cachemode2pte_tbl[pcm]; 66 } 67 EXPORT_SYMBOL(cachemode2protval); 68 69 static uint8_t __pte2cachemode_tbl[8] = { 70 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB, 71 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 72 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 73 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC, 74 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB, 75 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 76 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 77 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC, 78 }; 79 80 /* Check that the write-protect PAT entry is set for write-protect */ 81 bool x86_has_pat_wp(void) 82 { 83 return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP; 84 } 85 86 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) 87 { 88 unsigned long masked; 89 90 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK; 91 if (likely(masked == 0)) 92 return 0; 93 return __pte2cachemode_tbl[__pte2cm_idx(masked)]; 94 } 95 96 static unsigned long __initdata pgt_buf_start; 97 static unsigned long __initdata pgt_buf_end; 98 static unsigned long __initdata pgt_buf_top; 99 100 static unsigned long min_pfn_mapped; 101 102 static bool __initdata can_use_brk_pgt = true; 103 104 /* 105 * Pages returned are already directly mapped. 106 * 107 * Changing that is likely to break Xen, see commit: 108 * 109 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve 110 * 111 * for detailed information. 112 */ 113 __ref void *alloc_low_pages(unsigned int num) 114 { 115 unsigned long pfn; 116 int i; 117 118 if (after_bootmem) { 119 unsigned int order; 120 121 order = get_order((unsigned long)num << PAGE_SHIFT); 122 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 123 } 124 125 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) { 126 unsigned long ret = 0; 127 128 if (min_pfn_mapped < max_pfn_mapped) { 129 ret = memblock_find_in_range( 130 min_pfn_mapped << PAGE_SHIFT, 131 max_pfn_mapped << PAGE_SHIFT, 132 PAGE_SIZE * num , PAGE_SIZE); 133 } 134 if (ret) 135 memblock_reserve(ret, PAGE_SIZE * num); 136 else if (can_use_brk_pgt) 137 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE)); 138 139 if (!ret) 140 panic("alloc_low_pages: can not alloc memory"); 141 142 pfn = ret >> PAGE_SHIFT; 143 } else { 144 pfn = pgt_buf_end; 145 pgt_buf_end += num; 146 } 147 148 for (i = 0; i < num; i++) { 149 void *adr; 150 151 adr = __va((pfn + i) << PAGE_SHIFT); 152 clear_page(adr); 153 } 154 155 return __va(pfn << PAGE_SHIFT); 156 } 157 158 /* 159 * By default need 3 4k for initial PMD_SIZE, 3 4k for 0-ISA_END_ADDRESS. 160 * With KASLR memory randomization, depending on the machine e820 memory 161 * and the PUD alignment. We may need twice more pages when KASLR memory 162 * randomization is enabled. 163 */ 164 #ifndef CONFIG_RANDOMIZE_MEMORY 165 #define INIT_PGD_PAGE_COUNT 6 166 #else 167 #define INIT_PGD_PAGE_COUNT 12 168 #endif 169 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE) 170 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE); 171 void __init early_alloc_pgt_buf(void) 172 { 173 unsigned long tables = INIT_PGT_BUF_SIZE; 174 phys_addr_t base; 175 176 base = __pa(extend_brk(tables, PAGE_SIZE)); 177 178 pgt_buf_start = base >> PAGE_SHIFT; 179 pgt_buf_end = pgt_buf_start; 180 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT); 181 } 182 183 int after_bootmem; 184 185 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES); 186 187 struct map_range { 188 unsigned long start; 189 unsigned long end; 190 unsigned page_size_mask; 191 }; 192 193 static int page_size_mask; 194 195 /* 196 * Save some of cr4 feature set we're using (e.g. Pentium 4MB 197 * enable and PPro Global page enable), so that any CPU's that boot 198 * up after us can get the correct flags. Invoked on the boot CPU. 199 */ 200 static inline void cr4_set_bits_and_update_boot(unsigned long mask) 201 { 202 mmu_cr4_features |= mask; 203 if (trampoline_cr4_features) 204 *trampoline_cr4_features = mmu_cr4_features; 205 cr4_set_bits(mask); 206 } 207 208 static void __init probe_page_size_mask(void) 209 { 210 /* 211 * For pagealloc debugging, identity mapping will use small pages. 212 * This will simplify cpa(), which otherwise needs to support splitting 213 * large pages into small in interrupt context, etc. 214 */ 215 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled()) 216 page_size_mask |= 1 << PG_LEVEL_2M; 217 else 218 direct_gbpages = 0; 219 220 /* Enable PSE if available */ 221 if (boot_cpu_has(X86_FEATURE_PSE)) 222 cr4_set_bits_and_update_boot(X86_CR4_PSE); 223 224 /* Enable PGE if available */ 225 __supported_pte_mask &= ~_PAGE_GLOBAL; 226 if (boot_cpu_has(X86_FEATURE_PGE)) { 227 cr4_set_bits_and_update_boot(X86_CR4_PGE); 228 __supported_pte_mask |= _PAGE_GLOBAL; 229 } 230 231 /* By the default is everything supported: */ 232 __default_kernel_pte_mask = __supported_pte_mask; 233 /* Except when with PTI where the kernel is mostly non-Global: */ 234 if (cpu_feature_enabled(X86_FEATURE_PTI)) 235 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 236 237 /* Enable 1 GB linear kernel mappings if available: */ 238 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) { 239 printk(KERN_INFO "Using GB pages for direct mapping\n"); 240 page_size_mask |= 1 << PG_LEVEL_1G; 241 } else { 242 direct_gbpages = 0; 243 } 244 } 245 246 static void setup_pcid(void) 247 { 248 if (!IS_ENABLED(CONFIG_X86_64)) 249 return; 250 251 if (!boot_cpu_has(X86_FEATURE_PCID)) 252 return; 253 254 if (boot_cpu_has(X86_FEATURE_PGE)) { 255 /* 256 * This can't be cr4_set_bits_and_update_boot() -- the 257 * trampoline code can't handle CR4.PCIDE and it wouldn't 258 * do any good anyway. Despite the name, 259 * cr4_set_bits_and_update_boot() doesn't actually cause 260 * the bits in question to remain set all the way through 261 * the secondary boot asm. 262 * 263 * Instead, we brute-force it and set CR4.PCIDE manually in 264 * start_secondary(). 265 */ 266 cr4_set_bits(X86_CR4_PCIDE); 267 268 /* 269 * INVPCID's single-context modes (2/3) only work if we set 270 * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable 271 * on systems that have X86_CR4_PCIDE clear, or that have 272 * no INVPCID support at all. 273 */ 274 if (boot_cpu_has(X86_FEATURE_INVPCID)) 275 setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE); 276 } else { 277 /* 278 * flush_tlb_all(), as currently implemented, won't work if 279 * PCID is on but PGE is not. Since that combination 280 * doesn't exist on real hardware, there's no reason to try 281 * to fully support it, but it's polite to avoid corrupting 282 * data if we're on an improperly configured VM. 283 */ 284 setup_clear_cpu_cap(X86_FEATURE_PCID); 285 } 286 } 287 288 #ifdef CONFIG_X86_32 289 #define NR_RANGE_MR 3 290 #else /* CONFIG_X86_64 */ 291 #define NR_RANGE_MR 5 292 #endif 293 294 static int __meminit save_mr(struct map_range *mr, int nr_range, 295 unsigned long start_pfn, unsigned long end_pfn, 296 unsigned long page_size_mask) 297 { 298 if (start_pfn < end_pfn) { 299 if (nr_range >= NR_RANGE_MR) 300 panic("run out of range for init_memory_mapping\n"); 301 mr[nr_range].start = start_pfn<<PAGE_SHIFT; 302 mr[nr_range].end = end_pfn<<PAGE_SHIFT; 303 mr[nr_range].page_size_mask = page_size_mask; 304 nr_range++; 305 } 306 307 return nr_range; 308 } 309 310 /* 311 * adjust the page_size_mask for small range to go with 312 * big page size instead small one if nearby are ram too. 313 */ 314 static void __ref adjust_range_page_size_mask(struct map_range *mr, 315 int nr_range) 316 { 317 int i; 318 319 for (i = 0; i < nr_range; i++) { 320 if ((page_size_mask & (1<<PG_LEVEL_2M)) && 321 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) { 322 unsigned long start = round_down(mr[i].start, PMD_SIZE); 323 unsigned long end = round_up(mr[i].end, PMD_SIZE); 324 325 #ifdef CONFIG_X86_32 326 if ((end >> PAGE_SHIFT) > max_low_pfn) 327 continue; 328 #endif 329 330 if (memblock_is_region_memory(start, end - start)) 331 mr[i].page_size_mask |= 1<<PG_LEVEL_2M; 332 } 333 if ((page_size_mask & (1<<PG_LEVEL_1G)) && 334 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) { 335 unsigned long start = round_down(mr[i].start, PUD_SIZE); 336 unsigned long end = round_up(mr[i].end, PUD_SIZE); 337 338 if (memblock_is_region_memory(start, end - start)) 339 mr[i].page_size_mask |= 1<<PG_LEVEL_1G; 340 } 341 } 342 } 343 344 static const char *page_size_string(struct map_range *mr) 345 { 346 static const char str_1g[] = "1G"; 347 static const char str_2m[] = "2M"; 348 static const char str_4m[] = "4M"; 349 static const char str_4k[] = "4k"; 350 351 if (mr->page_size_mask & (1<<PG_LEVEL_1G)) 352 return str_1g; 353 /* 354 * 32-bit without PAE has a 4M large page size. 355 * PG_LEVEL_2M is misnamed, but we can at least 356 * print out the right size in the string. 357 */ 358 if (IS_ENABLED(CONFIG_X86_32) && 359 !IS_ENABLED(CONFIG_X86_PAE) && 360 mr->page_size_mask & (1<<PG_LEVEL_2M)) 361 return str_4m; 362 363 if (mr->page_size_mask & (1<<PG_LEVEL_2M)) 364 return str_2m; 365 366 return str_4k; 367 } 368 369 static int __meminit split_mem_range(struct map_range *mr, int nr_range, 370 unsigned long start, 371 unsigned long end) 372 { 373 unsigned long start_pfn, end_pfn, limit_pfn; 374 unsigned long pfn; 375 int i; 376 377 limit_pfn = PFN_DOWN(end); 378 379 /* head if not big page alignment ? */ 380 pfn = start_pfn = PFN_DOWN(start); 381 #ifdef CONFIG_X86_32 382 /* 383 * Don't use a large page for the first 2/4MB of memory 384 * because there are often fixed size MTRRs in there 385 * and overlapping MTRRs into large pages can cause 386 * slowdowns. 387 */ 388 if (pfn == 0) 389 end_pfn = PFN_DOWN(PMD_SIZE); 390 else 391 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 392 #else /* CONFIG_X86_64 */ 393 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 394 #endif 395 if (end_pfn > limit_pfn) 396 end_pfn = limit_pfn; 397 if (start_pfn < end_pfn) { 398 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 399 pfn = end_pfn; 400 } 401 402 /* big page (2M) range */ 403 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 404 #ifdef CONFIG_X86_32 405 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 406 #else /* CONFIG_X86_64 */ 407 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 408 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE))) 409 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 410 #endif 411 412 if (start_pfn < end_pfn) { 413 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 414 page_size_mask & (1<<PG_LEVEL_2M)); 415 pfn = end_pfn; 416 } 417 418 #ifdef CONFIG_X86_64 419 /* big page (1G) range */ 420 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 421 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE)); 422 if (start_pfn < end_pfn) { 423 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 424 page_size_mask & 425 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); 426 pfn = end_pfn; 427 } 428 429 /* tail is not big page (1G) alignment */ 430 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 431 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 432 if (start_pfn < end_pfn) { 433 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 434 page_size_mask & (1<<PG_LEVEL_2M)); 435 pfn = end_pfn; 436 } 437 #endif 438 439 /* tail is not big page (2M) alignment */ 440 start_pfn = pfn; 441 end_pfn = limit_pfn; 442 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 443 444 if (!after_bootmem) 445 adjust_range_page_size_mask(mr, nr_range); 446 447 /* try to merge same page size and continuous */ 448 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { 449 unsigned long old_start; 450 if (mr[i].end != mr[i+1].start || 451 mr[i].page_size_mask != mr[i+1].page_size_mask) 452 continue; 453 /* move it */ 454 old_start = mr[i].start; 455 memmove(&mr[i], &mr[i+1], 456 (nr_range - 1 - i) * sizeof(struct map_range)); 457 mr[i--].start = old_start; 458 nr_range--; 459 } 460 461 for (i = 0; i < nr_range; i++) 462 pr_debug(" [mem %#010lx-%#010lx] page %s\n", 463 mr[i].start, mr[i].end - 1, 464 page_size_string(&mr[i])); 465 466 return nr_range; 467 } 468 469 struct range pfn_mapped[E820_MAX_ENTRIES]; 470 int nr_pfn_mapped; 471 472 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn) 473 { 474 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES, 475 nr_pfn_mapped, start_pfn, end_pfn); 476 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES); 477 478 max_pfn_mapped = max(max_pfn_mapped, end_pfn); 479 480 if (start_pfn < (1UL<<(32-PAGE_SHIFT))) 481 max_low_pfn_mapped = max(max_low_pfn_mapped, 482 min(end_pfn, 1UL<<(32-PAGE_SHIFT))); 483 } 484 485 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn) 486 { 487 int i; 488 489 for (i = 0; i < nr_pfn_mapped; i++) 490 if ((start_pfn >= pfn_mapped[i].start) && 491 (end_pfn <= pfn_mapped[i].end)) 492 return true; 493 494 return false; 495 } 496 497 /* 498 * Setup the direct mapping of the physical memory at PAGE_OFFSET. 499 * This runs before bootmem is initialized and gets pages directly from 500 * the physical memory. To access them they are temporarily mapped. 501 */ 502 unsigned long __ref init_memory_mapping(unsigned long start, 503 unsigned long end, pgprot_t prot) 504 { 505 struct map_range mr[NR_RANGE_MR]; 506 unsigned long ret = 0; 507 int nr_range, i; 508 509 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n", 510 start, end - 1); 511 512 memset(mr, 0, sizeof(mr)); 513 nr_range = split_mem_range(mr, 0, start, end); 514 515 for (i = 0; i < nr_range; i++) 516 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end, 517 mr[i].page_size_mask, 518 prot); 519 520 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT); 521 522 return ret >> PAGE_SHIFT; 523 } 524 525 /* 526 * We need to iterate through the E820 memory map and create direct mappings 527 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply 528 * create direct mappings for all pfns from [0 to max_low_pfn) and 529 * [4GB to max_pfn) because of possible memory holes in high addresses 530 * that cannot be marked as UC by fixed/variable range MTRRs. 531 * Depending on the alignment of E820 ranges, this may possibly result 532 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables. 533 * 534 * init_mem_mapping() calls init_range_memory_mapping() with big range. 535 * That range would have hole in the middle or ends, and only ram parts 536 * will be mapped in init_range_memory_mapping(). 537 */ 538 static unsigned long __init init_range_memory_mapping( 539 unsigned long r_start, 540 unsigned long r_end) 541 { 542 unsigned long start_pfn, end_pfn; 543 unsigned long mapped_ram_size = 0; 544 int i; 545 546 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 547 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end); 548 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end); 549 if (start >= end) 550 continue; 551 552 /* 553 * if it is overlapping with brk pgt, we need to 554 * alloc pgt buf from memblock instead. 555 */ 556 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >= 557 min(end, (u64)pgt_buf_top<<PAGE_SHIFT); 558 init_memory_mapping(start, end, PAGE_KERNEL); 559 mapped_ram_size += end - start; 560 can_use_brk_pgt = true; 561 } 562 563 return mapped_ram_size; 564 } 565 566 static unsigned long __init get_new_step_size(unsigned long step_size) 567 { 568 /* 569 * Initial mapped size is PMD_SIZE (2M). 570 * We can not set step_size to be PUD_SIZE (1G) yet. 571 * In worse case, when we cross the 1G boundary, and 572 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k) 573 * to map 1G range with PTE. Hence we use one less than the 574 * difference of page table level shifts. 575 * 576 * Don't need to worry about overflow in the top-down case, on 32bit, 577 * when step_size is 0, round_down() returns 0 for start, and that 578 * turns it into 0x100000000ULL. 579 * In the bottom-up case, round_up(x, 0) returns 0 though too, which 580 * needs to be taken into consideration by the code below. 581 */ 582 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1); 583 } 584 585 /** 586 * memory_map_top_down - Map [map_start, map_end) top down 587 * @map_start: start address of the target memory range 588 * @map_end: end address of the target memory range 589 * 590 * This function will setup direct mapping for memory range 591 * [map_start, map_end) in top-down. That said, the page tables 592 * will be allocated at the end of the memory, and we map the 593 * memory in top-down. 594 */ 595 static void __init memory_map_top_down(unsigned long map_start, 596 unsigned long map_end) 597 { 598 unsigned long real_end, start, last_start; 599 unsigned long step_size; 600 unsigned long addr; 601 unsigned long mapped_ram_size = 0; 602 603 /* xen has big range in reserved near end of ram, skip it at first.*/ 604 addr = memblock_find_in_range(map_start, map_end, PMD_SIZE, PMD_SIZE); 605 real_end = addr + PMD_SIZE; 606 607 /* step_size need to be small so pgt_buf from BRK could cover it */ 608 step_size = PMD_SIZE; 609 max_pfn_mapped = 0; /* will get exact value next */ 610 min_pfn_mapped = real_end >> PAGE_SHIFT; 611 last_start = start = real_end; 612 613 /* 614 * We start from the top (end of memory) and go to the bottom. 615 * The memblock_find_in_range() gets us a block of RAM from the 616 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 617 * for page table. 618 */ 619 while (last_start > map_start) { 620 if (last_start > step_size) { 621 start = round_down(last_start - 1, step_size); 622 if (start < map_start) 623 start = map_start; 624 } else 625 start = map_start; 626 mapped_ram_size += init_range_memory_mapping(start, 627 last_start); 628 last_start = start; 629 min_pfn_mapped = last_start >> PAGE_SHIFT; 630 if (mapped_ram_size >= step_size) 631 step_size = get_new_step_size(step_size); 632 } 633 634 if (real_end < map_end) 635 init_range_memory_mapping(real_end, map_end); 636 } 637 638 /** 639 * memory_map_bottom_up - Map [map_start, map_end) bottom up 640 * @map_start: start address of the target memory range 641 * @map_end: end address of the target memory range 642 * 643 * This function will setup direct mapping for memory range 644 * [map_start, map_end) in bottom-up. Since we have limited the 645 * bottom-up allocation above the kernel, the page tables will 646 * be allocated just above the kernel and we map the memory 647 * in [map_start, map_end) in bottom-up. 648 */ 649 static void __init memory_map_bottom_up(unsigned long map_start, 650 unsigned long map_end) 651 { 652 unsigned long next, start; 653 unsigned long mapped_ram_size = 0; 654 /* step_size need to be small so pgt_buf from BRK could cover it */ 655 unsigned long step_size = PMD_SIZE; 656 657 start = map_start; 658 min_pfn_mapped = start >> PAGE_SHIFT; 659 660 /* 661 * We start from the bottom (@map_start) and go to the top (@map_end). 662 * The memblock_find_in_range() gets us a block of RAM from the 663 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 664 * for page table. 665 */ 666 while (start < map_end) { 667 if (step_size && map_end - start > step_size) { 668 next = round_up(start + 1, step_size); 669 if (next > map_end) 670 next = map_end; 671 } else { 672 next = map_end; 673 } 674 675 mapped_ram_size += init_range_memory_mapping(start, next); 676 start = next; 677 678 if (mapped_ram_size >= step_size) 679 step_size = get_new_step_size(step_size); 680 } 681 } 682 683 /* 684 * The real mode trampoline, which is required for bootstrapping CPUs 685 * occupies only a small area under the low 1MB. See reserve_real_mode() 686 * for details. 687 * 688 * If KASLR is disabled the first PGD entry of the direct mapping is copied 689 * to map the real mode trampoline. 690 * 691 * If KASLR is enabled, copy only the PUD which covers the low 1MB 692 * area. This limits the randomization granularity to 1GB for both 4-level 693 * and 5-level paging. 694 */ 695 static void __init init_trampoline(void) 696 { 697 #ifdef CONFIG_X86_64 698 if (!kaslr_memory_enabled()) 699 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)]; 700 else 701 init_trampoline_kaslr(); 702 #endif 703 } 704 705 void __init init_mem_mapping(void) 706 { 707 unsigned long end; 708 709 pti_check_boottime_disable(); 710 probe_page_size_mask(); 711 setup_pcid(); 712 713 #ifdef CONFIG_X86_64 714 end = max_pfn << PAGE_SHIFT; 715 #else 716 end = max_low_pfn << PAGE_SHIFT; 717 #endif 718 719 /* the ISA range is always mapped regardless of memory holes */ 720 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL); 721 722 /* Init the trampoline, possibly with KASLR memory offset */ 723 init_trampoline(); 724 725 /* 726 * If the allocation is in bottom-up direction, we setup direct mapping 727 * in bottom-up, otherwise we setup direct mapping in top-down. 728 */ 729 if (memblock_bottom_up()) { 730 unsigned long kernel_end = __pa_symbol(_end); 731 732 /* 733 * we need two separate calls here. This is because we want to 734 * allocate page tables above the kernel. So we first map 735 * [kernel_end, end) to make memory above the kernel be mapped 736 * as soon as possible. And then use page tables allocated above 737 * the kernel to map [ISA_END_ADDRESS, kernel_end). 738 */ 739 memory_map_bottom_up(kernel_end, end); 740 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end); 741 } else { 742 memory_map_top_down(ISA_END_ADDRESS, end); 743 } 744 745 #ifdef CONFIG_X86_64 746 if (max_pfn > max_low_pfn) { 747 /* can we preseve max_low_pfn ?*/ 748 max_low_pfn = max_pfn; 749 } 750 #else 751 early_ioremap_page_table_range_init(); 752 #endif 753 754 load_cr3(swapper_pg_dir); 755 __flush_tlb_all(); 756 757 x86_init.hyper.init_mem_mapping(); 758 759 early_memtest(0, max_pfn_mapped << PAGE_SHIFT); 760 } 761 762 /* 763 * Initialize an mm_struct to be used during poking and a pointer to be used 764 * during patching. 765 */ 766 void __init poking_init(void) 767 { 768 spinlock_t *ptl; 769 pte_t *ptep; 770 771 poking_mm = copy_init_mm(); 772 BUG_ON(!poking_mm); 773 774 /* 775 * Randomize the poking address, but make sure that the following page 776 * will be mapped at the same PMD. We need 2 pages, so find space for 3, 777 * and adjust the address if the PMD ends after the first one. 778 */ 779 poking_addr = TASK_UNMAPPED_BASE; 780 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 781 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) % 782 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE); 783 784 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0) 785 poking_addr += PAGE_SIZE; 786 787 /* 788 * We need to trigger the allocation of the page-tables that will be 789 * needed for poking now. Later, poking may be performed in an atomic 790 * section, which might cause allocation to fail. 791 */ 792 ptep = get_locked_pte(poking_mm, poking_addr, &ptl); 793 BUG_ON(!ptep); 794 pte_unmap_unlock(ptep, ptl); 795 } 796 797 /* 798 * devmem_is_allowed() checks to see if /dev/mem access to a certain address 799 * is valid. The argument is a physical page number. 800 * 801 * On x86, access has to be given to the first megabyte of RAM because that 802 * area traditionally contains BIOS code and data regions used by X, dosemu, 803 * and similar apps. Since they map the entire memory range, the whole range 804 * must be allowed (for mapping), but any areas that would otherwise be 805 * disallowed are flagged as being "zero filled" instead of rejected. 806 * Access has to be given to non-kernel-ram areas as well, these contain the 807 * PCI mmio resources as well as potential bios/acpi data regions. 808 */ 809 int devmem_is_allowed(unsigned long pagenr) 810 { 811 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE, 812 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE) 813 != REGION_DISJOINT) { 814 /* 815 * For disallowed memory regions in the low 1MB range, 816 * request that the page be shown as all zeros. 817 */ 818 if (pagenr < 256) 819 return 2; 820 821 return 0; 822 } 823 824 /* 825 * This must follow RAM test, since System RAM is considered a 826 * restricted resource under CONFIG_STRICT_IOMEM. 827 */ 828 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) { 829 /* Low 1MB bypasses iomem restrictions. */ 830 if (pagenr < 256) 831 return 1; 832 833 return 0; 834 } 835 836 return 1; 837 } 838 839 void free_init_pages(const char *what, unsigned long begin, unsigned long end) 840 { 841 unsigned long begin_aligned, end_aligned; 842 843 /* Make sure boundaries are page aligned */ 844 begin_aligned = PAGE_ALIGN(begin); 845 end_aligned = end & PAGE_MASK; 846 847 if (WARN_ON(begin_aligned != begin || end_aligned != end)) { 848 begin = begin_aligned; 849 end = end_aligned; 850 } 851 852 if (begin >= end) 853 return; 854 855 /* 856 * If debugging page accesses then do not free this memory but 857 * mark them not present - any buggy init-section access will 858 * create a kernel page fault: 859 */ 860 if (debug_pagealloc_enabled()) { 861 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n", 862 begin, end - 1); 863 /* 864 * Inform kmemleak about the hole in the memory since the 865 * corresponding pages will be unmapped. 866 */ 867 kmemleak_free_part((void *)begin, end - begin); 868 set_memory_np(begin, (end - begin) >> PAGE_SHIFT); 869 } else { 870 /* 871 * We just marked the kernel text read only above, now that 872 * we are going to free part of that, we need to make that 873 * writeable and non-executable first. 874 */ 875 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT); 876 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT); 877 878 free_reserved_area((void *)begin, (void *)end, 879 POISON_FREE_INITMEM, what); 880 } 881 } 882 883 /* 884 * begin/end can be in the direct map or the "high kernel mapping" 885 * used for the kernel image only. free_init_pages() will do the 886 * right thing for either kind of address. 887 */ 888 void free_kernel_image_pages(const char *what, void *begin, void *end) 889 { 890 unsigned long begin_ul = (unsigned long)begin; 891 unsigned long end_ul = (unsigned long)end; 892 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT; 893 894 free_init_pages(what, begin_ul, end_ul); 895 896 /* 897 * PTI maps some of the kernel into userspace. For performance, 898 * this includes some kernel areas that do not contain secrets. 899 * Those areas might be adjacent to the parts of the kernel image 900 * being freed, which may contain secrets. Remove the "high kernel 901 * image mapping" for these freed areas, ensuring they are not even 902 * potentially vulnerable to Meltdown regardless of the specific 903 * optimizations PTI is currently using. 904 * 905 * The "noalias" prevents unmapping the direct map alias which is 906 * needed to access the freed pages. 907 * 908 * This is only valid for 64bit kernels. 32bit has only one mapping 909 * which can't be treated in this way for obvious reasons. 910 */ 911 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI)) 912 set_memory_np_noalias(begin_ul, len_pages); 913 } 914 915 void __weak mem_encrypt_free_decrypted_mem(void) { } 916 917 void __ref free_initmem(void) 918 { 919 e820__reallocate_tables(); 920 921 mem_encrypt_free_decrypted_mem(); 922 923 free_kernel_image_pages("unused kernel image (initmem)", 924 &__init_begin, &__init_end); 925 } 926 927 #ifdef CONFIG_BLK_DEV_INITRD 928 void __init free_initrd_mem(unsigned long start, unsigned long end) 929 { 930 /* 931 * end could be not aligned, and We can not align that, 932 * decompresser could be confused by aligned initrd_end 933 * We already reserve the end partial page before in 934 * - i386_start_kernel() 935 * - x86_64_start_kernel() 936 * - relocate_initrd() 937 * So here We can do PAGE_ALIGN() safely to get partial page to be freed 938 */ 939 free_init_pages("initrd", start, PAGE_ALIGN(end)); 940 } 941 #endif 942 943 /* 944 * Calculate the precise size of the DMA zone (first 16 MB of RAM), 945 * and pass it to the MM layer - to help it set zone watermarks more 946 * accurately. 947 * 948 * Done on 64-bit systems only for the time being, although 32-bit systems 949 * might benefit from this as well. 950 */ 951 void __init memblock_find_dma_reserve(void) 952 { 953 #ifdef CONFIG_X86_64 954 u64 nr_pages = 0, nr_free_pages = 0; 955 unsigned long start_pfn, end_pfn; 956 phys_addr_t start_addr, end_addr; 957 int i; 958 u64 u; 959 960 /* 961 * Iterate over all memory ranges (free and reserved ones alike), 962 * to calculate the total number of pages in the first 16 MB of RAM: 963 */ 964 nr_pages = 0; 965 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 966 start_pfn = min(start_pfn, MAX_DMA_PFN); 967 end_pfn = min(end_pfn, MAX_DMA_PFN); 968 969 nr_pages += end_pfn - start_pfn; 970 } 971 972 /* 973 * Iterate over free memory ranges to calculate the number of free 974 * pages in the DMA zone, while not counting potential partial 975 * pages at the beginning or the end of the range: 976 */ 977 nr_free_pages = 0; 978 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) { 979 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN); 980 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN); 981 982 if (start_pfn < end_pfn) 983 nr_free_pages += end_pfn - start_pfn; 984 } 985 986 set_dma_reserve(nr_pages - nr_free_pages); 987 #endif 988 } 989 990 void __init zone_sizes_init(void) 991 { 992 unsigned long max_zone_pfns[MAX_NR_ZONES]; 993 994 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 995 996 #ifdef CONFIG_ZONE_DMA 997 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn); 998 #endif 999 #ifdef CONFIG_ZONE_DMA32 1000 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn); 1001 #endif 1002 max_zone_pfns[ZONE_NORMAL] = max_low_pfn; 1003 #ifdef CONFIG_HIGHMEM 1004 max_zone_pfns[ZONE_HIGHMEM] = max_pfn; 1005 #endif 1006 1007 free_area_init(max_zone_pfns); 1008 } 1009 1010 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { 1011 .loaded_mm = &init_mm, 1012 .next_asid = 1, 1013 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */ 1014 }; 1015 1016 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) 1017 { 1018 /* entry 0 MUST be WB (hardwired to speed up translations) */ 1019 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB); 1020 1021 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry); 1022 __pte2cachemode_tbl[entry] = cache; 1023 } 1024 1025 #ifdef CONFIG_SWAP 1026 unsigned long max_swapfile_size(void) 1027 { 1028 unsigned long pages; 1029 1030 pages = generic_max_swapfile_size(); 1031 1032 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) { 1033 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */ 1034 unsigned long long l1tf_limit = l1tf_pfn_limit(); 1035 /* 1036 * We encode swap offsets also with 3 bits below those for pfn 1037 * which makes the usable limit higher. 1038 */ 1039 #if CONFIG_PGTABLE_LEVELS > 2 1040 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT; 1041 #endif 1042 pages = min_t(unsigned long long, l1tf_limit, pages); 1043 } 1044 return pages; 1045 } 1046 #endif 1047