1 #include <linux/gfp.h> 2 #include <linux/initrd.h> 3 #include <linux/ioport.h> 4 #include <linux/swap.h> 5 #include <linux/memblock.h> 6 #include <linux/swapfile.h> 7 #include <linux/swapops.h> 8 #include <linux/kmemleak.h> 9 #include <linux/sched/task.h> 10 #include <linux/execmem.h> 11 12 #include <asm/set_memory.h> 13 #include <asm/cpu_device_id.h> 14 #include <asm/e820/api.h> 15 #include <asm/init.h> 16 #include <asm/page.h> 17 #include <asm/page_types.h> 18 #include <asm/sections.h> 19 #include <asm/setup.h> 20 #include <asm/tlbflush.h> 21 #include <asm/tlb.h> 22 #include <asm/proto.h> 23 #include <asm/dma.h> /* for MAX_DMA_PFN */ 24 #include <asm/kaslr.h> 25 #include <asm/hypervisor.h> 26 #include <asm/cpufeature.h> 27 #include <asm/pti.h> 28 #include <asm/text-patching.h> 29 #include <asm/memtype.h> 30 #include <asm/paravirt.h> 31 32 /* 33 * We need to define the tracepoints somewhere, and tlb.c 34 * is only compiled when SMP=y. 35 */ 36 #include <trace/events/tlb.h> 37 38 #include "mm_internal.h" 39 40 /* 41 * Tables translating between page_cache_type_t and pte encoding. 42 * 43 * The default values are defined statically as minimal supported mode; 44 * WC and WT fall back to UC-. pat_init() updates these values to support 45 * more cache modes, WC and WT, when it is safe to do so. See pat_init() 46 * for the details. Note, __early_ioremap() used during early boot-time 47 * takes pgprot_t (pte encoding) and does not use these tables. 48 * 49 * Index into __cachemode2pte_tbl[] is the cachemode. 50 * 51 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte 52 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2. 53 */ 54 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = { 55 [_PAGE_CACHE_MODE_WB ] = 0 | 0 , 56 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD, 57 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD, 58 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD, 59 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD, 60 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD, 61 }; 62 63 unsigned long cachemode2protval(enum page_cache_mode pcm) 64 { 65 if (likely(pcm == 0)) 66 return 0; 67 return __cachemode2pte_tbl[pcm]; 68 } 69 EXPORT_SYMBOL(cachemode2protval); 70 71 static uint8_t __pte2cachemode_tbl[8] = { 72 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB, 73 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 74 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 75 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC, 76 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB, 77 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 78 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 79 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC, 80 }; 81 82 /* 83 * Check that the write-protect PAT entry is set for write-protect. 84 * To do this without making assumptions how PAT has been set up (Xen has 85 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache 86 * mode via the __cachemode2pte_tbl[] into protection bits (those protection 87 * bits will select a cache mode of WP or better), and then translate the 88 * protection bits back into the cache mode using __pte2cm_idx() and the 89 * __pte2cachemode_tbl[] array. This will return the really used cache mode. 90 */ 91 bool x86_has_pat_wp(void) 92 { 93 uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP]; 94 95 return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP; 96 } 97 98 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) 99 { 100 unsigned long masked; 101 102 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK; 103 if (likely(masked == 0)) 104 return 0; 105 return __pte2cachemode_tbl[__pte2cm_idx(masked)]; 106 } 107 108 static unsigned long __initdata pgt_buf_start; 109 static unsigned long __initdata pgt_buf_end; 110 static unsigned long __initdata pgt_buf_top; 111 112 static unsigned long min_pfn_mapped; 113 114 static bool __initdata can_use_brk_pgt = true; 115 116 /* 117 * Pages returned are already directly mapped. 118 * 119 * Changing that is likely to break Xen, see commit: 120 * 121 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve 122 * 123 * for detailed information. 124 */ 125 __ref void *alloc_low_pages(unsigned int num) 126 { 127 unsigned long pfn; 128 int i; 129 130 if (after_bootmem) { 131 unsigned int order; 132 133 order = get_order((unsigned long)num << PAGE_SHIFT); 134 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 135 } 136 137 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) { 138 unsigned long ret = 0; 139 140 if (min_pfn_mapped < max_pfn_mapped) { 141 ret = memblock_phys_alloc_range( 142 PAGE_SIZE * num, PAGE_SIZE, 143 min_pfn_mapped << PAGE_SHIFT, 144 max_pfn_mapped << PAGE_SHIFT); 145 } 146 if (!ret && can_use_brk_pgt) 147 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE)); 148 149 if (!ret) 150 panic("alloc_low_pages: can not alloc memory"); 151 152 pfn = ret >> PAGE_SHIFT; 153 } else { 154 pfn = pgt_buf_end; 155 pgt_buf_end += num; 156 } 157 158 for (i = 0; i < num; i++) { 159 void *adr; 160 161 adr = __va((pfn + i) << PAGE_SHIFT); 162 clear_page(adr); 163 } 164 165 return __va(pfn << PAGE_SHIFT); 166 } 167 168 /* 169 * By default need to be able to allocate page tables below PGD firstly for 170 * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping. 171 * With KASLR memory randomization, depending on the machine e820 memory and the 172 * PUD alignment, twice that many pages may be needed when KASLR memory 173 * randomization is enabled. 174 */ 175 176 #ifndef CONFIG_X86_5LEVEL 177 #define INIT_PGD_PAGE_TABLES 3 178 #else 179 #define INIT_PGD_PAGE_TABLES 4 180 #endif 181 182 #ifndef CONFIG_RANDOMIZE_MEMORY 183 #define INIT_PGD_PAGE_COUNT (2 * INIT_PGD_PAGE_TABLES) 184 #else 185 #define INIT_PGD_PAGE_COUNT (4 * INIT_PGD_PAGE_TABLES) 186 #endif 187 188 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE) 189 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE); 190 void __init early_alloc_pgt_buf(void) 191 { 192 unsigned long tables = INIT_PGT_BUF_SIZE; 193 phys_addr_t base; 194 195 base = __pa(extend_brk(tables, PAGE_SIZE)); 196 197 pgt_buf_start = base >> PAGE_SHIFT; 198 pgt_buf_end = pgt_buf_start; 199 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT); 200 } 201 202 int after_bootmem; 203 204 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES); 205 206 struct map_range { 207 unsigned long start; 208 unsigned long end; 209 unsigned page_size_mask; 210 }; 211 212 static int page_size_mask; 213 214 /* 215 * Save some of cr4 feature set we're using (e.g. Pentium 4MB 216 * enable and PPro Global page enable), so that any CPU's that boot 217 * up after us can get the correct flags. Invoked on the boot CPU. 218 */ 219 static inline void cr4_set_bits_and_update_boot(unsigned long mask) 220 { 221 mmu_cr4_features |= mask; 222 if (trampoline_cr4_features) 223 *trampoline_cr4_features = mmu_cr4_features; 224 cr4_set_bits(mask); 225 } 226 227 static void __init probe_page_size_mask(void) 228 { 229 /* 230 * For pagealloc debugging, identity mapping will use small pages. 231 * This will simplify cpa(), which otherwise needs to support splitting 232 * large pages into small in interrupt context, etc. 233 */ 234 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled()) 235 page_size_mask |= 1 << PG_LEVEL_2M; 236 else 237 direct_gbpages = 0; 238 239 /* Enable PSE if available */ 240 if (boot_cpu_has(X86_FEATURE_PSE)) 241 cr4_set_bits_and_update_boot(X86_CR4_PSE); 242 243 /* Enable PGE if available */ 244 __supported_pte_mask &= ~_PAGE_GLOBAL; 245 if (boot_cpu_has(X86_FEATURE_PGE)) { 246 cr4_set_bits_and_update_boot(X86_CR4_PGE); 247 __supported_pte_mask |= _PAGE_GLOBAL; 248 } 249 250 /* By the default is everything supported: */ 251 __default_kernel_pte_mask = __supported_pte_mask; 252 /* Except when with PTI where the kernel is mostly non-Global: */ 253 if (cpu_feature_enabled(X86_FEATURE_PTI)) 254 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 255 256 /* Enable 1 GB linear kernel mappings if available: */ 257 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) { 258 printk(KERN_INFO "Using GB pages for direct mapping\n"); 259 page_size_mask |= 1 << PG_LEVEL_1G; 260 } else { 261 direct_gbpages = 0; 262 } 263 } 264 265 /* 266 * INVLPG may not properly flush Global entries 267 * on these CPUs when PCIDs are enabled. 268 */ 269 static const struct x86_cpu_id invlpg_miss_ids[] = { 270 X86_MATCH_VFM(INTEL_ALDERLAKE, 0), 271 X86_MATCH_VFM(INTEL_ALDERLAKE_L, 0), 272 X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, 0), 273 X86_MATCH_VFM(INTEL_RAPTORLAKE, 0), 274 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, 0), 275 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, 0), 276 {} 277 }; 278 279 static void setup_pcid(void) 280 { 281 if (!IS_ENABLED(CONFIG_X86_64)) 282 return; 283 284 if (!boot_cpu_has(X86_FEATURE_PCID)) 285 return; 286 287 if (x86_match_cpu(invlpg_miss_ids)) { 288 pr_info("Incomplete global flushes, disabling PCID"); 289 setup_clear_cpu_cap(X86_FEATURE_PCID); 290 return; 291 } 292 293 if (boot_cpu_has(X86_FEATURE_PGE)) { 294 /* 295 * This can't be cr4_set_bits_and_update_boot() -- the 296 * trampoline code can't handle CR4.PCIDE and it wouldn't 297 * do any good anyway. Despite the name, 298 * cr4_set_bits_and_update_boot() doesn't actually cause 299 * the bits in question to remain set all the way through 300 * the secondary boot asm. 301 * 302 * Instead, we brute-force it and set CR4.PCIDE manually in 303 * start_secondary(). 304 */ 305 cr4_set_bits(X86_CR4_PCIDE); 306 } else { 307 /* 308 * flush_tlb_all(), as currently implemented, won't work if 309 * PCID is on but PGE is not. Since that combination 310 * doesn't exist on real hardware, there's no reason to try 311 * to fully support it, but it's polite to avoid corrupting 312 * data if we're on an improperly configured VM. 313 */ 314 setup_clear_cpu_cap(X86_FEATURE_PCID); 315 } 316 } 317 318 #ifdef CONFIG_X86_32 319 #define NR_RANGE_MR 3 320 #else /* CONFIG_X86_64 */ 321 #define NR_RANGE_MR 5 322 #endif 323 324 static int __meminit save_mr(struct map_range *mr, int nr_range, 325 unsigned long start_pfn, unsigned long end_pfn, 326 unsigned long page_size_mask) 327 { 328 if (start_pfn < end_pfn) { 329 if (nr_range >= NR_RANGE_MR) 330 panic("run out of range for init_memory_mapping\n"); 331 mr[nr_range].start = start_pfn<<PAGE_SHIFT; 332 mr[nr_range].end = end_pfn<<PAGE_SHIFT; 333 mr[nr_range].page_size_mask = page_size_mask; 334 nr_range++; 335 } 336 337 return nr_range; 338 } 339 340 /* 341 * adjust the page_size_mask for small range to go with 342 * big page size instead small one if nearby are ram too. 343 */ 344 static void __ref adjust_range_page_size_mask(struct map_range *mr, 345 int nr_range) 346 { 347 int i; 348 349 for (i = 0; i < nr_range; i++) { 350 if ((page_size_mask & (1<<PG_LEVEL_2M)) && 351 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) { 352 unsigned long start = round_down(mr[i].start, PMD_SIZE); 353 unsigned long end = round_up(mr[i].end, PMD_SIZE); 354 355 #ifdef CONFIG_X86_32 356 if ((end >> PAGE_SHIFT) > max_low_pfn) 357 continue; 358 #endif 359 360 if (memblock_is_region_memory(start, end - start)) 361 mr[i].page_size_mask |= 1<<PG_LEVEL_2M; 362 } 363 if ((page_size_mask & (1<<PG_LEVEL_1G)) && 364 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) { 365 unsigned long start = round_down(mr[i].start, PUD_SIZE); 366 unsigned long end = round_up(mr[i].end, PUD_SIZE); 367 368 if (memblock_is_region_memory(start, end - start)) 369 mr[i].page_size_mask |= 1<<PG_LEVEL_1G; 370 } 371 } 372 } 373 374 static const char *page_size_string(struct map_range *mr) 375 { 376 static const char str_1g[] = "1G"; 377 static const char str_2m[] = "2M"; 378 static const char str_4m[] = "4M"; 379 static const char str_4k[] = "4k"; 380 381 if (mr->page_size_mask & (1<<PG_LEVEL_1G)) 382 return str_1g; 383 /* 384 * 32-bit without PAE has a 4M large page size. 385 * PG_LEVEL_2M is misnamed, but we can at least 386 * print out the right size in the string. 387 */ 388 if (IS_ENABLED(CONFIG_X86_32) && 389 !IS_ENABLED(CONFIG_X86_PAE) && 390 mr->page_size_mask & (1<<PG_LEVEL_2M)) 391 return str_4m; 392 393 if (mr->page_size_mask & (1<<PG_LEVEL_2M)) 394 return str_2m; 395 396 return str_4k; 397 } 398 399 static int __meminit split_mem_range(struct map_range *mr, int nr_range, 400 unsigned long start, 401 unsigned long end) 402 { 403 unsigned long start_pfn, end_pfn, limit_pfn; 404 unsigned long pfn; 405 int i; 406 407 limit_pfn = PFN_DOWN(end); 408 409 /* head if not big page alignment ? */ 410 pfn = start_pfn = PFN_DOWN(start); 411 #ifdef CONFIG_X86_32 412 /* 413 * Don't use a large page for the first 2/4MB of memory 414 * because there are often fixed size MTRRs in there 415 * and overlapping MTRRs into large pages can cause 416 * slowdowns. 417 */ 418 if (pfn == 0) 419 end_pfn = PFN_DOWN(PMD_SIZE); 420 else 421 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 422 #else /* CONFIG_X86_64 */ 423 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 424 #endif 425 if (end_pfn > limit_pfn) 426 end_pfn = limit_pfn; 427 if (start_pfn < end_pfn) { 428 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 429 pfn = end_pfn; 430 } 431 432 /* big page (2M) range */ 433 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 434 #ifdef CONFIG_X86_32 435 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 436 #else /* CONFIG_X86_64 */ 437 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 438 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE))) 439 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 440 #endif 441 442 if (start_pfn < end_pfn) { 443 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 444 page_size_mask & (1<<PG_LEVEL_2M)); 445 pfn = end_pfn; 446 } 447 448 #ifdef CONFIG_X86_64 449 /* big page (1G) range */ 450 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 451 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE)); 452 if (start_pfn < end_pfn) { 453 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 454 page_size_mask & 455 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); 456 pfn = end_pfn; 457 } 458 459 /* tail is not big page (1G) alignment */ 460 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 461 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 462 if (start_pfn < end_pfn) { 463 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 464 page_size_mask & (1<<PG_LEVEL_2M)); 465 pfn = end_pfn; 466 } 467 #endif 468 469 /* tail is not big page (2M) alignment */ 470 start_pfn = pfn; 471 end_pfn = limit_pfn; 472 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 473 474 if (!after_bootmem) 475 adjust_range_page_size_mask(mr, nr_range); 476 477 /* try to merge same page size and continuous */ 478 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { 479 unsigned long old_start; 480 if (mr[i].end != mr[i+1].start || 481 mr[i].page_size_mask != mr[i+1].page_size_mask) 482 continue; 483 /* move it */ 484 old_start = mr[i].start; 485 memmove(&mr[i], &mr[i+1], 486 (nr_range - 1 - i) * sizeof(struct map_range)); 487 mr[i--].start = old_start; 488 nr_range--; 489 } 490 491 for (i = 0; i < nr_range; i++) 492 pr_debug(" [mem %#010lx-%#010lx] page %s\n", 493 mr[i].start, mr[i].end - 1, 494 page_size_string(&mr[i])); 495 496 return nr_range; 497 } 498 499 struct range pfn_mapped[E820_MAX_ENTRIES]; 500 int nr_pfn_mapped; 501 502 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn) 503 { 504 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES, 505 nr_pfn_mapped, start_pfn, end_pfn); 506 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES); 507 508 max_pfn_mapped = max(max_pfn_mapped, end_pfn); 509 510 if (start_pfn < (1UL<<(32-PAGE_SHIFT))) 511 max_low_pfn_mapped = max(max_low_pfn_mapped, 512 min(end_pfn, 1UL<<(32-PAGE_SHIFT))); 513 } 514 515 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn) 516 { 517 int i; 518 519 for (i = 0; i < nr_pfn_mapped; i++) 520 if ((start_pfn >= pfn_mapped[i].start) && 521 (end_pfn <= pfn_mapped[i].end)) 522 return true; 523 524 return false; 525 } 526 527 /* 528 * Setup the direct mapping of the physical memory at PAGE_OFFSET. 529 * This runs before bootmem is initialized and gets pages directly from 530 * the physical memory. To access them they are temporarily mapped. 531 */ 532 unsigned long __ref init_memory_mapping(unsigned long start, 533 unsigned long end, pgprot_t prot) 534 { 535 struct map_range mr[NR_RANGE_MR]; 536 unsigned long ret = 0; 537 int nr_range, i; 538 539 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n", 540 start, end - 1); 541 542 memset(mr, 0, sizeof(mr)); 543 nr_range = split_mem_range(mr, 0, start, end); 544 545 for (i = 0; i < nr_range; i++) 546 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end, 547 mr[i].page_size_mask, 548 prot); 549 550 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT); 551 552 return ret >> PAGE_SHIFT; 553 } 554 555 /* 556 * We need to iterate through the E820 memory map and create direct mappings 557 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply 558 * create direct mappings for all pfns from [0 to max_low_pfn) and 559 * [4GB to max_pfn) because of possible memory holes in high addresses 560 * that cannot be marked as UC by fixed/variable range MTRRs. 561 * Depending on the alignment of E820 ranges, this may possibly result 562 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables. 563 * 564 * init_mem_mapping() calls init_range_memory_mapping() with big range. 565 * That range would have hole in the middle or ends, and only ram parts 566 * will be mapped in init_range_memory_mapping(). 567 */ 568 static unsigned long __init init_range_memory_mapping( 569 unsigned long r_start, 570 unsigned long r_end) 571 { 572 unsigned long start_pfn, end_pfn; 573 unsigned long mapped_ram_size = 0; 574 int i; 575 576 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 577 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end); 578 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end); 579 if (start >= end) 580 continue; 581 582 /* 583 * if it is overlapping with brk pgt, we need to 584 * alloc pgt buf from memblock instead. 585 */ 586 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >= 587 min(end, (u64)pgt_buf_top<<PAGE_SHIFT); 588 init_memory_mapping(start, end, PAGE_KERNEL); 589 mapped_ram_size += end - start; 590 can_use_brk_pgt = true; 591 } 592 593 return mapped_ram_size; 594 } 595 596 static unsigned long __init get_new_step_size(unsigned long step_size) 597 { 598 /* 599 * Initial mapped size is PMD_SIZE (2M). 600 * We can not set step_size to be PUD_SIZE (1G) yet. 601 * In worse case, when we cross the 1G boundary, and 602 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k) 603 * to map 1G range with PTE. Hence we use one less than the 604 * difference of page table level shifts. 605 * 606 * Don't need to worry about overflow in the top-down case, on 32bit, 607 * when step_size is 0, round_down() returns 0 for start, and that 608 * turns it into 0x100000000ULL. 609 * In the bottom-up case, round_up(x, 0) returns 0 though too, which 610 * needs to be taken into consideration by the code below. 611 */ 612 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1); 613 } 614 615 /** 616 * memory_map_top_down - Map [map_start, map_end) top down 617 * @map_start: start address of the target memory range 618 * @map_end: end address of the target memory range 619 * 620 * This function will setup direct mapping for memory range 621 * [map_start, map_end) in top-down. That said, the page tables 622 * will be allocated at the end of the memory, and we map the 623 * memory in top-down. 624 */ 625 static void __init memory_map_top_down(unsigned long map_start, 626 unsigned long map_end) 627 { 628 unsigned long real_end, last_start; 629 unsigned long step_size; 630 unsigned long addr; 631 unsigned long mapped_ram_size = 0; 632 633 /* 634 * Systems that have many reserved areas near top of the memory, 635 * e.g. QEMU with less than 1G RAM and EFI enabled, or Xen, will 636 * require lots of 4K mappings which may exhaust pgt_buf. 637 * Start with top-most PMD_SIZE range aligned at PMD_SIZE to ensure 638 * there is enough mapped memory that can be allocated from 639 * memblock. 640 */ 641 addr = memblock_phys_alloc_range(PMD_SIZE, PMD_SIZE, map_start, 642 map_end); 643 memblock_phys_free(addr, PMD_SIZE); 644 real_end = addr + PMD_SIZE; 645 646 /* step_size need to be small so pgt_buf from BRK could cover it */ 647 step_size = PMD_SIZE; 648 max_pfn_mapped = 0; /* will get exact value next */ 649 min_pfn_mapped = real_end >> PAGE_SHIFT; 650 last_start = real_end; 651 652 /* 653 * We start from the top (end of memory) and go to the bottom. 654 * The memblock_find_in_range() gets us a block of RAM from the 655 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 656 * for page table. 657 */ 658 while (last_start > map_start) { 659 unsigned long start; 660 661 if (last_start > step_size) { 662 start = round_down(last_start - 1, step_size); 663 if (start < map_start) 664 start = map_start; 665 } else 666 start = map_start; 667 mapped_ram_size += init_range_memory_mapping(start, 668 last_start); 669 last_start = start; 670 min_pfn_mapped = last_start >> PAGE_SHIFT; 671 if (mapped_ram_size >= step_size) 672 step_size = get_new_step_size(step_size); 673 } 674 675 if (real_end < map_end) 676 init_range_memory_mapping(real_end, map_end); 677 } 678 679 /** 680 * memory_map_bottom_up - Map [map_start, map_end) bottom up 681 * @map_start: start address of the target memory range 682 * @map_end: end address of the target memory range 683 * 684 * This function will setup direct mapping for memory range 685 * [map_start, map_end) in bottom-up. Since we have limited the 686 * bottom-up allocation above the kernel, the page tables will 687 * be allocated just above the kernel and we map the memory 688 * in [map_start, map_end) in bottom-up. 689 */ 690 static void __init memory_map_bottom_up(unsigned long map_start, 691 unsigned long map_end) 692 { 693 unsigned long next, start; 694 unsigned long mapped_ram_size = 0; 695 /* step_size need to be small so pgt_buf from BRK could cover it */ 696 unsigned long step_size = PMD_SIZE; 697 698 start = map_start; 699 min_pfn_mapped = start >> PAGE_SHIFT; 700 701 /* 702 * We start from the bottom (@map_start) and go to the top (@map_end). 703 * The memblock_find_in_range() gets us a block of RAM from the 704 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 705 * for page table. 706 */ 707 while (start < map_end) { 708 if (step_size && map_end - start > step_size) { 709 next = round_up(start + 1, step_size); 710 if (next > map_end) 711 next = map_end; 712 } else { 713 next = map_end; 714 } 715 716 mapped_ram_size += init_range_memory_mapping(start, next); 717 start = next; 718 719 if (mapped_ram_size >= step_size) 720 step_size = get_new_step_size(step_size); 721 } 722 } 723 724 /* 725 * The real mode trampoline, which is required for bootstrapping CPUs 726 * occupies only a small area under the low 1MB. See reserve_real_mode() 727 * for details. 728 * 729 * If KASLR is disabled the first PGD entry of the direct mapping is copied 730 * to map the real mode trampoline. 731 * 732 * If KASLR is enabled, copy only the PUD which covers the low 1MB 733 * area. This limits the randomization granularity to 1GB for both 4-level 734 * and 5-level paging. 735 */ 736 static void __init init_trampoline(void) 737 { 738 #ifdef CONFIG_X86_64 739 /* 740 * The code below will alias kernel page-tables in the user-range of the 741 * address space, including the Global bit. So global TLB entries will 742 * be created when using the trampoline page-table. 743 */ 744 if (!kaslr_memory_enabled()) 745 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)]; 746 else 747 init_trampoline_kaslr(); 748 #endif 749 } 750 751 void __init init_mem_mapping(void) 752 { 753 unsigned long end; 754 755 pti_check_boottime_disable(); 756 probe_page_size_mask(); 757 setup_pcid(); 758 759 #ifdef CONFIG_X86_64 760 end = max_pfn << PAGE_SHIFT; 761 #else 762 end = max_low_pfn << PAGE_SHIFT; 763 #endif 764 765 /* the ISA range is always mapped regardless of memory holes */ 766 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL); 767 768 /* Init the trampoline, possibly with KASLR memory offset */ 769 init_trampoline(); 770 771 /* 772 * If the allocation is in bottom-up direction, we setup direct mapping 773 * in bottom-up, otherwise we setup direct mapping in top-down. 774 */ 775 if (memblock_bottom_up()) { 776 unsigned long kernel_end = __pa_symbol(_end); 777 778 /* 779 * we need two separate calls here. This is because we want to 780 * allocate page tables above the kernel. So we first map 781 * [kernel_end, end) to make memory above the kernel be mapped 782 * as soon as possible. And then use page tables allocated above 783 * the kernel to map [ISA_END_ADDRESS, kernel_end). 784 */ 785 memory_map_bottom_up(kernel_end, end); 786 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end); 787 } else { 788 memory_map_top_down(ISA_END_ADDRESS, end); 789 } 790 791 #ifdef CONFIG_X86_64 792 if (max_pfn > max_low_pfn) { 793 /* can we preserve max_low_pfn ?*/ 794 max_low_pfn = max_pfn; 795 } 796 #else 797 early_ioremap_page_table_range_init(); 798 #endif 799 800 load_cr3(swapper_pg_dir); 801 __flush_tlb_all(); 802 803 x86_init.hyper.init_mem_mapping(); 804 805 early_memtest(0, max_pfn_mapped << PAGE_SHIFT); 806 } 807 808 /* 809 * Initialize an mm_struct to be used during poking and a pointer to be used 810 * during patching. 811 */ 812 void __init poking_init(void) 813 { 814 spinlock_t *ptl; 815 pte_t *ptep; 816 817 poking_mm = mm_alloc(); 818 BUG_ON(!poking_mm); 819 820 /* Xen PV guests need the PGD to be pinned. */ 821 paravirt_enter_mmap(poking_mm); 822 823 /* 824 * Randomize the poking address, but make sure that the following page 825 * will be mapped at the same PMD. We need 2 pages, so find space for 3, 826 * and adjust the address if the PMD ends after the first one. 827 */ 828 poking_addr = TASK_UNMAPPED_BASE; 829 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 830 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) % 831 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE); 832 833 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0) 834 poking_addr += PAGE_SIZE; 835 836 /* 837 * We need to trigger the allocation of the page-tables that will be 838 * needed for poking now. Later, poking may be performed in an atomic 839 * section, which might cause allocation to fail. 840 */ 841 ptep = get_locked_pte(poking_mm, poking_addr, &ptl); 842 BUG_ON(!ptep); 843 pte_unmap_unlock(ptep, ptl); 844 } 845 846 /* 847 * devmem_is_allowed() checks to see if /dev/mem access to a certain address 848 * is valid. The argument is a physical page number. 849 * 850 * On x86, access has to be given to the first megabyte of RAM because that 851 * area traditionally contains BIOS code and data regions used by X, dosemu, 852 * and similar apps. Since they map the entire memory range, the whole range 853 * must be allowed (for mapping), but any areas that would otherwise be 854 * disallowed are flagged as being "zero filled" instead of rejected. 855 * Access has to be given to non-kernel-ram areas as well, these contain the 856 * PCI mmio resources as well as potential bios/acpi data regions. 857 */ 858 int devmem_is_allowed(unsigned long pagenr) 859 { 860 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE, 861 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE) 862 != REGION_DISJOINT) { 863 /* 864 * For disallowed memory regions in the low 1MB range, 865 * request that the page be shown as all zeros. 866 */ 867 if (pagenr < 256) 868 return 2; 869 870 return 0; 871 } 872 873 /* 874 * This must follow RAM test, since System RAM is considered a 875 * restricted resource under CONFIG_STRICT_DEVMEM. 876 */ 877 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) { 878 /* Low 1MB bypasses iomem restrictions. */ 879 if (pagenr < 256) 880 return 1; 881 882 return 0; 883 } 884 885 return 1; 886 } 887 888 void free_init_pages(const char *what, unsigned long begin, unsigned long end) 889 { 890 unsigned long begin_aligned, end_aligned; 891 892 /* Make sure boundaries are page aligned */ 893 begin_aligned = PAGE_ALIGN(begin); 894 end_aligned = end & PAGE_MASK; 895 896 if (WARN_ON(begin_aligned != begin || end_aligned != end)) { 897 begin = begin_aligned; 898 end = end_aligned; 899 } 900 901 if (begin >= end) 902 return; 903 904 /* 905 * If debugging page accesses then do not free this memory but 906 * mark them not present - any buggy init-section access will 907 * create a kernel page fault: 908 */ 909 if (debug_pagealloc_enabled()) { 910 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n", 911 begin, end - 1); 912 /* 913 * Inform kmemleak about the hole in the memory since the 914 * corresponding pages will be unmapped. 915 */ 916 kmemleak_free_part((void *)begin, end - begin); 917 set_memory_np(begin, (end - begin) >> PAGE_SHIFT); 918 } else { 919 /* 920 * We just marked the kernel text read only above, now that 921 * we are going to free part of that, we need to make that 922 * writeable and non-executable first. 923 */ 924 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT); 925 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT); 926 927 free_reserved_area((void *)begin, (void *)end, 928 POISON_FREE_INITMEM, what); 929 } 930 } 931 932 /* 933 * begin/end can be in the direct map or the "high kernel mapping" 934 * used for the kernel image only. free_init_pages() will do the 935 * right thing for either kind of address. 936 */ 937 void free_kernel_image_pages(const char *what, void *begin, void *end) 938 { 939 unsigned long begin_ul = (unsigned long)begin; 940 unsigned long end_ul = (unsigned long)end; 941 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT; 942 943 free_init_pages(what, begin_ul, end_ul); 944 945 /* 946 * PTI maps some of the kernel into userspace. For performance, 947 * this includes some kernel areas that do not contain secrets. 948 * Those areas might be adjacent to the parts of the kernel image 949 * being freed, which may contain secrets. Remove the "high kernel 950 * image mapping" for these freed areas, ensuring they are not even 951 * potentially vulnerable to Meltdown regardless of the specific 952 * optimizations PTI is currently using. 953 * 954 * The "noalias" prevents unmapping the direct map alias which is 955 * needed to access the freed pages. 956 * 957 * This is only valid for 64bit kernels. 32bit has only one mapping 958 * which can't be treated in this way for obvious reasons. 959 */ 960 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI)) 961 set_memory_np_noalias(begin_ul, len_pages); 962 } 963 964 void __ref free_initmem(void) 965 { 966 e820__reallocate_tables(); 967 968 mem_encrypt_free_decrypted_mem(); 969 970 free_kernel_image_pages("unused kernel image (initmem)", 971 &__init_begin, &__init_end); 972 } 973 974 #ifdef CONFIG_BLK_DEV_INITRD 975 void __init free_initrd_mem(unsigned long start, unsigned long end) 976 { 977 /* 978 * end could be not aligned, and We can not align that, 979 * decompressor could be confused by aligned initrd_end 980 * We already reserve the end partial page before in 981 * - i386_start_kernel() 982 * - x86_64_start_kernel() 983 * - relocate_initrd() 984 * So here We can do PAGE_ALIGN() safely to get partial page to be freed 985 */ 986 free_init_pages("initrd", start, PAGE_ALIGN(end)); 987 } 988 #endif 989 990 void __init zone_sizes_init(void) 991 { 992 unsigned long max_zone_pfns[MAX_NR_ZONES]; 993 994 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 995 996 #ifdef CONFIG_ZONE_DMA 997 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn); 998 #endif 999 #ifdef CONFIG_ZONE_DMA32 1000 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn); 1001 #endif 1002 max_zone_pfns[ZONE_NORMAL] = max_low_pfn; 1003 #ifdef CONFIG_HIGHMEM 1004 max_zone_pfns[ZONE_HIGHMEM] = max_pfn; 1005 #endif 1006 1007 free_area_init(max_zone_pfns); 1008 } 1009 1010 __visible DEFINE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate) = { 1011 .loaded_mm = &init_mm, 1012 .next_asid = 1, 1013 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */ 1014 }; 1015 1016 #ifdef CONFIG_ADDRESS_MASKING 1017 DEFINE_PER_CPU(u64, tlbstate_untag_mask); 1018 EXPORT_PER_CPU_SYMBOL(tlbstate_untag_mask); 1019 #endif 1020 1021 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) 1022 { 1023 /* entry 0 MUST be WB (hardwired to speed up translations) */ 1024 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB); 1025 1026 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry); 1027 __pte2cachemode_tbl[entry] = cache; 1028 } 1029 1030 #ifdef CONFIG_SWAP 1031 unsigned long arch_max_swapfile_size(void) 1032 { 1033 unsigned long pages; 1034 1035 pages = generic_max_swapfile_size(); 1036 1037 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) { 1038 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */ 1039 unsigned long long l1tf_limit = l1tf_pfn_limit(); 1040 /* 1041 * We encode swap offsets also with 3 bits below those for pfn 1042 * which makes the usable limit higher. 1043 */ 1044 #if CONFIG_PGTABLE_LEVELS > 2 1045 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT; 1046 #endif 1047 pages = min_t(unsigned long long, l1tf_limit, pages); 1048 } 1049 return pages; 1050 } 1051 #endif 1052 1053 #ifdef CONFIG_EXECMEM 1054 static struct execmem_info execmem_info __ro_after_init; 1055 1056 struct execmem_info __init *execmem_arch_setup(void) 1057 { 1058 unsigned long start, offset = 0; 1059 1060 if (kaslr_enabled()) 1061 offset = get_random_u32_inclusive(1, 1024) * PAGE_SIZE; 1062 1063 start = MODULES_VADDR + offset; 1064 1065 execmem_info = (struct execmem_info){ 1066 .ranges = { 1067 [EXECMEM_DEFAULT] = { 1068 .flags = EXECMEM_KASAN_SHADOW, 1069 .start = start, 1070 .end = MODULES_END, 1071 .pgprot = PAGE_KERNEL, 1072 .alignment = MODULE_ALIGN, 1073 }, 1074 }, 1075 }; 1076 1077 return &execmem_info; 1078 } 1079 #endif /* CONFIG_EXECMEM */ 1080