1 #include <linux/gfp.h> 2 #include <linux/initrd.h> 3 #include <linux/ioport.h> 4 #include <linux/swap.h> 5 #include <linux/memblock.h> 6 #include <linux/swapfile.h> 7 #include <linux/swapops.h> 8 #include <linux/kmemleak.h> 9 #include <linux/sched/task.h> 10 11 #include <asm/set_memory.h> 12 #include <asm/e820/api.h> 13 #include <asm/init.h> 14 #include <asm/page.h> 15 #include <asm/page_types.h> 16 #include <asm/sections.h> 17 #include <asm/setup.h> 18 #include <asm/tlbflush.h> 19 #include <asm/tlb.h> 20 #include <asm/proto.h> 21 #include <asm/dma.h> /* for MAX_DMA_PFN */ 22 #include <asm/microcode.h> 23 #include <asm/kaslr.h> 24 #include <asm/hypervisor.h> 25 #include <asm/cpufeature.h> 26 #include <asm/pti.h> 27 #include <asm/text-patching.h> 28 #include <asm/memtype.h> 29 30 /* 31 * We need to define the tracepoints somewhere, and tlb.c 32 * is only compiled when SMP=y. 33 */ 34 #include <trace/events/tlb.h> 35 36 #include "mm_internal.h" 37 38 /* 39 * Tables translating between page_cache_type_t and pte encoding. 40 * 41 * The default values are defined statically as minimal supported mode; 42 * WC and WT fall back to UC-. pat_init() updates these values to support 43 * more cache modes, WC and WT, when it is safe to do so. See pat_init() 44 * for the details. Note, __early_ioremap() used during early boot-time 45 * takes pgprot_t (pte encoding) and does not use these tables. 46 * 47 * Index into __cachemode2pte_tbl[] is the cachemode. 48 * 49 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte 50 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2. 51 */ 52 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = { 53 [_PAGE_CACHE_MODE_WB ] = 0 | 0 , 54 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD, 55 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD, 56 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD, 57 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD, 58 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD, 59 }; 60 61 unsigned long cachemode2protval(enum page_cache_mode pcm) 62 { 63 if (likely(pcm == 0)) 64 return 0; 65 return __cachemode2pte_tbl[pcm]; 66 } 67 EXPORT_SYMBOL(cachemode2protval); 68 69 static uint8_t __pte2cachemode_tbl[8] = { 70 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB, 71 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 72 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS, 73 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC, 74 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB, 75 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 76 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS, 77 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC, 78 }; 79 80 /* Check that the write-protect PAT entry is set for write-protect */ 81 bool x86_has_pat_wp(void) 82 { 83 return __pte2cachemode_tbl[_PAGE_CACHE_MODE_WP] == _PAGE_CACHE_MODE_WP; 84 } 85 86 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot) 87 { 88 unsigned long masked; 89 90 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK; 91 if (likely(masked == 0)) 92 return 0; 93 return __pte2cachemode_tbl[__pte2cm_idx(masked)]; 94 } 95 96 static unsigned long __initdata pgt_buf_start; 97 static unsigned long __initdata pgt_buf_end; 98 static unsigned long __initdata pgt_buf_top; 99 100 static unsigned long min_pfn_mapped; 101 102 static bool __initdata can_use_brk_pgt = true; 103 104 /* 105 * Pages returned are already directly mapped. 106 * 107 * Changing that is likely to break Xen, see commit: 108 * 109 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve 110 * 111 * for detailed information. 112 */ 113 __ref void *alloc_low_pages(unsigned int num) 114 { 115 unsigned long pfn; 116 int i; 117 118 if (after_bootmem) { 119 unsigned int order; 120 121 order = get_order((unsigned long)num << PAGE_SHIFT); 122 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 123 } 124 125 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) { 126 unsigned long ret = 0; 127 128 if (min_pfn_mapped < max_pfn_mapped) { 129 ret = memblock_phys_alloc_range( 130 PAGE_SIZE * num, PAGE_SIZE, 131 min_pfn_mapped << PAGE_SHIFT, 132 max_pfn_mapped << PAGE_SHIFT); 133 } 134 if (!ret && can_use_brk_pgt) 135 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE)); 136 137 if (!ret) 138 panic("alloc_low_pages: can not alloc memory"); 139 140 pfn = ret >> PAGE_SHIFT; 141 } else { 142 pfn = pgt_buf_end; 143 pgt_buf_end += num; 144 } 145 146 for (i = 0; i < num; i++) { 147 void *adr; 148 149 adr = __va((pfn + i) << PAGE_SHIFT); 150 clear_page(adr); 151 } 152 153 return __va(pfn << PAGE_SHIFT); 154 } 155 156 /* 157 * By default need to be able to allocate page tables below PGD firstly for 158 * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping. 159 * With KASLR memory randomization, depending on the machine e820 memory and the 160 * PUD alignment, twice that many pages may be needed when KASLR memory 161 * randomization is enabled. 162 */ 163 164 #ifndef CONFIG_X86_5LEVEL 165 #define INIT_PGD_PAGE_TABLES 3 166 #else 167 #define INIT_PGD_PAGE_TABLES 4 168 #endif 169 170 #ifndef CONFIG_RANDOMIZE_MEMORY 171 #define INIT_PGD_PAGE_COUNT (2 * INIT_PGD_PAGE_TABLES) 172 #else 173 #define INIT_PGD_PAGE_COUNT (4 * INIT_PGD_PAGE_TABLES) 174 #endif 175 176 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE) 177 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE); 178 void __init early_alloc_pgt_buf(void) 179 { 180 unsigned long tables = INIT_PGT_BUF_SIZE; 181 phys_addr_t base; 182 183 base = __pa(extend_brk(tables, PAGE_SIZE)); 184 185 pgt_buf_start = base >> PAGE_SHIFT; 186 pgt_buf_end = pgt_buf_start; 187 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT); 188 } 189 190 int after_bootmem; 191 192 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES); 193 194 struct map_range { 195 unsigned long start; 196 unsigned long end; 197 unsigned page_size_mask; 198 }; 199 200 static int page_size_mask; 201 202 /* 203 * Save some of cr4 feature set we're using (e.g. Pentium 4MB 204 * enable and PPro Global page enable), so that any CPU's that boot 205 * up after us can get the correct flags. Invoked on the boot CPU. 206 */ 207 static inline void cr4_set_bits_and_update_boot(unsigned long mask) 208 { 209 mmu_cr4_features |= mask; 210 if (trampoline_cr4_features) 211 *trampoline_cr4_features = mmu_cr4_features; 212 cr4_set_bits(mask); 213 } 214 215 static void __init probe_page_size_mask(void) 216 { 217 /* 218 * For pagealloc debugging, identity mapping will use small pages. 219 * This will simplify cpa(), which otherwise needs to support splitting 220 * large pages into small in interrupt context, etc. 221 */ 222 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled()) 223 page_size_mask |= 1 << PG_LEVEL_2M; 224 else 225 direct_gbpages = 0; 226 227 /* Enable PSE if available */ 228 if (boot_cpu_has(X86_FEATURE_PSE)) 229 cr4_set_bits_and_update_boot(X86_CR4_PSE); 230 231 /* Enable PGE if available */ 232 __supported_pte_mask &= ~_PAGE_GLOBAL; 233 if (boot_cpu_has(X86_FEATURE_PGE)) { 234 cr4_set_bits_and_update_boot(X86_CR4_PGE); 235 __supported_pte_mask |= _PAGE_GLOBAL; 236 } 237 238 /* By the default is everything supported: */ 239 __default_kernel_pte_mask = __supported_pte_mask; 240 /* Except when with PTI where the kernel is mostly non-Global: */ 241 if (cpu_feature_enabled(X86_FEATURE_PTI)) 242 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 243 244 /* Enable 1 GB linear kernel mappings if available: */ 245 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) { 246 printk(KERN_INFO "Using GB pages for direct mapping\n"); 247 page_size_mask |= 1 << PG_LEVEL_1G; 248 } else { 249 direct_gbpages = 0; 250 } 251 } 252 253 static void setup_pcid(void) 254 { 255 if (!IS_ENABLED(CONFIG_X86_64)) 256 return; 257 258 if (!boot_cpu_has(X86_FEATURE_PCID)) 259 return; 260 261 if (boot_cpu_has(X86_FEATURE_PGE)) { 262 /* 263 * This can't be cr4_set_bits_and_update_boot() -- the 264 * trampoline code can't handle CR4.PCIDE and it wouldn't 265 * do any good anyway. Despite the name, 266 * cr4_set_bits_and_update_boot() doesn't actually cause 267 * the bits in question to remain set all the way through 268 * the secondary boot asm. 269 * 270 * Instead, we brute-force it and set CR4.PCIDE manually in 271 * start_secondary(). 272 */ 273 cr4_set_bits(X86_CR4_PCIDE); 274 275 /* 276 * INVPCID's single-context modes (2/3) only work if we set 277 * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable 278 * on systems that have X86_CR4_PCIDE clear, or that have 279 * no INVPCID support at all. 280 */ 281 if (boot_cpu_has(X86_FEATURE_INVPCID)) 282 setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE); 283 } else { 284 /* 285 * flush_tlb_all(), as currently implemented, won't work if 286 * PCID is on but PGE is not. Since that combination 287 * doesn't exist on real hardware, there's no reason to try 288 * to fully support it, but it's polite to avoid corrupting 289 * data if we're on an improperly configured VM. 290 */ 291 setup_clear_cpu_cap(X86_FEATURE_PCID); 292 } 293 } 294 295 #ifdef CONFIG_X86_32 296 #define NR_RANGE_MR 3 297 #else /* CONFIG_X86_64 */ 298 #define NR_RANGE_MR 5 299 #endif 300 301 static int __meminit save_mr(struct map_range *mr, int nr_range, 302 unsigned long start_pfn, unsigned long end_pfn, 303 unsigned long page_size_mask) 304 { 305 if (start_pfn < end_pfn) { 306 if (nr_range >= NR_RANGE_MR) 307 panic("run out of range for init_memory_mapping\n"); 308 mr[nr_range].start = start_pfn<<PAGE_SHIFT; 309 mr[nr_range].end = end_pfn<<PAGE_SHIFT; 310 mr[nr_range].page_size_mask = page_size_mask; 311 nr_range++; 312 } 313 314 return nr_range; 315 } 316 317 /* 318 * adjust the page_size_mask for small range to go with 319 * big page size instead small one if nearby are ram too. 320 */ 321 static void __ref adjust_range_page_size_mask(struct map_range *mr, 322 int nr_range) 323 { 324 int i; 325 326 for (i = 0; i < nr_range; i++) { 327 if ((page_size_mask & (1<<PG_LEVEL_2M)) && 328 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) { 329 unsigned long start = round_down(mr[i].start, PMD_SIZE); 330 unsigned long end = round_up(mr[i].end, PMD_SIZE); 331 332 #ifdef CONFIG_X86_32 333 if ((end >> PAGE_SHIFT) > max_low_pfn) 334 continue; 335 #endif 336 337 if (memblock_is_region_memory(start, end - start)) 338 mr[i].page_size_mask |= 1<<PG_LEVEL_2M; 339 } 340 if ((page_size_mask & (1<<PG_LEVEL_1G)) && 341 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) { 342 unsigned long start = round_down(mr[i].start, PUD_SIZE); 343 unsigned long end = round_up(mr[i].end, PUD_SIZE); 344 345 if (memblock_is_region_memory(start, end - start)) 346 mr[i].page_size_mask |= 1<<PG_LEVEL_1G; 347 } 348 } 349 } 350 351 static const char *page_size_string(struct map_range *mr) 352 { 353 static const char str_1g[] = "1G"; 354 static const char str_2m[] = "2M"; 355 static const char str_4m[] = "4M"; 356 static const char str_4k[] = "4k"; 357 358 if (mr->page_size_mask & (1<<PG_LEVEL_1G)) 359 return str_1g; 360 /* 361 * 32-bit without PAE has a 4M large page size. 362 * PG_LEVEL_2M is misnamed, but we can at least 363 * print out the right size in the string. 364 */ 365 if (IS_ENABLED(CONFIG_X86_32) && 366 !IS_ENABLED(CONFIG_X86_PAE) && 367 mr->page_size_mask & (1<<PG_LEVEL_2M)) 368 return str_4m; 369 370 if (mr->page_size_mask & (1<<PG_LEVEL_2M)) 371 return str_2m; 372 373 return str_4k; 374 } 375 376 static int __meminit split_mem_range(struct map_range *mr, int nr_range, 377 unsigned long start, 378 unsigned long end) 379 { 380 unsigned long start_pfn, end_pfn, limit_pfn; 381 unsigned long pfn; 382 int i; 383 384 limit_pfn = PFN_DOWN(end); 385 386 /* head if not big page alignment ? */ 387 pfn = start_pfn = PFN_DOWN(start); 388 #ifdef CONFIG_X86_32 389 /* 390 * Don't use a large page for the first 2/4MB of memory 391 * because there are often fixed size MTRRs in there 392 * and overlapping MTRRs into large pages can cause 393 * slowdowns. 394 */ 395 if (pfn == 0) 396 end_pfn = PFN_DOWN(PMD_SIZE); 397 else 398 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 399 #else /* CONFIG_X86_64 */ 400 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 401 #endif 402 if (end_pfn > limit_pfn) 403 end_pfn = limit_pfn; 404 if (start_pfn < end_pfn) { 405 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 406 pfn = end_pfn; 407 } 408 409 /* big page (2M) range */ 410 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 411 #ifdef CONFIG_X86_32 412 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 413 #else /* CONFIG_X86_64 */ 414 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 415 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE))) 416 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 417 #endif 418 419 if (start_pfn < end_pfn) { 420 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 421 page_size_mask & (1<<PG_LEVEL_2M)); 422 pfn = end_pfn; 423 } 424 425 #ifdef CONFIG_X86_64 426 /* big page (1G) range */ 427 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE)); 428 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE)); 429 if (start_pfn < end_pfn) { 430 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 431 page_size_mask & 432 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); 433 pfn = end_pfn; 434 } 435 436 /* tail is not big page (1G) alignment */ 437 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE)); 438 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE)); 439 if (start_pfn < end_pfn) { 440 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 441 page_size_mask & (1<<PG_LEVEL_2M)); 442 pfn = end_pfn; 443 } 444 #endif 445 446 /* tail is not big page (2M) alignment */ 447 start_pfn = pfn; 448 end_pfn = limit_pfn; 449 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 450 451 if (!after_bootmem) 452 adjust_range_page_size_mask(mr, nr_range); 453 454 /* try to merge same page size and continuous */ 455 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { 456 unsigned long old_start; 457 if (mr[i].end != mr[i+1].start || 458 mr[i].page_size_mask != mr[i+1].page_size_mask) 459 continue; 460 /* move it */ 461 old_start = mr[i].start; 462 memmove(&mr[i], &mr[i+1], 463 (nr_range - 1 - i) * sizeof(struct map_range)); 464 mr[i--].start = old_start; 465 nr_range--; 466 } 467 468 for (i = 0; i < nr_range; i++) 469 pr_debug(" [mem %#010lx-%#010lx] page %s\n", 470 mr[i].start, mr[i].end - 1, 471 page_size_string(&mr[i])); 472 473 return nr_range; 474 } 475 476 struct range pfn_mapped[E820_MAX_ENTRIES]; 477 int nr_pfn_mapped; 478 479 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn) 480 { 481 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES, 482 nr_pfn_mapped, start_pfn, end_pfn); 483 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES); 484 485 max_pfn_mapped = max(max_pfn_mapped, end_pfn); 486 487 if (start_pfn < (1UL<<(32-PAGE_SHIFT))) 488 max_low_pfn_mapped = max(max_low_pfn_mapped, 489 min(end_pfn, 1UL<<(32-PAGE_SHIFT))); 490 } 491 492 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn) 493 { 494 int i; 495 496 for (i = 0; i < nr_pfn_mapped; i++) 497 if ((start_pfn >= pfn_mapped[i].start) && 498 (end_pfn <= pfn_mapped[i].end)) 499 return true; 500 501 return false; 502 } 503 504 /* 505 * Setup the direct mapping of the physical memory at PAGE_OFFSET. 506 * This runs before bootmem is initialized and gets pages directly from 507 * the physical memory. To access them they are temporarily mapped. 508 */ 509 unsigned long __ref init_memory_mapping(unsigned long start, 510 unsigned long end, pgprot_t prot) 511 { 512 struct map_range mr[NR_RANGE_MR]; 513 unsigned long ret = 0; 514 int nr_range, i; 515 516 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n", 517 start, end - 1); 518 519 memset(mr, 0, sizeof(mr)); 520 nr_range = split_mem_range(mr, 0, start, end); 521 522 for (i = 0; i < nr_range; i++) 523 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end, 524 mr[i].page_size_mask, 525 prot); 526 527 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT); 528 529 return ret >> PAGE_SHIFT; 530 } 531 532 /* 533 * We need to iterate through the E820 memory map and create direct mappings 534 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply 535 * create direct mappings for all pfns from [0 to max_low_pfn) and 536 * [4GB to max_pfn) because of possible memory holes in high addresses 537 * that cannot be marked as UC by fixed/variable range MTRRs. 538 * Depending on the alignment of E820 ranges, this may possibly result 539 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables. 540 * 541 * init_mem_mapping() calls init_range_memory_mapping() with big range. 542 * That range would have hole in the middle or ends, and only ram parts 543 * will be mapped in init_range_memory_mapping(). 544 */ 545 static unsigned long __init init_range_memory_mapping( 546 unsigned long r_start, 547 unsigned long r_end) 548 { 549 unsigned long start_pfn, end_pfn; 550 unsigned long mapped_ram_size = 0; 551 int i; 552 553 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 554 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end); 555 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end); 556 if (start >= end) 557 continue; 558 559 /* 560 * if it is overlapping with brk pgt, we need to 561 * alloc pgt buf from memblock instead. 562 */ 563 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >= 564 min(end, (u64)pgt_buf_top<<PAGE_SHIFT); 565 init_memory_mapping(start, end, PAGE_KERNEL); 566 mapped_ram_size += end - start; 567 can_use_brk_pgt = true; 568 } 569 570 return mapped_ram_size; 571 } 572 573 static unsigned long __init get_new_step_size(unsigned long step_size) 574 { 575 /* 576 * Initial mapped size is PMD_SIZE (2M). 577 * We can not set step_size to be PUD_SIZE (1G) yet. 578 * In worse case, when we cross the 1G boundary, and 579 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k) 580 * to map 1G range with PTE. Hence we use one less than the 581 * difference of page table level shifts. 582 * 583 * Don't need to worry about overflow in the top-down case, on 32bit, 584 * when step_size is 0, round_down() returns 0 for start, and that 585 * turns it into 0x100000000ULL. 586 * In the bottom-up case, round_up(x, 0) returns 0 though too, which 587 * needs to be taken into consideration by the code below. 588 */ 589 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1); 590 } 591 592 /** 593 * memory_map_top_down - Map [map_start, map_end) top down 594 * @map_start: start address of the target memory range 595 * @map_end: end address of the target memory range 596 * 597 * This function will setup direct mapping for memory range 598 * [map_start, map_end) in top-down. That said, the page tables 599 * will be allocated at the end of the memory, and we map the 600 * memory in top-down. 601 */ 602 static void __init memory_map_top_down(unsigned long map_start, 603 unsigned long map_end) 604 { 605 unsigned long real_end, last_start; 606 unsigned long step_size; 607 unsigned long addr; 608 unsigned long mapped_ram_size = 0; 609 610 /* 611 * Systems that have many reserved areas near top of the memory, 612 * e.g. QEMU with less than 1G RAM and EFI enabled, or Xen, will 613 * require lots of 4K mappings which may exhaust pgt_buf. 614 * Start with top-most PMD_SIZE range aligned at PMD_SIZE to ensure 615 * there is enough mapped memory that can be allocated from 616 * memblock. 617 */ 618 addr = memblock_phys_alloc_range(PMD_SIZE, PMD_SIZE, map_start, 619 map_end); 620 memblock_phys_free(addr, PMD_SIZE); 621 real_end = addr + PMD_SIZE; 622 623 /* step_size need to be small so pgt_buf from BRK could cover it */ 624 step_size = PMD_SIZE; 625 max_pfn_mapped = 0; /* will get exact value next */ 626 min_pfn_mapped = real_end >> PAGE_SHIFT; 627 last_start = real_end; 628 629 /* 630 * We start from the top (end of memory) and go to the bottom. 631 * The memblock_find_in_range() gets us a block of RAM from the 632 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 633 * for page table. 634 */ 635 while (last_start > map_start) { 636 unsigned long start; 637 638 if (last_start > step_size) { 639 start = round_down(last_start - 1, step_size); 640 if (start < map_start) 641 start = map_start; 642 } else 643 start = map_start; 644 mapped_ram_size += init_range_memory_mapping(start, 645 last_start); 646 last_start = start; 647 min_pfn_mapped = last_start >> PAGE_SHIFT; 648 if (mapped_ram_size >= step_size) 649 step_size = get_new_step_size(step_size); 650 } 651 652 if (real_end < map_end) 653 init_range_memory_mapping(real_end, map_end); 654 } 655 656 /** 657 * memory_map_bottom_up - Map [map_start, map_end) bottom up 658 * @map_start: start address of the target memory range 659 * @map_end: end address of the target memory range 660 * 661 * This function will setup direct mapping for memory range 662 * [map_start, map_end) in bottom-up. Since we have limited the 663 * bottom-up allocation above the kernel, the page tables will 664 * be allocated just above the kernel and we map the memory 665 * in [map_start, map_end) in bottom-up. 666 */ 667 static void __init memory_map_bottom_up(unsigned long map_start, 668 unsigned long map_end) 669 { 670 unsigned long next, start; 671 unsigned long mapped_ram_size = 0; 672 /* step_size need to be small so pgt_buf from BRK could cover it */ 673 unsigned long step_size = PMD_SIZE; 674 675 start = map_start; 676 min_pfn_mapped = start >> PAGE_SHIFT; 677 678 /* 679 * We start from the bottom (@map_start) and go to the top (@map_end). 680 * The memblock_find_in_range() gets us a block of RAM from the 681 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages 682 * for page table. 683 */ 684 while (start < map_end) { 685 if (step_size && map_end - start > step_size) { 686 next = round_up(start + 1, step_size); 687 if (next > map_end) 688 next = map_end; 689 } else { 690 next = map_end; 691 } 692 693 mapped_ram_size += init_range_memory_mapping(start, next); 694 start = next; 695 696 if (mapped_ram_size >= step_size) 697 step_size = get_new_step_size(step_size); 698 } 699 } 700 701 /* 702 * The real mode trampoline, which is required for bootstrapping CPUs 703 * occupies only a small area under the low 1MB. See reserve_real_mode() 704 * for details. 705 * 706 * If KASLR is disabled the first PGD entry of the direct mapping is copied 707 * to map the real mode trampoline. 708 * 709 * If KASLR is enabled, copy only the PUD which covers the low 1MB 710 * area. This limits the randomization granularity to 1GB for both 4-level 711 * and 5-level paging. 712 */ 713 static void __init init_trampoline(void) 714 { 715 #ifdef CONFIG_X86_64 716 /* 717 * The code below will alias kernel page-tables in the user-range of the 718 * address space, including the Global bit. So global TLB entries will 719 * be created when using the trampoline page-table. 720 */ 721 if (!kaslr_memory_enabled()) 722 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)]; 723 else 724 init_trampoline_kaslr(); 725 #endif 726 } 727 728 void __init init_mem_mapping(void) 729 { 730 unsigned long end; 731 732 pti_check_boottime_disable(); 733 probe_page_size_mask(); 734 setup_pcid(); 735 736 #ifdef CONFIG_X86_64 737 end = max_pfn << PAGE_SHIFT; 738 #else 739 end = max_low_pfn << PAGE_SHIFT; 740 #endif 741 742 /* the ISA range is always mapped regardless of memory holes */ 743 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL); 744 745 /* Init the trampoline, possibly with KASLR memory offset */ 746 init_trampoline(); 747 748 /* 749 * If the allocation is in bottom-up direction, we setup direct mapping 750 * in bottom-up, otherwise we setup direct mapping in top-down. 751 */ 752 if (memblock_bottom_up()) { 753 unsigned long kernel_end = __pa_symbol(_end); 754 755 /* 756 * we need two separate calls here. This is because we want to 757 * allocate page tables above the kernel. So we first map 758 * [kernel_end, end) to make memory above the kernel be mapped 759 * as soon as possible. And then use page tables allocated above 760 * the kernel to map [ISA_END_ADDRESS, kernel_end). 761 */ 762 memory_map_bottom_up(kernel_end, end); 763 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end); 764 } else { 765 memory_map_top_down(ISA_END_ADDRESS, end); 766 } 767 768 #ifdef CONFIG_X86_64 769 if (max_pfn > max_low_pfn) { 770 /* can we preserve max_low_pfn ?*/ 771 max_low_pfn = max_pfn; 772 } 773 #else 774 early_ioremap_page_table_range_init(); 775 #endif 776 777 load_cr3(swapper_pg_dir); 778 __flush_tlb_all(); 779 780 x86_init.hyper.init_mem_mapping(); 781 782 early_memtest(0, max_pfn_mapped << PAGE_SHIFT); 783 } 784 785 /* 786 * Initialize an mm_struct to be used during poking and a pointer to be used 787 * during patching. 788 */ 789 void __init poking_init(void) 790 { 791 spinlock_t *ptl; 792 pte_t *ptep; 793 794 poking_mm = copy_init_mm(); 795 BUG_ON(!poking_mm); 796 797 /* 798 * Randomize the poking address, but make sure that the following page 799 * will be mapped at the same PMD. We need 2 pages, so find space for 3, 800 * and adjust the address if the PMD ends after the first one. 801 */ 802 poking_addr = TASK_UNMAPPED_BASE; 803 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 804 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) % 805 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE); 806 807 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0) 808 poking_addr += PAGE_SIZE; 809 810 /* 811 * We need to trigger the allocation of the page-tables that will be 812 * needed for poking now. Later, poking may be performed in an atomic 813 * section, which might cause allocation to fail. 814 */ 815 ptep = get_locked_pte(poking_mm, poking_addr, &ptl); 816 BUG_ON(!ptep); 817 pte_unmap_unlock(ptep, ptl); 818 } 819 820 /* 821 * devmem_is_allowed() checks to see if /dev/mem access to a certain address 822 * is valid. The argument is a physical page number. 823 * 824 * On x86, access has to be given to the first megabyte of RAM because that 825 * area traditionally contains BIOS code and data regions used by X, dosemu, 826 * and similar apps. Since they map the entire memory range, the whole range 827 * must be allowed (for mapping), but any areas that would otherwise be 828 * disallowed are flagged as being "zero filled" instead of rejected. 829 * Access has to be given to non-kernel-ram areas as well, these contain the 830 * PCI mmio resources as well as potential bios/acpi data regions. 831 */ 832 int devmem_is_allowed(unsigned long pagenr) 833 { 834 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE, 835 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE) 836 != REGION_DISJOINT) { 837 /* 838 * For disallowed memory regions in the low 1MB range, 839 * request that the page be shown as all zeros. 840 */ 841 if (pagenr < 256) 842 return 2; 843 844 return 0; 845 } 846 847 /* 848 * This must follow RAM test, since System RAM is considered a 849 * restricted resource under CONFIG_STRICT_IOMEM. 850 */ 851 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) { 852 /* Low 1MB bypasses iomem restrictions. */ 853 if (pagenr < 256) 854 return 1; 855 856 return 0; 857 } 858 859 return 1; 860 } 861 862 void free_init_pages(const char *what, unsigned long begin, unsigned long end) 863 { 864 unsigned long begin_aligned, end_aligned; 865 866 /* Make sure boundaries are page aligned */ 867 begin_aligned = PAGE_ALIGN(begin); 868 end_aligned = end & PAGE_MASK; 869 870 if (WARN_ON(begin_aligned != begin || end_aligned != end)) { 871 begin = begin_aligned; 872 end = end_aligned; 873 } 874 875 if (begin >= end) 876 return; 877 878 /* 879 * If debugging page accesses then do not free this memory but 880 * mark them not present - any buggy init-section access will 881 * create a kernel page fault: 882 */ 883 if (debug_pagealloc_enabled()) { 884 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n", 885 begin, end - 1); 886 /* 887 * Inform kmemleak about the hole in the memory since the 888 * corresponding pages will be unmapped. 889 */ 890 kmemleak_free_part((void *)begin, end - begin); 891 set_memory_np(begin, (end - begin) >> PAGE_SHIFT); 892 } else { 893 /* 894 * We just marked the kernel text read only above, now that 895 * we are going to free part of that, we need to make that 896 * writeable and non-executable first. 897 */ 898 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT); 899 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT); 900 901 free_reserved_area((void *)begin, (void *)end, 902 POISON_FREE_INITMEM, what); 903 } 904 } 905 906 /* 907 * begin/end can be in the direct map or the "high kernel mapping" 908 * used for the kernel image only. free_init_pages() will do the 909 * right thing for either kind of address. 910 */ 911 void free_kernel_image_pages(const char *what, void *begin, void *end) 912 { 913 unsigned long begin_ul = (unsigned long)begin; 914 unsigned long end_ul = (unsigned long)end; 915 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT; 916 917 free_init_pages(what, begin_ul, end_ul); 918 919 /* 920 * PTI maps some of the kernel into userspace. For performance, 921 * this includes some kernel areas that do not contain secrets. 922 * Those areas might be adjacent to the parts of the kernel image 923 * being freed, which may contain secrets. Remove the "high kernel 924 * image mapping" for these freed areas, ensuring they are not even 925 * potentially vulnerable to Meltdown regardless of the specific 926 * optimizations PTI is currently using. 927 * 928 * The "noalias" prevents unmapping the direct map alias which is 929 * needed to access the freed pages. 930 * 931 * This is only valid for 64bit kernels. 32bit has only one mapping 932 * which can't be treated in this way for obvious reasons. 933 */ 934 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI)) 935 set_memory_np_noalias(begin_ul, len_pages); 936 } 937 938 void __ref free_initmem(void) 939 { 940 e820__reallocate_tables(); 941 942 mem_encrypt_free_decrypted_mem(); 943 944 free_kernel_image_pages("unused kernel image (initmem)", 945 &__init_begin, &__init_end); 946 } 947 948 #ifdef CONFIG_BLK_DEV_INITRD 949 void __init free_initrd_mem(unsigned long start, unsigned long end) 950 { 951 /* 952 * end could be not aligned, and We can not align that, 953 * decompressor could be confused by aligned initrd_end 954 * We already reserve the end partial page before in 955 * - i386_start_kernel() 956 * - x86_64_start_kernel() 957 * - relocate_initrd() 958 * So here We can do PAGE_ALIGN() safely to get partial page to be freed 959 */ 960 free_init_pages("initrd", start, PAGE_ALIGN(end)); 961 } 962 #endif 963 964 /* 965 * Calculate the precise size of the DMA zone (first 16 MB of RAM), 966 * and pass it to the MM layer - to help it set zone watermarks more 967 * accurately. 968 * 969 * Done on 64-bit systems only for the time being, although 32-bit systems 970 * might benefit from this as well. 971 */ 972 void __init memblock_find_dma_reserve(void) 973 { 974 #ifdef CONFIG_X86_64 975 u64 nr_pages = 0, nr_free_pages = 0; 976 unsigned long start_pfn, end_pfn; 977 phys_addr_t start_addr, end_addr; 978 int i; 979 u64 u; 980 981 /* 982 * Iterate over all memory ranges (free and reserved ones alike), 983 * to calculate the total number of pages in the first 16 MB of RAM: 984 */ 985 nr_pages = 0; 986 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) { 987 start_pfn = min(start_pfn, MAX_DMA_PFN); 988 end_pfn = min(end_pfn, MAX_DMA_PFN); 989 990 nr_pages += end_pfn - start_pfn; 991 } 992 993 /* 994 * Iterate over free memory ranges to calculate the number of free 995 * pages in the DMA zone, while not counting potential partial 996 * pages at the beginning or the end of the range: 997 */ 998 nr_free_pages = 0; 999 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) { 1000 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN); 1001 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN); 1002 1003 if (start_pfn < end_pfn) 1004 nr_free_pages += end_pfn - start_pfn; 1005 } 1006 1007 set_dma_reserve(nr_pages - nr_free_pages); 1008 #endif 1009 } 1010 1011 void __init zone_sizes_init(void) 1012 { 1013 unsigned long max_zone_pfns[MAX_NR_ZONES]; 1014 1015 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 1016 1017 #ifdef CONFIG_ZONE_DMA 1018 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn); 1019 #endif 1020 #ifdef CONFIG_ZONE_DMA32 1021 max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn); 1022 #endif 1023 max_zone_pfns[ZONE_NORMAL] = max_low_pfn; 1024 #ifdef CONFIG_HIGHMEM 1025 max_zone_pfns[ZONE_HIGHMEM] = max_pfn; 1026 #endif 1027 1028 free_area_init(max_zone_pfns); 1029 } 1030 1031 __visible DEFINE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate) = { 1032 .loaded_mm = &init_mm, 1033 .next_asid = 1, 1034 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */ 1035 }; 1036 1037 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) 1038 { 1039 /* entry 0 MUST be WB (hardwired to speed up translations) */ 1040 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB); 1041 1042 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry); 1043 __pte2cachemode_tbl[entry] = cache; 1044 } 1045 1046 #ifdef CONFIG_SWAP 1047 unsigned long max_swapfile_size(void) 1048 { 1049 unsigned long pages; 1050 1051 pages = generic_max_swapfile_size(); 1052 1053 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) { 1054 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */ 1055 unsigned long long l1tf_limit = l1tf_pfn_limit(); 1056 /* 1057 * We encode swap offsets also with 3 bits below those for pfn 1058 * which makes the usable limit higher. 1059 */ 1060 #if CONFIG_PGTABLE_LEVELS > 2 1061 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT; 1062 #endif 1063 pages = min_t(unsigned long long, l1tf_limit, pages); 1064 } 1065 return pages; 1066 } 1067 #endif 1068