1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AMD NUMA support. 4 * Discover the memory map and associated nodes. 5 * 6 * This version reads it directly from the AMD northbridge. 7 * 8 * Copyright 2002,2003 Andi Kleen, SuSE Labs. 9 */ 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/string.h> 13 #include <linux/nodemask.h> 14 #include <linux/memblock.h> 15 #include <linux/bootmem.h> 16 17 #include <asm/io.h> 18 #include <linux/pci_ids.h> 19 #include <linux/acpi.h> 20 #include <asm/types.h> 21 #include <asm/mmzone.h> 22 #include <asm/proto.h> 23 #include <asm/e820/api.h> 24 #include <asm/pci-direct.h> 25 #include <asm/numa.h> 26 #include <asm/mpspec.h> 27 #include <asm/apic.h> 28 #include <asm/amd_nb.h> 29 30 static unsigned char __initdata nodeids[8]; 31 32 static __init int find_northbridge(void) 33 { 34 int num; 35 36 for (num = 0; num < 32; num++) { 37 u32 header; 38 39 header = read_pci_config(0, num, 0, 0x00); 40 if (header != (PCI_VENDOR_ID_AMD | (0x1100<<16)) && 41 header != (PCI_VENDOR_ID_AMD | (0x1200<<16)) && 42 header != (PCI_VENDOR_ID_AMD | (0x1300<<16))) 43 continue; 44 45 header = read_pci_config(0, num, 1, 0x00); 46 if (header != (PCI_VENDOR_ID_AMD | (0x1101<<16)) && 47 header != (PCI_VENDOR_ID_AMD | (0x1201<<16)) && 48 header != (PCI_VENDOR_ID_AMD | (0x1301<<16))) 49 continue; 50 return num; 51 } 52 53 return -ENOENT; 54 } 55 56 int __init amd_numa_init(void) 57 { 58 u64 start = PFN_PHYS(0); 59 u64 end = PFN_PHYS(max_pfn); 60 unsigned numnodes; 61 u64 prevbase; 62 int i, j, nb; 63 u32 nodeid, reg; 64 unsigned int bits, cores, apicid_base; 65 66 if (!early_pci_allowed()) 67 return -EINVAL; 68 69 nb = find_northbridge(); 70 if (nb < 0) 71 return nb; 72 73 pr_info("Scanning NUMA topology in Northbridge %d\n", nb); 74 75 reg = read_pci_config(0, nb, 0, 0x60); 76 numnodes = ((reg >> 4) & 0xF) + 1; 77 if (numnodes <= 1) 78 return -ENOENT; 79 80 pr_info("Number of physical nodes %d\n", numnodes); 81 82 prevbase = 0; 83 for (i = 0; i < 8; i++) { 84 u64 base, limit; 85 86 base = read_pci_config(0, nb, 1, 0x40 + i*8); 87 limit = read_pci_config(0, nb, 1, 0x44 + i*8); 88 89 nodeids[i] = nodeid = limit & 7; 90 if ((base & 3) == 0) { 91 if (i < numnodes) 92 pr_info("Skipping disabled node %d\n", i); 93 continue; 94 } 95 if (nodeid >= numnodes) { 96 pr_info("Ignoring excess node %d (%Lx:%Lx)\n", nodeid, 97 base, limit); 98 continue; 99 } 100 101 if (!limit) { 102 pr_info("Skipping node entry %d (base %Lx)\n", 103 i, base); 104 continue; 105 } 106 if ((base >> 8) & 3 || (limit >> 8) & 3) { 107 pr_err("Node %d using interleaving mode %Lx/%Lx\n", 108 nodeid, (base >> 8) & 3, (limit >> 8) & 3); 109 return -EINVAL; 110 } 111 if (node_isset(nodeid, numa_nodes_parsed)) { 112 pr_info("Node %d already present, skipping\n", 113 nodeid); 114 continue; 115 } 116 117 limit >>= 16; 118 limit++; 119 limit <<= 24; 120 121 if (limit > end) 122 limit = end; 123 if (limit <= base) 124 continue; 125 126 base >>= 16; 127 base <<= 24; 128 129 if (base < start) 130 base = start; 131 if (limit > end) 132 limit = end; 133 if (limit == base) { 134 pr_err("Empty node %d\n", nodeid); 135 continue; 136 } 137 if (limit < base) { 138 pr_err("Node %d bogus settings %Lx-%Lx.\n", 139 nodeid, base, limit); 140 continue; 141 } 142 143 /* Could sort here, but pun for now. Should not happen anyroads. */ 144 if (prevbase > base) { 145 pr_err("Node map not sorted %Lx,%Lx\n", 146 prevbase, base); 147 return -EINVAL; 148 } 149 150 pr_info("Node %d MemBase %016Lx Limit %016Lx\n", 151 nodeid, base, limit); 152 153 prevbase = base; 154 numa_add_memblk(nodeid, base, limit); 155 node_set(nodeid, numa_nodes_parsed); 156 } 157 158 if (!nodes_weight(numa_nodes_parsed)) 159 return -ENOENT; 160 161 /* 162 * We seem to have valid NUMA configuration. Map apicids to nodes 163 * using the coreid bits from early_identify_cpu. 164 */ 165 bits = boot_cpu_data.x86_coreid_bits; 166 cores = 1 << bits; 167 apicid_base = 0; 168 169 /* 170 * get boot-time SMP configuration: 171 */ 172 early_get_smp_config(); 173 174 if (boot_cpu_physical_apicid > 0) { 175 pr_info("BSP APIC ID: %02x\n", boot_cpu_physical_apicid); 176 apicid_base = boot_cpu_physical_apicid; 177 } 178 179 for_each_node_mask(i, numa_nodes_parsed) 180 for (j = apicid_base; j < cores + apicid_base; j++) 181 set_apicid_to_node((i << bits) + j, i); 182 183 return 0; 184 } 185