1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_X86_H 3 #define ARCH_X86_KVM_X86_H 4 5 #include <linux/kvm_host.h> 6 #include <asm/fpu/xstate.h> 7 #include <asm/mce.h> 8 #include <asm/pvclock.h> 9 #include "kvm_cache_regs.h" 10 #include "kvm_emulate.h" 11 #include "cpuid.h" 12 13 #define KVM_MAX_MCE_BANKS 32 14 15 struct kvm_caps { 16 /* control of guest tsc rate supported? */ 17 bool has_tsc_control; 18 /* maximum supported tsc_khz for guests */ 19 u32 max_guest_tsc_khz; 20 /* number of bits of the fractional part of the TSC scaling ratio */ 21 u8 tsc_scaling_ratio_frac_bits; 22 /* maximum allowed value of TSC scaling ratio */ 23 u64 max_tsc_scaling_ratio; 24 /* 1ull << kvm_caps.tsc_scaling_ratio_frac_bits */ 25 u64 default_tsc_scaling_ratio; 26 /* bus lock detection supported? */ 27 bool has_bus_lock_exit; 28 /* notify VM exit supported? */ 29 bool has_notify_vmexit; 30 /* bit mask of VM types */ 31 u32 supported_vm_types; 32 33 u64 supported_mce_cap; 34 u64 supported_xcr0; 35 u64 supported_xss; 36 u64 supported_perf_cap; 37 38 u64 supported_quirks; 39 u64 inapplicable_quirks; 40 }; 41 42 struct kvm_host_values { 43 /* 44 * The host's raw MAXPHYADDR, i.e. the number of non-reserved physical 45 * address bits irrespective of features that repurpose legal bits, 46 * e.g. MKTME. 47 */ 48 u8 maxphyaddr; 49 50 u64 efer; 51 u64 xcr0; 52 u64 xss; 53 u64 arch_capabilities; 54 }; 55 56 void kvm_spurious_fault(void); 57 58 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \ 59 ({ \ 60 bool failed = (consistency_check); \ 61 if (failed) \ 62 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \ 63 failed; \ 64 }) 65 66 /* 67 * The first...last VMX feature MSRs that are emulated by KVM. This may or may 68 * not cover all known VMX MSRs, as KVM doesn't emulate an MSR until there's an 69 * associated feature that KVM supports for nested virtualization. 70 */ 71 #define KVM_FIRST_EMULATED_VMX_MSR MSR_IA32_VMX_BASIC 72 #define KVM_LAST_EMULATED_VMX_MSR MSR_IA32_VMX_VMFUNC 73 74 #define KVM_DEFAULT_PLE_GAP 128 75 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 76 #define KVM_DEFAULT_PLE_WINDOW_GROW 2 77 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0 78 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX 79 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX 80 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000 81 82 static inline unsigned int __grow_ple_window(unsigned int val, 83 unsigned int base, unsigned int modifier, unsigned int max) 84 { 85 u64 ret = val; 86 87 if (modifier < 1) 88 return base; 89 90 if (modifier < base) 91 ret *= modifier; 92 else 93 ret += modifier; 94 95 return min(ret, (u64)max); 96 } 97 98 static inline unsigned int __shrink_ple_window(unsigned int val, 99 unsigned int base, unsigned int modifier, unsigned int min) 100 { 101 if (modifier < 1) 102 return base; 103 104 if (modifier < base) 105 val /= modifier; 106 else 107 val -= modifier; 108 109 return max(val, min); 110 } 111 112 #define MSR_IA32_CR_PAT_DEFAULT \ 113 PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC) 114 115 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu); 116 int kvm_check_nested_events(struct kvm_vcpu *vcpu); 117 118 /* Forcibly leave the nested mode in cases like a vCPU reset */ 119 static inline void kvm_leave_nested(struct kvm_vcpu *vcpu) 120 { 121 kvm_x86_ops.nested_ops->leave_nested(vcpu); 122 } 123 124 /* 125 * If IBRS is advertised to the vCPU, KVM must flush the indirect branch 126 * predictors when transitioning from L2 to L1, as L1 expects hardware (KVM in 127 * this case) to provide separate predictor modes. Bare metal isolates the host 128 * from the guest, but doesn't isolate different guests from one another (in 129 * this case L1 and L2). The exception is if bare metal supports same mode IBRS, 130 * which offers protection within the same mode, and hence protects L1 from L2. 131 */ 132 static inline void kvm_nested_vmexit_handle_ibrs(struct kvm_vcpu *vcpu) 133 { 134 if (cpu_feature_enabled(X86_FEATURE_AMD_IBRS_SAME_MODE)) 135 return; 136 137 if (guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL) || 138 guest_cpu_cap_has(vcpu, X86_FEATURE_AMD_IBRS)) 139 indirect_branch_prediction_barrier(); 140 } 141 142 static inline bool kvm_vcpu_has_run(struct kvm_vcpu *vcpu) 143 { 144 return vcpu->arch.last_vmentry_cpu != -1; 145 } 146 147 static inline void kvm_set_mp_state(struct kvm_vcpu *vcpu, int mp_state) 148 { 149 vcpu->arch.mp_state = mp_state; 150 if (mp_state == KVM_MP_STATE_RUNNABLE) 151 vcpu->arch.pv.pv_unhalted = false; 152 } 153 154 static inline bool kvm_is_exception_pending(struct kvm_vcpu *vcpu) 155 { 156 return vcpu->arch.exception.pending || 157 vcpu->arch.exception_vmexit.pending || 158 kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); 159 } 160 161 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu) 162 { 163 vcpu->arch.exception.pending = false; 164 vcpu->arch.exception.injected = false; 165 vcpu->arch.exception_vmexit.pending = false; 166 } 167 168 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector, 169 bool soft) 170 { 171 vcpu->arch.interrupt.injected = true; 172 vcpu->arch.interrupt.soft = soft; 173 vcpu->arch.interrupt.nr = vector; 174 } 175 176 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu) 177 { 178 vcpu->arch.interrupt.injected = false; 179 } 180 181 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu) 182 { 183 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected || 184 vcpu->arch.nmi_injected; 185 } 186 187 static inline bool kvm_exception_is_soft(unsigned int nr) 188 { 189 return (nr == BP_VECTOR) || (nr == OF_VECTOR); 190 } 191 192 static inline bool is_protmode(struct kvm_vcpu *vcpu) 193 { 194 return kvm_is_cr0_bit_set(vcpu, X86_CR0_PE); 195 } 196 197 static inline bool is_long_mode(struct kvm_vcpu *vcpu) 198 { 199 #ifdef CONFIG_X86_64 200 return !!(vcpu->arch.efer & EFER_LMA); 201 #else 202 return false; 203 #endif 204 } 205 206 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu) 207 { 208 int cs_db, cs_l; 209 210 WARN_ON_ONCE(vcpu->arch.guest_state_protected); 211 212 if (!is_long_mode(vcpu)) 213 return false; 214 kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 215 return cs_l; 216 } 217 218 static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu) 219 { 220 /* 221 * If running with protected guest state, the CS register is not 222 * accessible. The hypercall register values will have had to been 223 * provided in 64-bit mode, so assume the guest is in 64-bit. 224 */ 225 return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu); 226 } 227 228 static inline bool x86_exception_has_error_code(unsigned int vector) 229 { 230 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) | 231 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) | 232 BIT(PF_VECTOR) | BIT(AC_VECTOR); 233 234 return (1U << vector) & exception_has_error_code; 235 } 236 237 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu) 238 { 239 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu; 240 } 241 242 static inline bool is_pae(struct kvm_vcpu *vcpu) 243 { 244 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PAE); 245 } 246 247 static inline bool is_pse(struct kvm_vcpu *vcpu) 248 { 249 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PSE); 250 } 251 252 static inline bool is_paging(struct kvm_vcpu *vcpu) 253 { 254 return likely(kvm_is_cr0_bit_set(vcpu, X86_CR0_PG)); 255 } 256 257 static inline bool is_pae_paging(struct kvm_vcpu *vcpu) 258 { 259 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu); 260 } 261 262 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) 263 { 264 return kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 57 : 48; 265 } 266 267 static inline u8 max_host_virt_addr_bits(void) 268 { 269 return kvm_cpu_cap_has(X86_FEATURE_LA57) ? 57 : 48; 270 } 271 272 /* 273 * x86 MSRs which contain linear addresses, x86 hidden segment bases, and 274 * IDT/GDT bases have static canonicality checks, the size of which depends 275 * only on the CPU's support for 5-level paging, rather than on the state of 276 * CR4.LA57. This applies to both WRMSR and to other instructions that set 277 * their values, e.g. SGDT. 278 * 279 * KVM passes through most of these MSRS and also doesn't intercept the 280 * instructions that set the hidden segment bases. 281 * 282 * Because of this, to be consistent with hardware, even if the guest doesn't 283 * have LA57 enabled in its CPUID, perform canonicality checks based on *host* 284 * support for 5 level paging. 285 * 286 * Finally, instructions which are related to MMU invalidation of a given 287 * linear address, also have a similar static canonical check on address. 288 * This allows for example to invalidate 5-level addresses of a guest from a 289 * host which uses 4-level paging. 290 */ 291 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu, 292 unsigned int flags) 293 { 294 if (flags & (X86EMUL_F_INVLPG | X86EMUL_F_MSR | X86EMUL_F_DT_LOAD)) 295 return !__is_canonical_address(la, max_host_virt_addr_bits()); 296 else 297 return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu)); 298 } 299 300 static inline bool is_noncanonical_msr_address(u64 la, struct kvm_vcpu *vcpu) 301 { 302 return is_noncanonical_address(la, vcpu, X86EMUL_F_MSR); 303 } 304 305 static inline bool is_noncanonical_base_address(u64 la, struct kvm_vcpu *vcpu) 306 { 307 return is_noncanonical_address(la, vcpu, X86EMUL_F_DT_LOAD); 308 } 309 310 static inline bool is_noncanonical_invlpg_address(u64 la, struct kvm_vcpu *vcpu) 311 { 312 return is_noncanonical_address(la, vcpu, X86EMUL_F_INVLPG); 313 } 314 315 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, 316 gva_t gva, gfn_t gfn, unsigned access) 317 { 318 u64 gen = kvm_memslots(vcpu->kvm)->generation; 319 320 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) 321 return; 322 323 /* 324 * If this is a shadow nested page table, the "GVA" is 325 * actually a nGPA. 326 */ 327 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK; 328 vcpu->arch.mmio_access = access; 329 vcpu->arch.mmio_gfn = gfn; 330 vcpu->arch.mmio_gen = gen; 331 } 332 333 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu) 334 { 335 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation; 336 } 337 338 /* 339 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we 340 * clear all mmio cache info. 341 */ 342 #define MMIO_GVA_ANY (~(gva_t)0) 343 344 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva) 345 { 346 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK)) 347 return; 348 349 vcpu->arch.mmio_gva = 0; 350 } 351 352 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva) 353 { 354 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva && 355 vcpu->arch.mmio_gva == (gva & PAGE_MASK)) 356 return true; 357 358 return false; 359 } 360 361 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 362 { 363 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn && 364 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT) 365 return true; 366 367 return false; 368 } 369 370 static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg) 371 { 372 unsigned long val = kvm_register_read_raw(vcpu, reg); 373 374 return is_64_bit_mode(vcpu) ? val : (u32)val; 375 } 376 377 static inline void kvm_register_write(struct kvm_vcpu *vcpu, 378 int reg, unsigned long val) 379 { 380 if (!is_64_bit_mode(vcpu)) 381 val = (u32)val; 382 return kvm_register_write_raw(vcpu, reg, val); 383 } 384 385 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk) 386 { 387 return !(kvm->arch.disabled_quirks & quirk); 388 } 389 390 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip); 391 392 u64 get_kvmclock_ns(struct kvm *kvm); 393 uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm); 394 bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp); 395 int kvm_guest_time_update(struct kvm_vcpu *v); 396 397 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 398 gva_t addr, void *val, unsigned int bytes, 399 struct x86_exception *exception); 400 401 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, 402 gva_t addr, void *val, unsigned int bytes, 403 struct x86_exception *exception); 404 405 int handle_ud(struct kvm_vcpu *vcpu); 406 407 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu, 408 struct kvm_queued_exception *ex); 409 410 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); 411 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 412 bool kvm_vector_hashing_enabled(void); 413 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code); 414 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 415 void *insn, int insn_len); 416 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 417 int emulation_type, void *insn, int insn_len); 418 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu); 419 fastpath_t handle_fastpath_hlt(struct kvm_vcpu *vcpu); 420 421 extern struct kvm_caps kvm_caps; 422 extern struct kvm_host_values kvm_host; 423 424 extern bool enable_pmu; 425 426 /* 427 * Get a filtered version of KVM's supported XCR0 that strips out dynamic 428 * features for which the current process doesn't (yet) have permission to use. 429 * This is intended to be used only when enumerating support to userspace, 430 * e.g. in KVM_GET_SUPPORTED_CPUID and KVM_CAP_XSAVE2, it does NOT need to be 431 * used to check/restrict guest behavior as KVM rejects KVM_SET_CPUID{2} if 432 * userspace attempts to enable unpermitted features. 433 */ 434 static inline u64 kvm_get_filtered_xcr0(void) 435 { 436 u64 permitted_xcr0 = kvm_caps.supported_xcr0; 437 438 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA); 439 440 if (permitted_xcr0 & XFEATURE_MASK_USER_DYNAMIC) { 441 permitted_xcr0 &= xstate_get_guest_group_perm(); 442 443 /* 444 * Treat XTILE_CFG as unsupported if the current process isn't 445 * allowed to use XTILE_DATA, as attempting to set XTILE_CFG in 446 * XCR0 without setting XTILE_DATA is architecturally illegal. 447 */ 448 if (!(permitted_xcr0 & XFEATURE_MASK_XTILE_DATA)) 449 permitted_xcr0 &= ~XFEATURE_MASK_XTILE_CFG; 450 } 451 return permitted_xcr0; 452 } 453 454 static inline bool kvm_mpx_supported(void) 455 { 456 return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)) 457 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); 458 } 459 460 extern unsigned int min_timer_period_us; 461 462 extern bool enable_vmware_backdoor; 463 464 extern int pi_inject_timer; 465 466 extern bool report_ignored_msrs; 467 468 extern bool eager_page_split; 469 470 static inline void kvm_pr_unimpl_wrmsr(struct kvm_vcpu *vcpu, u32 msr, u64 data) 471 { 472 if (report_ignored_msrs) 473 vcpu_unimpl(vcpu, "Unhandled WRMSR(0x%x) = 0x%llx\n", msr, data); 474 } 475 476 static inline void kvm_pr_unimpl_rdmsr(struct kvm_vcpu *vcpu, u32 msr) 477 { 478 if (report_ignored_msrs) 479 vcpu_unimpl(vcpu, "Unhandled RDMSR(0x%x)\n", msr); 480 } 481 482 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 483 { 484 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 485 vcpu->arch.virtual_tsc_shift); 486 } 487 488 /* Same "calling convention" as do_div: 489 * - divide (n << 32) by base 490 * - put result in n 491 * - return remainder 492 */ 493 #define do_shl32_div32(n, base) \ 494 ({ \ 495 u32 __quot, __rem; \ 496 asm("divl %2" : "=a" (__quot), "=d" (__rem) \ 497 : "rm" (base), "0" (0), "1" ((u32) n)); \ 498 n = __quot; \ 499 __rem; \ 500 }) 501 502 static inline bool kvm_mwait_in_guest(struct kvm *kvm) 503 { 504 return kvm->arch.mwait_in_guest; 505 } 506 507 static inline bool kvm_hlt_in_guest(struct kvm *kvm) 508 { 509 return kvm->arch.hlt_in_guest; 510 } 511 512 static inline bool kvm_pause_in_guest(struct kvm *kvm) 513 { 514 return kvm->arch.pause_in_guest; 515 } 516 517 static inline bool kvm_cstate_in_guest(struct kvm *kvm) 518 { 519 return kvm->arch.cstate_in_guest; 520 } 521 522 static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm) 523 { 524 return kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_ENABLED; 525 } 526 527 static __always_inline void kvm_before_interrupt(struct kvm_vcpu *vcpu, 528 enum kvm_intr_type intr) 529 { 530 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr); 531 } 532 533 static __always_inline void kvm_after_interrupt(struct kvm_vcpu *vcpu) 534 { 535 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0); 536 } 537 538 static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu) 539 { 540 return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI; 541 } 542 543 static inline bool kvm_pat_valid(u64 data) 544 { 545 if (data & 0xF8F8F8F8F8F8F8F8ull) 546 return false; 547 /* 0, 1, 4, 5, 6, 7 are valid values. */ 548 return (data | ((data & 0x0202020202020202ull) << 1)) == data; 549 } 550 551 static inline bool kvm_dr7_valid(u64 data) 552 { 553 /* Bits [63:32] are reserved */ 554 return !(data >> 32); 555 } 556 static inline bool kvm_dr6_valid(u64 data) 557 { 558 /* Bits [63:32] are reserved */ 559 return !(data >> 32); 560 } 561 562 /* 563 * Trigger machine check on the host. We assume all the MSRs are already set up 564 * by the CPU and that we still run on the same CPU as the MCE occurred on. 565 * We pass a fake environment to the machine check handler because we want 566 * the guest to be always treated like user space, no matter what context 567 * it used internally. 568 */ 569 static inline void kvm_machine_check(void) 570 { 571 #if defined(CONFIG_X86_MCE) 572 struct pt_regs regs = { 573 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 574 .flags = X86_EFLAGS_IF, 575 }; 576 577 do_machine_check(®s); 578 #endif 579 } 580 581 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu); 582 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu); 583 int kvm_spec_ctrl_test_value(u64 value); 584 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 585 struct x86_exception *e); 586 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva); 587 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); 588 589 enum kvm_msr_access { 590 MSR_TYPE_R = BIT(0), 591 MSR_TYPE_W = BIT(1), 592 MSR_TYPE_RW = MSR_TYPE_R | MSR_TYPE_W, 593 }; 594 595 /* 596 * Internal error codes that are used to indicate that MSR emulation encountered 597 * an error that should result in #GP in the guest, unless userspace handles it. 598 * Note, '1', '0', and negative numbers are off limits, as they are used by KVM 599 * as part of KVM's lightly documented internal KVM_RUN return codes. 600 * 601 * UNSUPPORTED - The MSR isn't supported, either because it is completely 602 * unknown to KVM, or because the MSR should not exist according 603 * to the vCPU model. 604 * 605 * FILTERED - Access to the MSR is denied by a userspace MSR filter. 606 */ 607 #define KVM_MSR_RET_UNSUPPORTED 2 608 #define KVM_MSR_RET_FILTERED 3 609 610 static inline bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 611 { 612 return !(cr4 & vcpu->arch.cr4_guest_rsvd_bits); 613 } 614 615 #define __cr4_reserved_bits(__cpu_has, __c) \ 616 ({ \ 617 u64 __reserved_bits = CR4_RESERVED_BITS; \ 618 \ 619 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ 620 __reserved_bits |= X86_CR4_OSXSAVE; \ 621 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \ 622 __reserved_bits |= X86_CR4_SMEP; \ 623 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \ 624 __reserved_bits |= X86_CR4_SMAP; \ 625 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \ 626 __reserved_bits |= X86_CR4_FSGSBASE; \ 627 if (!__cpu_has(__c, X86_FEATURE_PKU)) \ 628 __reserved_bits |= X86_CR4_PKE; \ 629 if (!__cpu_has(__c, X86_FEATURE_LA57)) \ 630 __reserved_bits |= X86_CR4_LA57; \ 631 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \ 632 __reserved_bits |= X86_CR4_UMIP; \ 633 if (!__cpu_has(__c, X86_FEATURE_VMX)) \ 634 __reserved_bits |= X86_CR4_VMXE; \ 635 if (!__cpu_has(__c, X86_FEATURE_PCID)) \ 636 __reserved_bits |= X86_CR4_PCIDE; \ 637 if (!__cpu_has(__c, X86_FEATURE_LAM)) \ 638 __reserved_bits |= X86_CR4_LAM_SUP; \ 639 __reserved_bits; \ 640 }) 641 642 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes, 643 void *dst); 644 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes, 645 void *dst); 646 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 647 unsigned int port, void *data, unsigned int count, 648 int in); 649 650 static inline bool user_exit_on_hypercall(struct kvm *kvm, unsigned long hc_nr) 651 { 652 return kvm->arch.hypercall_exit_enabled & BIT(hc_nr); 653 } 654 655 int ____kvm_emulate_hypercall(struct kvm_vcpu *vcpu, int cpl, 656 int (*complete_hypercall)(struct kvm_vcpu *)); 657 658 #define __kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall) \ 659 ({ \ 660 int __ret; \ 661 __ret = ____kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall); \ 662 \ 663 if (__ret > 0) \ 664 __ret = complete_hypercall(_vcpu); \ 665 __ret; \ 666 }) 667 668 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 669 670 #endif 671