1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_X86_H 3 #define ARCH_X86_KVM_X86_H 4 5 #include <linux/kvm_host.h> 6 #include <asm/fpu/xstate.h> 7 #include <asm/mce.h> 8 #include <asm/pvclock.h> 9 #include "kvm_cache_regs.h" 10 #include "kvm_emulate.h" 11 #include "cpuid.h" 12 13 #define KVM_MAX_MCE_BANKS 32 14 15 struct kvm_caps { 16 /* control of guest tsc rate supported? */ 17 bool has_tsc_control; 18 /* maximum supported tsc_khz for guests */ 19 u32 max_guest_tsc_khz; 20 /* number of bits of the fractional part of the TSC scaling ratio */ 21 u8 tsc_scaling_ratio_frac_bits; 22 /* maximum allowed value of TSC scaling ratio */ 23 u64 max_tsc_scaling_ratio; 24 /* 1ull << kvm_caps.tsc_scaling_ratio_frac_bits */ 25 u64 default_tsc_scaling_ratio; 26 /* bus lock detection supported? */ 27 bool has_bus_lock_exit; 28 /* notify VM exit supported? */ 29 bool has_notify_vmexit; 30 /* bit mask of VM types */ 31 u32 supported_vm_types; 32 33 u64 supported_mce_cap; 34 u64 supported_xcr0; 35 u64 supported_xss; 36 u64 supported_perf_cap; 37 38 u64 supported_quirks; 39 u64 inapplicable_quirks; 40 }; 41 42 struct kvm_host_values { 43 /* 44 * The host's raw MAXPHYADDR, i.e. the number of non-reserved physical 45 * address bits irrespective of features that repurpose legal bits, 46 * e.g. MKTME. 47 */ 48 u8 maxphyaddr; 49 50 u64 efer; 51 u64 xcr0; 52 u64 xss; 53 u64 arch_capabilities; 54 }; 55 56 void kvm_spurious_fault(void); 57 58 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \ 59 ({ \ 60 bool failed = (consistency_check); \ 61 if (failed) \ 62 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \ 63 failed; \ 64 }) 65 66 /* 67 * The first...last VMX feature MSRs that are emulated by KVM. This may or may 68 * not cover all known VMX MSRs, as KVM doesn't emulate an MSR until there's an 69 * associated feature that KVM supports for nested virtualization. 70 */ 71 #define KVM_FIRST_EMULATED_VMX_MSR MSR_IA32_VMX_BASIC 72 #define KVM_LAST_EMULATED_VMX_MSR MSR_IA32_VMX_VMFUNC 73 74 #define KVM_DEFAULT_PLE_GAP 128 75 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 76 #define KVM_DEFAULT_PLE_WINDOW_GROW 2 77 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0 78 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX 79 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX 80 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000 81 82 static inline unsigned int __grow_ple_window(unsigned int val, 83 unsigned int base, unsigned int modifier, unsigned int max) 84 { 85 u64 ret = val; 86 87 if (modifier < 1) 88 return base; 89 90 if (modifier < base) 91 ret *= modifier; 92 else 93 ret += modifier; 94 95 return min(ret, (u64)max); 96 } 97 98 static inline unsigned int __shrink_ple_window(unsigned int val, 99 unsigned int base, unsigned int modifier, unsigned int min) 100 { 101 if (modifier < 1) 102 return base; 103 104 if (modifier < base) 105 val /= modifier; 106 else 107 val -= modifier; 108 109 return max(val, min); 110 } 111 112 #define MSR_IA32_CR_PAT_DEFAULT \ 113 PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC) 114 115 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu); 116 int kvm_check_nested_events(struct kvm_vcpu *vcpu); 117 118 /* Forcibly leave the nested mode in cases like a vCPU reset */ 119 static inline void kvm_leave_nested(struct kvm_vcpu *vcpu) 120 { 121 kvm_x86_ops.nested_ops->leave_nested(vcpu); 122 } 123 124 static inline bool kvm_vcpu_has_run(struct kvm_vcpu *vcpu) 125 { 126 return vcpu->arch.last_vmentry_cpu != -1; 127 } 128 129 static inline void kvm_set_mp_state(struct kvm_vcpu *vcpu, int mp_state) 130 { 131 vcpu->arch.mp_state = mp_state; 132 if (mp_state == KVM_MP_STATE_RUNNABLE) 133 vcpu->arch.pv.pv_unhalted = false; 134 } 135 136 static inline bool kvm_is_exception_pending(struct kvm_vcpu *vcpu) 137 { 138 return vcpu->arch.exception.pending || 139 vcpu->arch.exception_vmexit.pending || 140 kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); 141 } 142 143 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu) 144 { 145 vcpu->arch.exception.pending = false; 146 vcpu->arch.exception.injected = false; 147 vcpu->arch.exception_vmexit.pending = false; 148 } 149 150 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector, 151 bool soft) 152 { 153 vcpu->arch.interrupt.injected = true; 154 vcpu->arch.interrupt.soft = soft; 155 vcpu->arch.interrupt.nr = vector; 156 } 157 158 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu) 159 { 160 vcpu->arch.interrupt.injected = false; 161 } 162 163 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu) 164 { 165 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected || 166 vcpu->arch.nmi_injected; 167 } 168 169 static inline bool kvm_exception_is_soft(unsigned int nr) 170 { 171 return (nr == BP_VECTOR) || (nr == OF_VECTOR); 172 } 173 174 static inline bool is_protmode(struct kvm_vcpu *vcpu) 175 { 176 return kvm_is_cr0_bit_set(vcpu, X86_CR0_PE); 177 } 178 179 static inline bool is_long_mode(struct kvm_vcpu *vcpu) 180 { 181 #ifdef CONFIG_X86_64 182 return !!(vcpu->arch.efer & EFER_LMA); 183 #else 184 return false; 185 #endif 186 } 187 188 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu) 189 { 190 int cs_db, cs_l; 191 192 WARN_ON_ONCE(vcpu->arch.guest_state_protected); 193 194 if (!is_long_mode(vcpu)) 195 return false; 196 kvm_x86_call(get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 197 return cs_l; 198 } 199 200 static inline bool is_64_bit_hypercall(struct kvm_vcpu *vcpu) 201 { 202 /* 203 * If running with protected guest state, the CS register is not 204 * accessible. The hypercall register values will have had to been 205 * provided in 64-bit mode, so assume the guest is in 64-bit. 206 */ 207 return vcpu->arch.guest_state_protected || is_64_bit_mode(vcpu); 208 } 209 210 static inline bool x86_exception_has_error_code(unsigned int vector) 211 { 212 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) | 213 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) | 214 BIT(PF_VECTOR) | BIT(AC_VECTOR); 215 216 return (1U << vector) & exception_has_error_code; 217 } 218 219 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu) 220 { 221 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu; 222 } 223 224 static inline bool is_pae(struct kvm_vcpu *vcpu) 225 { 226 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PAE); 227 } 228 229 static inline bool is_pse(struct kvm_vcpu *vcpu) 230 { 231 return kvm_is_cr4_bit_set(vcpu, X86_CR4_PSE); 232 } 233 234 static inline bool is_paging(struct kvm_vcpu *vcpu) 235 { 236 return likely(kvm_is_cr0_bit_set(vcpu, X86_CR0_PG)); 237 } 238 239 static inline bool is_pae_paging(struct kvm_vcpu *vcpu) 240 { 241 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu); 242 } 243 244 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) 245 { 246 return kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 57 : 48; 247 } 248 249 static inline u8 max_host_virt_addr_bits(void) 250 { 251 return kvm_cpu_cap_has(X86_FEATURE_LA57) ? 57 : 48; 252 } 253 254 /* 255 * x86 MSRs which contain linear addresses, x86 hidden segment bases, and 256 * IDT/GDT bases have static canonicality checks, the size of which depends 257 * only on the CPU's support for 5-level paging, rather than on the state of 258 * CR4.LA57. This applies to both WRMSR and to other instructions that set 259 * their values, e.g. SGDT. 260 * 261 * KVM passes through most of these MSRS and also doesn't intercept the 262 * instructions that set the hidden segment bases. 263 * 264 * Because of this, to be consistent with hardware, even if the guest doesn't 265 * have LA57 enabled in its CPUID, perform canonicality checks based on *host* 266 * support for 5 level paging. 267 * 268 * Finally, instructions which are related to MMU invalidation of a given 269 * linear address, also have a similar static canonical check on address. 270 * This allows for example to invalidate 5-level addresses of a guest from a 271 * host which uses 4-level paging. 272 */ 273 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu, 274 unsigned int flags) 275 { 276 if (flags & (X86EMUL_F_INVLPG | X86EMUL_F_MSR | X86EMUL_F_DT_LOAD)) 277 return !__is_canonical_address(la, max_host_virt_addr_bits()); 278 else 279 return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu)); 280 } 281 282 static inline bool is_noncanonical_msr_address(u64 la, struct kvm_vcpu *vcpu) 283 { 284 return is_noncanonical_address(la, vcpu, X86EMUL_F_MSR); 285 } 286 287 static inline bool is_noncanonical_base_address(u64 la, struct kvm_vcpu *vcpu) 288 { 289 return is_noncanonical_address(la, vcpu, X86EMUL_F_DT_LOAD); 290 } 291 292 static inline bool is_noncanonical_invlpg_address(u64 la, struct kvm_vcpu *vcpu) 293 { 294 return is_noncanonical_address(la, vcpu, X86EMUL_F_INVLPG); 295 } 296 297 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, 298 gva_t gva, gfn_t gfn, unsigned access) 299 { 300 u64 gen = kvm_memslots(vcpu->kvm)->generation; 301 302 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) 303 return; 304 305 /* 306 * If this is a shadow nested page table, the "GVA" is 307 * actually a nGPA. 308 */ 309 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK; 310 vcpu->arch.mmio_access = access; 311 vcpu->arch.mmio_gfn = gfn; 312 vcpu->arch.mmio_gen = gen; 313 } 314 315 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu) 316 { 317 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation; 318 } 319 320 /* 321 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we 322 * clear all mmio cache info. 323 */ 324 #define MMIO_GVA_ANY (~(gva_t)0) 325 326 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva) 327 { 328 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK)) 329 return; 330 331 vcpu->arch.mmio_gva = 0; 332 } 333 334 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva) 335 { 336 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva && 337 vcpu->arch.mmio_gva == (gva & PAGE_MASK)) 338 return true; 339 340 return false; 341 } 342 343 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 344 { 345 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn && 346 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT) 347 return true; 348 349 return false; 350 } 351 352 static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg) 353 { 354 unsigned long val = kvm_register_read_raw(vcpu, reg); 355 356 return is_64_bit_mode(vcpu) ? val : (u32)val; 357 } 358 359 static inline void kvm_register_write(struct kvm_vcpu *vcpu, 360 int reg, unsigned long val) 361 { 362 if (!is_64_bit_mode(vcpu)) 363 val = (u32)val; 364 return kvm_register_write_raw(vcpu, reg, val); 365 } 366 367 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk) 368 { 369 return !(kvm->arch.disabled_quirks & quirk); 370 } 371 372 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip); 373 374 u64 get_kvmclock_ns(struct kvm *kvm); 375 uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm); 376 bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp); 377 int kvm_guest_time_update(struct kvm_vcpu *v); 378 379 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 380 gva_t addr, void *val, unsigned int bytes, 381 struct x86_exception *exception); 382 383 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, 384 gva_t addr, void *val, unsigned int bytes, 385 struct x86_exception *exception); 386 387 int handle_ud(struct kvm_vcpu *vcpu); 388 389 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu, 390 struct kvm_queued_exception *ex); 391 392 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); 393 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 394 bool kvm_vector_hashing_enabled(void); 395 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code); 396 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 397 void *insn, int insn_len); 398 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 399 int emulation_type, void *insn, int insn_len); 400 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu); 401 fastpath_t handle_fastpath_hlt(struct kvm_vcpu *vcpu); 402 403 extern struct kvm_caps kvm_caps; 404 extern struct kvm_host_values kvm_host; 405 406 extern bool enable_pmu; 407 408 /* 409 * Get a filtered version of KVM's supported XCR0 that strips out dynamic 410 * features for which the current process doesn't (yet) have permission to use. 411 * This is intended to be used only when enumerating support to userspace, 412 * e.g. in KVM_GET_SUPPORTED_CPUID and KVM_CAP_XSAVE2, it does NOT need to be 413 * used to check/restrict guest behavior as KVM rejects KVM_SET_CPUID{2} if 414 * userspace attempts to enable unpermitted features. 415 */ 416 static inline u64 kvm_get_filtered_xcr0(void) 417 { 418 u64 permitted_xcr0 = kvm_caps.supported_xcr0; 419 420 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA); 421 422 if (permitted_xcr0 & XFEATURE_MASK_USER_DYNAMIC) { 423 permitted_xcr0 &= xstate_get_guest_group_perm(); 424 425 /* 426 * Treat XTILE_CFG as unsupported if the current process isn't 427 * allowed to use XTILE_DATA, as attempting to set XTILE_CFG in 428 * XCR0 without setting XTILE_DATA is architecturally illegal. 429 */ 430 if (!(permitted_xcr0 & XFEATURE_MASK_XTILE_DATA)) 431 permitted_xcr0 &= ~XFEATURE_MASK_XTILE_CFG; 432 } 433 return permitted_xcr0; 434 } 435 436 static inline bool kvm_mpx_supported(void) 437 { 438 return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)) 439 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); 440 } 441 442 extern unsigned int min_timer_period_us; 443 444 extern bool enable_vmware_backdoor; 445 446 extern int pi_inject_timer; 447 448 extern bool report_ignored_msrs; 449 450 extern bool eager_page_split; 451 452 static inline void kvm_pr_unimpl_wrmsr(struct kvm_vcpu *vcpu, u32 msr, u64 data) 453 { 454 if (report_ignored_msrs) 455 vcpu_unimpl(vcpu, "Unhandled WRMSR(0x%x) = 0x%llx\n", msr, data); 456 } 457 458 static inline void kvm_pr_unimpl_rdmsr(struct kvm_vcpu *vcpu, u32 msr) 459 { 460 if (report_ignored_msrs) 461 vcpu_unimpl(vcpu, "Unhandled RDMSR(0x%x)\n", msr); 462 } 463 464 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 465 { 466 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 467 vcpu->arch.virtual_tsc_shift); 468 } 469 470 /* Same "calling convention" as do_div: 471 * - divide (n << 32) by base 472 * - put result in n 473 * - return remainder 474 */ 475 #define do_shl32_div32(n, base) \ 476 ({ \ 477 u32 __quot, __rem; \ 478 asm("divl %2" : "=a" (__quot), "=d" (__rem) \ 479 : "rm" (base), "0" (0), "1" ((u32) n)); \ 480 n = __quot; \ 481 __rem; \ 482 }) 483 484 static inline bool kvm_mwait_in_guest(struct kvm *kvm) 485 { 486 return kvm->arch.mwait_in_guest; 487 } 488 489 static inline bool kvm_hlt_in_guest(struct kvm *kvm) 490 { 491 return kvm->arch.hlt_in_guest; 492 } 493 494 static inline bool kvm_pause_in_guest(struct kvm *kvm) 495 { 496 return kvm->arch.pause_in_guest; 497 } 498 499 static inline bool kvm_cstate_in_guest(struct kvm *kvm) 500 { 501 return kvm->arch.cstate_in_guest; 502 } 503 504 static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm) 505 { 506 return kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_ENABLED; 507 } 508 509 static __always_inline void kvm_before_interrupt(struct kvm_vcpu *vcpu, 510 enum kvm_intr_type intr) 511 { 512 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr); 513 } 514 515 static __always_inline void kvm_after_interrupt(struct kvm_vcpu *vcpu) 516 { 517 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0); 518 } 519 520 static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu) 521 { 522 return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI; 523 } 524 525 static inline bool kvm_pat_valid(u64 data) 526 { 527 if (data & 0xF8F8F8F8F8F8F8F8ull) 528 return false; 529 /* 0, 1, 4, 5, 6, 7 are valid values. */ 530 return (data | ((data & 0x0202020202020202ull) << 1)) == data; 531 } 532 533 static inline bool kvm_dr7_valid(u64 data) 534 { 535 /* Bits [63:32] are reserved */ 536 return !(data >> 32); 537 } 538 static inline bool kvm_dr6_valid(u64 data) 539 { 540 /* Bits [63:32] are reserved */ 541 return !(data >> 32); 542 } 543 544 /* 545 * Trigger machine check on the host. We assume all the MSRs are already set up 546 * by the CPU and that we still run on the same CPU as the MCE occurred on. 547 * We pass a fake environment to the machine check handler because we want 548 * the guest to be always treated like user space, no matter what context 549 * it used internally. 550 */ 551 static inline void kvm_machine_check(void) 552 { 553 #if defined(CONFIG_X86_MCE) 554 struct pt_regs regs = { 555 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 556 .flags = X86_EFLAGS_IF, 557 }; 558 559 do_machine_check(®s); 560 #endif 561 } 562 563 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu); 564 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu); 565 int kvm_spec_ctrl_test_value(u64 value); 566 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 567 struct x86_exception *e); 568 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva); 569 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); 570 571 enum kvm_msr_access { 572 MSR_TYPE_R = BIT(0), 573 MSR_TYPE_W = BIT(1), 574 MSR_TYPE_RW = MSR_TYPE_R | MSR_TYPE_W, 575 }; 576 577 /* 578 * Internal error codes that are used to indicate that MSR emulation encountered 579 * an error that should result in #GP in the guest, unless userspace handles it. 580 * Note, '1', '0', and negative numbers are off limits, as they are used by KVM 581 * as part of KVM's lightly documented internal KVM_RUN return codes. 582 * 583 * UNSUPPORTED - The MSR isn't supported, either because it is completely 584 * unknown to KVM, or because the MSR should not exist according 585 * to the vCPU model. 586 * 587 * FILTERED - Access to the MSR is denied by a userspace MSR filter. 588 */ 589 #define KVM_MSR_RET_UNSUPPORTED 2 590 #define KVM_MSR_RET_FILTERED 3 591 592 static inline bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 593 { 594 return !(cr4 & vcpu->arch.cr4_guest_rsvd_bits); 595 } 596 597 #define __cr4_reserved_bits(__cpu_has, __c) \ 598 ({ \ 599 u64 __reserved_bits = CR4_RESERVED_BITS; \ 600 \ 601 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ 602 __reserved_bits |= X86_CR4_OSXSAVE; \ 603 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \ 604 __reserved_bits |= X86_CR4_SMEP; \ 605 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \ 606 __reserved_bits |= X86_CR4_SMAP; \ 607 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \ 608 __reserved_bits |= X86_CR4_FSGSBASE; \ 609 if (!__cpu_has(__c, X86_FEATURE_PKU)) \ 610 __reserved_bits |= X86_CR4_PKE; \ 611 if (!__cpu_has(__c, X86_FEATURE_LA57)) \ 612 __reserved_bits |= X86_CR4_LA57; \ 613 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \ 614 __reserved_bits |= X86_CR4_UMIP; \ 615 if (!__cpu_has(__c, X86_FEATURE_VMX)) \ 616 __reserved_bits |= X86_CR4_VMXE; \ 617 if (!__cpu_has(__c, X86_FEATURE_PCID)) \ 618 __reserved_bits |= X86_CR4_PCIDE; \ 619 if (!__cpu_has(__c, X86_FEATURE_LAM)) \ 620 __reserved_bits |= X86_CR4_LAM_SUP; \ 621 __reserved_bits; \ 622 }) 623 624 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes, 625 void *dst); 626 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes, 627 void *dst); 628 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 629 unsigned int port, void *data, unsigned int count, 630 int in); 631 632 static inline bool user_exit_on_hypercall(struct kvm *kvm, unsigned long hc_nr) 633 { 634 return kvm->arch.hypercall_exit_enabled & BIT(hc_nr); 635 } 636 637 int ____kvm_emulate_hypercall(struct kvm_vcpu *vcpu, int cpl, 638 int (*complete_hypercall)(struct kvm_vcpu *)); 639 640 #define __kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall) \ 641 ({ \ 642 int __ret; \ 643 __ret = ____kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall); \ 644 \ 645 if (__ret > 0) \ 646 __ret = complete_hypercall(_vcpu); \ 647 __ret; \ 648 }) 649 650 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 651 652 #endif 653