1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_X86_H 3 #define ARCH_X86_KVM_X86_H 4 5 #include <linux/kvm_host.h> 6 #include <asm/fpu/xstate.h> 7 #include <asm/mce.h> 8 #include <asm/pvclock.h> 9 #include "regs.h" 10 #include "kvm_emulate.h" 11 #include "cpuid.h" 12 13 #define KVM_MAX_MCE_BANKS 32 14 15 struct kvm_caps { 16 /* control of guest tsc rate supported? */ 17 bool has_tsc_control; 18 /* maximum supported tsc_khz for guests */ 19 u32 max_guest_tsc_khz; 20 /* number of bits of the fractional part of the TSC scaling ratio */ 21 u8 tsc_scaling_ratio_frac_bits; 22 /* maximum allowed value of TSC scaling ratio */ 23 u64 max_tsc_scaling_ratio; 24 /* 1ull << kvm_caps.tsc_scaling_ratio_frac_bits */ 25 u64 default_tsc_scaling_ratio; 26 /* bus lock detection supported? */ 27 bool has_bus_lock_exit; 28 /* notify VM exit supported? */ 29 bool has_notify_vmexit; 30 /* bit mask of VM types */ 31 u32 supported_vm_types; 32 33 u64 supported_mce_cap; 34 u64 supported_xcr0; 35 u64 supported_xss; 36 u64 supported_perf_cap; 37 38 u64 supported_quirks; 39 u64 inapplicable_quirks; 40 }; 41 42 struct kvm_host_values { 43 /* 44 * The host's raw MAXPHYADDR, i.e. the number of non-reserved physical 45 * address bits irrespective of features that repurpose legal bits, 46 * e.g. MKTME. 47 */ 48 u8 maxphyaddr; 49 50 u64 efer; 51 u64 xcr0; 52 u64 xss; 53 u64 s_cet; 54 u64 arch_capabilities; 55 }; 56 57 void kvm_spurious_fault(void); 58 59 #define SIZE_OF_MEMSLOTS_HASHTABLE \ 60 (sizeof(((struct kvm_memslots *)0)->id_hash) * 2 * KVM_MAX_NR_ADDRESS_SPACES) 61 62 /* Sanity check the size of the memslot hash tables. */ 63 static_assert(SIZE_OF_MEMSLOTS_HASHTABLE == 64 (1024 * (1 + IS_ENABLED(CONFIG_X86_64)) * (1 + IS_ENABLED(CONFIG_KVM_SMM)))); 65 66 /* 67 * Assert that "struct kvm_{svm,vmx,tdx}" is an order-0 or order-1 allocation. 68 * Spilling over to an order-2 allocation isn't fundamentally problematic, but 69 * isn't expected to happen in the foreseeable future (O(years)). Assert that 70 * the size is an order-0 allocation when ignoring the memslot hash tables, to 71 * help detect and debug unexpected size increases. 72 */ 73 #define KVM_SANITY_CHECK_VM_STRUCT_SIZE(x) \ 74 do { \ 75 BUILD_BUG_ON(get_order(sizeof(struct x) - SIZE_OF_MEMSLOTS_HASHTABLE) && \ 76 !IS_ENABLED(CONFIG_DEBUG_KERNEL) && !IS_ENABLED(CONFIG_KASAN)); \ 77 BUILD_BUG_ON(get_order(sizeof(struct x)) > 1 && \ 78 !IS_ENABLED(CONFIG_DEBUG_KERNEL) && !IS_ENABLED(CONFIG_KASAN)); \ 79 } while (0) 80 81 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \ 82 ({ \ 83 bool failed = (consistency_check); \ 84 if (failed) \ 85 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \ 86 failed; \ 87 }) 88 89 /* 90 * The first...last VMX feature MSRs that are emulated by KVM. This may or may 91 * not cover all known VMX MSRs, as KVM doesn't emulate an MSR until there's an 92 * associated feature that KVM supports for nested virtualization. 93 */ 94 #define KVM_FIRST_EMULATED_VMX_MSR MSR_IA32_VMX_BASIC 95 #define KVM_LAST_EMULATED_VMX_MSR MSR_IA32_VMX_VMFUNC 96 97 #define KVM_DEFAULT_PLE_GAP 128 98 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 99 #define KVM_DEFAULT_PLE_WINDOW_GROW 2 100 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0 101 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX 102 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX 103 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000 104 105 /* 106 * KVM's internal, non-ABI indices for synthetic MSRs. The values themselves 107 * are arbitrary and have no meaning, the only requirement is that they don't 108 * conflict with "real" MSRs that KVM supports. Use values at the upper end 109 * of KVM's reserved paravirtual MSR range to minimize churn, i.e. these values 110 * will be usable until KVM exhausts its supply of paravirtual MSR indices. 111 */ 112 113 #define MSR_KVM_INTERNAL_GUEST_SSP 0x4b564dff 114 115 static inline unsigned int __grow_ple_window(unsigned int val, 116 unsigned int base, unsigned int modifier, unsigned int max) 117 { 118 u64 ret = val; 119 120 if (modifier < 1) 121 return base; 122 123 if (modifier < base) 124 ret *= modifier; 125 else 126 ret += modifier; 127 128 return min(ret, (u64)max); 129 } 130 131 static inline unsigned int __shrink_ple_window(unsigned int val, 132 unsigned int base, unsigned int modifier, unsigned int min) 133 { 134 if (modifier < 1) 135 return base; 136 137 if (modifier < base) 138 val /= modifier; 139 else 140 val -= modifier; 141 142 return max(val, min); 143 } 144 145 #define MSR_IA32_CR_PAT_DEFAULT \ 146 PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC) 147 148 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu); 149 int kvm_check_nested_events(struct kvm_vcpu *vcpu); 150 151 /* Forcibly leave the nested mode in cases like a vCPU reset */ 152 static inline void kvm_leave_nested(struct kvm_vcpu *vcpu) 153 { 154 kvm_x86_ops.nested_ops->leave_nested(vcpu); 155 } 156 157 /* 158 * If IBRS is advertised to the vCPU, KVM must flush the indirect branch 159 * predictors when transitioning from L2 to L1, as L1 expects hardware (KVM in 160 * this case) to provide separate predictor modes. Bare metal isolates the host 161 * from the guest, but doesn't isolate different guests from one another (in 162 * this case L1 and L2). The exception is if bare metal supports same mode IBRS, 163 * which offers protection within the same mode, and hence protects L1 from L2. 164 */ 165 static inline void kvm_nested_vmexit_handle_ibrs(struct kvm_vcpu *vcpu) 166 { 167 if (cpu_feature_enabled(X86_FEATURE_AMD_IBRS_SAME_MODE)) 168 return; 169 170 if (guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL) || 171 guest_cpu_cap_has(vcpu, X86_FEATURE_AMD_IBRS)) 172 indirect_branch_prediction_barrier(); 173 } 174 175 /* 176 * Disallow modifying CPUID and feature MSRs, which affect the core virtual CPU 177 * model exposed to the guest and virtualized by KVM, if the vCPU has already 178 * run or is in guest mode (L2). In both cases, KVM has already consumed the 179 * current virtual CPU model, and doesn't support "unwinding" to react to the 180 * new model. 181 * 182 * Note, the only way is_guest_mode() can be true with 'last_vmentry_cpu == -1' 183 * is if userspace sets CPUID and feature MSRs (to enable VMX/SVM), then sets 184 * nested state, and then attempts to set CPUID and/or feature MSRs *again*. 185 */ 186 static inline bool kvm_can_set_cpuid_and_feature_msrs(struct kvm_vcpu *vcpu) 187 { 188 return vcpu->arch.last_vmentry_cpu == -1 && !is_guest_mode(vcpu); 189 } 190 191 /* 192 * WARN if a nested VM-Enter is pending completion, and userspace hasn't gained 193 * control since the nested VM-Enter was initiated (in which case, userspace 194 * may have modified vCPU state to induce an architecturally invalid VM-Exit). 195 */ 196 static inline void kvm_warn_on_nested_run_pending(struct kvm_vcpu *vcpu) 197 { 198 WARN_ON_ONCE(vcpu->arch.nested_run_pending == KVM_NESTED_RUN_PENDING); 199 } 200 201 static inline void kvm_set_mp_state(struct kvm_vcpu *vcpu, int mp_state) 202 { 203 vcpu->arch.mp_state = mp_state; 204 if (mp_state == KVM_MP_STATE_RUNNABLE) 205 vcpu->arch.pv.pv_unhalted = false; 206 } 207 208 static inline bool kvm_is_exception_pending(struct kvm_vcpu *vcpu) 209 { 210 return vcpu->arch.exception.pending || 211 vcpu->arch.exception_vmexit.pending || 212 kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); 213 } 214 215 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu) 216 { 217 vcpu->arch.exception.pending = false; 218 vcpu->arch.exception.injected = false; 219 vcpu->arch.exception_vmexit.pending = false; 220 } 221 222 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector, 223 bool soft) 224 { 225 vcpu->arch.interrupt.injected = true; 226 vcpu->arch.interrupt.soft = soft; 227 vcpu->arch.interrupt.nr = vector; 228 } 229 230 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu) 231 { 232 vcpu->arch.interrupt.injected = false; 233 } 234 235 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu) 236 { 237 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected || 238 vcpu->arch.nmi_injected; 239 } 240 241 static inline bool kvm_exception_is_soft(unsigned int nr) 242 { 243 return (nr == BP_VECTOR) || (nr == OF_VECTOR); 244 } 245 246 static inline bool x86_exception_has_error_code(unsigned int vector) 247 { 248 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) | 249 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) | 250 BIT(PF_VECTOR) | BIT(AC_VECTOR); 251 252 return (1U << vector) & exception_has_error_code; 253 } 254 255 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu) 256 { 257 return vcpu->arch.mmu == &vcpu->arch.guest_mmu; 258 } 259 260 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) 261 { 262 return kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 57 : 48; 263 } 264 265 static inline u8 max_host_virt_addr_bits(void) 266 { 267 return kvm_cpu_cap_has(X86_FEATURE_LA57) ? 57 : 48; 268 } 269 270 /* 271 * x86 MSRs which contain linear addresses, x86 hidden segment bases, and 272 * IDT/GDT bases have static canonicality checks, the size of which depends 273 * only on the CPU's support for 5-level paging, rather than on the state of 274 * CR4.LA57. This applies to both WRMSR and to other instructions that set 275 * their values, e.g. SGDT. 276 * 277 * KVM passes through most of these MSRS and also doesn't intercept the 278 * instructions that set the hidden segment bases. 279 * 280 * Because of this, to be consistent with hardware, even if the guest doesn't 281 * have LA57 enabled in its CPUID, perform canonicality checks based on *host* 282 * support for 5 level paging. 283 * 284 * Finally, instructions which are related to MMU invalidation of a given 285 * linear address, also have a similar static canonical check on address. 286 * This allows for example to invalidate 5-level addresses of a guest from a 287 * host which uses 4-level paging. 288 */ 289 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu, 290 unsigned int flags) 291 { 292 if (flags & (X86EMUL_F_INVLPG | X86EMUL_F_MSR | X86EMUL_F_DT_LOAD)) 293 return !__is_canonical_address(la, max_host_virt_addr_bits()); 294 else 295 return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu)); 296 } 297 298 static inline bool is_noncanonical_msr_address(u64 la, struct kvm_vcpu *vcpu) 299 { 300 return is_noncanonical_address(la, vcpu, X86EMUL_F_MSR); 301 } 302 303 static inline bool is_noncanonical_base_address(u64 la, struct kvm_vcpu *vcpu) 304 { 305 return is_noncanonical_address(la, vcpu, X86EMUL_F_DT_LOAD); 306 } 307 308 static inline bool is_noncanonical_invlpg_address(u64 la, struct kvm_vcpu *vcpu) 309 { 310 return is_noncanonical_address(la, vcpu, X86EMUL_F_INVLPG); 311 } 312 313 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, 314 gva_t gva, gfn_t gfn, unsigned access) 315 { 316 u64 gen = kvm_memslots(vcpu->kvm)->generation; 317 318 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) 319 return; 320 321 /* 322 * If this is a shadow nested page table, the "GVA" is 323 * actually a nGPA. 324 */ 325 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK; 326 vcpu->arch.mmio_access = access; 327 vcpu->arch.mmio_gfn = gfn; 328 vcpu->arch.mmio_gen = gen; 329 } 330 331 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu) 332 { 333 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation; 334 } 335 336 /* 337 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we 338 * clear all mmio cache info. 339 */ 340 #define MMIO_GVA_ANY (~(gva_t)0) 341 342 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva) 343 { 344 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK)) 345 return; 346 347 vcpu->arch.mmio_gva = 0; 348 } 349 350 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva) 351 { 352 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva && 353 vcpu->arch.mmio_gva == (gva & PAGE_MASK)) 354 return true; 355 356 return false; 357 } 358 359 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 360 { 361 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn && 362 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT) 363 return true; 364 365 return false; 366 } 367 368 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk) 369 { 370 return !(kvm->arch.disabled_quirks & quirk); 371 } 372 373 static __always_inline void kvm_request_l1tf_flush_l1d(void) 374 { 375 #if IS_ENABLED(CONFIG_CPU_MITIGATIONS) && IS_ENABLED(CONFIG_KVM_INTEL) 376 /* 377 * Use a raw write to set the per-CPU flag, as KVM will ensure a flush 378 * even if preemption is currently enabled.. If the current vCPU task 379 * is migrated to a different CPU (or userspace runs the vCPU on a 380 * different task) before the next VM-Entry, then kvm_arch_vcpu_load() 381 * will request a flush on the new CPU. 382 */ 383 raw_cpu_write(irq_stat.kvm_cpu_l1tf_flush_l1d, 1); 384 #endif 385 } 386 387 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip); 388 389 u64 get_kvmclock_ns(struct kvm *kvm); 390 uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm); 391 bool kvm_get_monotonic_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp); 392 int kvm_guest_time_update(struct kvm_vcpu *v); 393 394 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 395 gva_t addr, void *val, unsigned int bytes, 396 struct x86_exception *exception); 397 398 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, 399 gva_t addr, void *val, unsigned int bytes, 400 struct x86_exception *exception); 401 402 int handle_ud(struct kvm_vcpu *vcpu); 403 404 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu, 405 struct kvm_queued_exception *ex); 406 407 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); 408 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 409 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code); 410 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 411 void *insn, int insn_len); 412 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 413 int emulation_type, void *insn, int insn_len); 414 fastpath_t handle_fastpath_wrmsr(struct kvm_vcpu *vcpu); 415 fastpath_t handle_fastpath_wrmsr_imm(struct kvm_vcpu *vcpu, u32 msr, int reg); 416 fastpath_t handle_fastpath_hlt(struct kvm_vcpu *vcpu); 417 fastpath_t handle_fastpath_invd(struct kvm_vcpu *vcpu); 418 419 extern struct kvm_caps kvm_caps; 420 extern struct kvm_host_values kvm_host; 421 422 void kvm_setup_xss_caps(void); 423 424 /* 425 * Get a filtered version of KVM's supported XCR0 that strips out dynamic 426 * features for which the current process doesn't (yet) have permission to use. 427 * This is intended to be used only when enumerating support to userspace, 428 * e.g. in KVM_GET_SUPPORTED_CPUID and KVM_CAP_XSAVE2, it does NOT need to be 429 * used to check/restrict guest behavior as KVM rejects KVM_SET_CPUID{2} if 430 * userspace attempts to enable unpermitted features. 431 */ 432 static inline u64 kvm_get_filtered_xcr0(void) 433 { 434 u64 permitted_xcr0 = kvm_caps.supported_xcr0; 435 436 BUILD_BUG_ON(XFEATURE_MASK_USER_DYNAMIC != XFEATURE_MASK_XTILE_DATA); 437 438 if (permitted_xcr0 & XFEATURE_MASK_USER_DYNAMIC) { 439 permitted_xcr0 &= xstate_get_guest_group_perm(); 440 441 /* 442 * Treat XTILE_CFG as unsupported if the current process isn't 443 * allowed to use XTILE_DATA, as attempting to set XTILE_CFG in 444 * XCR0 without setting XTILE_DATA is architecturally illegal. 445 */ 446 if (!(permitted_xcr0 & XFEATURE_MASK_XTILE_DATA)) 447 permitted_xcr0 &= ~XFEATURE_MASK_XTILE_CFG; 448 } 449 return permitted_xcr0; 450 } 451 452 static inline bool kvm_mpx_supported(void) 453 { 454 return (kvm_caps.supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)) 455 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); 456 } 457 458 extern unsigned int min_timer_period_us; 459 460 extern bool enable_vmware_backdoor; 461 462 extern int pi_inject_timer; 463 464 extern bool report_ignored_msrs; 465 466 extern bool eager_page_split; 467 468 static inline void kvm_pr_unimpl_wrmsr(struct kvm_vcpu *vcpu, u32 msr, u64 data) 469 { 470 if (report_ignored_msrs) 471 vcpu_unimpl(vcpu, "Unhandled WRMSR(0x%x) = 0x%llx\n", msr, data); 472 } 473 474 static inline void kvm_pr_unimpl_rdmsr(struct kvm_vcpu *vcpu, u32 msr) 475 { 476 if (report_ignored_msrs) 477 vcpu_unimpl(vcpu, "Unhandled RDMSR(0x%x)\n", msr); 478 } 479 480 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 481 { 482 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 483 vcpu->arch.virtual_tsc_shift); 484 } 485 486 /* Same "calling convention" as do_div: 487 * - divide (n << 32) by base 488 * - put result in n 489 * - return remainder 490 */ 491 #define do_shl32_div32(n, base) \ 492 ({ \ 493 u32 __quot, __rem; \ 494 asm("divl %2" : "=a" (__quot), "=d" (__rem) \ 495 : "rm" (base), "0" (0), "1" ((u32) n)); \ 496 n = __quot; \ 497 __rem; \ 498 }) 499 500 static inline void kvm_disable_exits(struct kvm *kvm, u64 mask) 501 { 502 kvm->arch.disabled_exits |= mask; 503 } 504 505 static inline bool kvm_mwait_in_guest(struct kvm *kvm) 506 { 507 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_MWAIT; 508 } 509 510 static inline bool kvm_hlt_in_guest(struct kvm *kvm) 511 { 512 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_HLT; 513 } 514 515 static inline bool kvm_pause_in_guest(struct kvm *kvm) 516 { 517 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_PAUSE; 518 } 519 520 static inline bool kvm_cstate_in_guest(struct kvm *kvm) 521 { 522 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_CSTATE; 523 } 524 525 static inline bool kvm_aperfmperf_in_guest(struct kvm *kvm) 526 { 527 return kvm->arch.disabled_exits & KVM_X86_DISABLE_EXITS_APERFMPERF; 528 } 529 530 static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm) 531 { 532 return kvm->arch.notify_vmexit_flags & KVM_X86_NOTIFY_VMEXIT_ENABLED; 533 } 534 535 static __always_inline void kvm_before_interrupt(struct kvm_vcpu *vcpu, 536 enum kvm_intr_type intr) 537 { 538 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, (u8)intr); 539 } 540 541 static __always_inline void kvm_after_interrupt(struct kvm_vcpu *vcpu) 542 { 543 WRITE_ONCE(vcpu->arch.handling_intr_from_guest, 0); 544 } 545 546 static inline bool kvm_handling_nmi_from_guest(struct kvm_vcpu *vcpu) 547 { 548 return vcpu->arch.handling_intr_from_guest == KVM_HANDLING_NMI; 549 } 550 551 static inline bool kvm_pat_valid(u64 data) 552 { 553 if (data & 0xF8F8F8F8F8F8F8F8ull) 554 return false; 555 /* 0, 1, 4, 5, 6, 7 are valid values. */ 556 return (data | ((data & 0x0202020202020202ull) << 1)) == data; 557 } 558 559 static inline bool __kvm_pv_async_pf_enabled(u64 data) 560 { 561 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; 562 563 return (data & mask) == mask; 564 } 565 566 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) 567 { 568 return __kvm_pv_async_pf_enabled(vcpu->arch.apf.msr_en_val); 569 } 570 571 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) 572 { 573 int i; 574 for (i = 0; i < ASYNC_PF_PER_VCPU; i++) 575 vcpu->arch.apf.gfns[i] = ~0; 576 } 577 578 /* 579 * Trigger machine check on the host. We assume all the MSRs are already set up 580 * by the CPU and that we still run on the same CPU as the MCE occurred on. 581 * We pass a fake environment to the machine check handler because we want 582 * the guest to be always treated like user space, no matter what context 583 * it used internally. 584 */ 585 static inline void kvm_machine_check(void) 586 { 587 #if defined(CONFIG_X86_MCE) 588 struct pt_regs regs = { 589 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 590 .flags = X86_EFLAGS_IF, 591 }; 592 593 do_machine_check(®s); 594 #endif 595 } 596 597 int kvm_spec_ctrl_test_value(u64 value); 598 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 599 struct x86_exception *e); 600 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva); 601 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); 602 603 enum kvm_msr_access { 604 MSR_TYPE_R = BIT(0), 605 MSR_TYPE_W = BIT(1), 606 MSR_TYPE_RW = MSR_TYPE_R | MSR_TYPE_W, 607 }; 608 609 /* 610 * Internal error codes that are used to indicate that MSR emulation encountered 611 * an error that should result in #GP in the guest, unless userspace handles it. 612 * Note, '1', '0', and negative numbers are off limits, as they are used by KVM 613 * as part of KVM's lightly documented internal KVM_RUN return codes. 614 * 615 * UNSUPPORTED - The MSR isn't supported, either because it is completely 616 * unknown to KVM, or because the MSR should not exist according 617 * to the vCPU model. 618 * 619 * FILTERED - Access to the MSR is denied by a userspace MSR filter. 620 */ 621 #define KVM_MSR_RET_UNSUPPORTED 2 622 #define KVM_MSR_RET_FILTERED 3 623 624 int kvm_sev_es_mmio(struct kvm_vcpu *vcpu, bool is_write, gpa_t gpa, 625 unsigned int bytes, void *data); 626 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 627 unsigned int port, void *data, unsigned int count, 628 int in); 629 630 static inline void __kvm_prepare_emulated_mmio_exit(struct kvm_vcpu *vcpu, 631 gpa_t gpa, unsigned int len, 632 const void *data, 633 bool is_write) 634 { 635 struct kvm_run *run = vcpu->run; 636 637 KVM_BUG_ON(len > 8, vcpu->kvm); 638 639 run->mmio.len = len; 640 run->mmio.is_write = is_write; 641 run->exit_reason = KVM_EXIT_MMIO; 642 run->mmio.phys_addr = gpa; 643 if (is_write) 644 memcpy(run->mmio.data, data, len); 645 } 646 647 static inline void kvm_prepare_emulated_mmio_exit(struct kvm_vcpu *vcpu, 648 struct kvm_mmio_fragment *frag) 649 { 650 WARN_ON_ONCE(!vcpu->mmio_needed || !vcpu->mmio_nr_fragments); 651 652 __kvm_prepare_emulated_mmio_exit(vcpu, frag->gpa, min(8u, frag->len), 653 frag->data, vcpu->mmio_is_write); 654 } 655 656 static inline bool kvm_is_valid_map_gpa_range_ret(u64 hypercall_ret) 657 { 658 return !hypercall_ret || hypercall_ret == EINVAL || 659 hypercall_ret == EAGAIN; 660 } 661 662 static inline bool user_exit_on_hypercall(struct kvm *kvm, unsigned long hc_nr) 663 { 664 return kvm->arch.hypercall_exit_enabled & BIT(hc_nr); 665 } 666 667 int ____kvm_emulate_hypercall(struct kvm_vcpu *vcpu, int cpl, 668 int (*complete_hypercall)(struct kvm_vcpu *)); 669 670 #define __kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall) \ 671 ({ \ 672 int __ret; \ 673 __ret = ____kvm_emulate_hypercall(_vcpu, cpl, complete_hypercall); \ 674 \ 675 if (__ret > 0) \ 676 __ret = complete_hypercall(_vcpu); \ 677 __ret; \ 678 }) 679 680 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); 681 682 #define CET_US_RESERVED_BITS GENMASK(9, 6) 683 #define CET_US_SHSTK_MASK_BITS GENMASK(1, 0) 684 #define CET_US_IBT_MASK_BITS (GENMASK_ULL(5, 2) | GENMASK_ULL(63, 10)) 685 #define CET_US_LEGACY_BITMAP_BASE(data) ((data) >> 12) 686 687 static inline bool kvm_is_valid_u_s_cet(struct kvm_vcpu *vcpu, u64 data) 688 { 689 if (data & CET_US_RESERVED_BITS) 690 return false; 691 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_SHSTK) && 692 (data & CET_US_SHSTK_MASK_BITS)) 693 return false; 694 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_IBT) && 695 (data & CET_US_IBT_MASK_BITS)) 696 return false; 697 if (!IS_ALIGNED(CET_US_LEGACY_BITMAP_BASE(data), 4)) 698 return false; 699 /* IBT can be suppressed iff the TRACKER isn't WAIT_ENDBR. */ 700 if ((data & CET_SUPPRESS) && (data & CET_WAIT_ENDBR)) 701 return false; 702 703 return true; 704 } 705 #endif 706