1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef ARCH_X86_KVM_X86_H 3 #define ARCH_X86_KVM_X86_H 4 5 #include <linux/kvm_host.h> 6 #include <asm/mce.h> 7 #include <asm/pvclock.h> 8 #include "kvm_cache_regs.h" 9 #include "kvm_emulate.h" 10 11 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \ 12 ({ \ 13 bool failed = (consistency_check); \ 14 if (failed) \ 15 trace_kvm_nested_vmenter_failed(#consistency_check, 0); \ 16 failed; \ 17 }) 18 19 #define KVM_DEFAULT_PLE_GAP 128 20 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 21 #define KVM_DEFAULT_PLE_WINDOW_GROW 2 22 #define KVM_DEFAULT_PLE_WINDOW_SHRINK 0 23 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX UINT_MAX 24 #define KVM_SVM_DEFAULT_PLE_WINDOW_MAX USHRT_MAX 25 #define KVM_SVM_DEFAULT_PLE_WINDOW 3000 26 27 static inline unsigned int __grow_ple_window(unsigned int val, 28 unsigned int base, unsigned int modifier, unsigned int max) 29 { 30 u64 ret = val; 31 32 if (modifier < 1) 33 return base; 34 35 if (modifier < base) 36 ret *= modifier; 37 else 38 ret += modifier; 39 40 return min(ret, (u64)max); 41 } 42 43 static inline unsigned int __shrink_ple_window(unsigned int val, 44 unsigned int base, unsigned int modifier, unsigned int min) 45 { 46 if (modifier < 1) 47 return base; 48 49 if (modifier < base) 50 val /= modifier; 51 else 52 val -= modifier; 53 54 return max(val, min); 55 } 56 57 #define MSR_IA32_CR_PAT_DEFAULT 0x0007040600070406ULL 58 59 int kvm_check_nested_events(struct kvm_vcpu *vcpu); 60 61 static inline void kvm_clear_exception_queue(struct kvm_vcpu *vcpu) 62 { 63 vcpu->arch.exception.pending = false; 64 vcpu->arch.exception.injected = false; 65 } 66 67 static inline void kvm_queue_interrupt(struct kvm_vcpu *vcpu, u8 vector, 68 bool soft) 69 { 70 vcpu->arch.interrupt.injected = true; 71 vcpu->arch.interrupt.soft = soft; 72 vcpu->arch.interrupt.nr = vector; 73 } 74 75 static inline void kvm_clear_interrupt_queue(struct kvm_vcpu *vcpu) 76 { 77 vcpu->arch.interrupt.injected = false; 78 } 79 80 static inline bool kvm_event_needs_reinjection(struct kvm_vcpu *vcpu) 81 { 82 return vcpu->arch.exception.injected || vcpu->arch.interrupt.injected || 83 vcpu->arch.nmi_injected; 84 } 85 86 static inline bool kvm_exception_is_soft(unsigned int nr) 87 { 88 return (nr == BP_VECTOR) || (nr == OF_VECTOR); 89 } 90 91 static inline bool is_protmode(struct kvm_vcpu *vcpu) 92 { 93 return kvm_read_cr0_bits(vcpu, X86_CR0_PE); 94 } 95 96 static inline int is_long_mode(struct kvm_vcpu *vcpu) 97 { 98 #ifdef CONFIG_X86_64 99 return vcpu->arch.efer & EFER_LMA; 100 #else 101 return 0; 102 #endif 103 } 104 105 static inline bool is_64_bit_mode(struct kvm_vcpu *vcpu) 106 { 107 int cs_db, cs_l; 108 109 if (!is_long_mode(vcpu)) 110 return false; 111 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); 112 return cs_l; 113 } 114 115 static inline bool is_la57_mode(struct kvm_vcpu *vcpu) 116 { 117 #ifdef CONFIG_X86_64 118 return (vcpu->arch.efer & EFER_LMA) && 119 kvm_read_cr4_bits(vcpu, X86_CR4_LA57); 120 #else 121 return 0; 122 #endif 123 } 124 125 static inline bool x86_exception_has_error_code(unsigned int vector) 126 { 127 static u32 exception_has_error_code = BIT(DF_VECTOR) | BIT(TS_VECTOR) | 128 BIT(NP_VECTOR) | BIT(SS_VECTOR) | BIT(GP_VECTOR) | 129 BIT(PF_VECTOR) | BIT(AC_VECTOR); 130 131 return (1U << vector) & exception_has_error_code; 132 } 133 134 static inline bool mmu_is_nested(struct kvm_vcpu *vcpu) 135 { 136 return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu; 137 } 138 139 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) 140 { 141 ++vcpu->stat.tlb_flush; 142 static_call(kvm_x86_tlb_flush_current)(vcpu); 143 } 144 145 static inline int is_pae(struct kvm_vcpu *vcpu) 146 { 147 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE); 148 } 149 150 static inline int is_pse(struct kvm_vcpu *vcpu) 151 { 152 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE); 153 } 154 155 static inline int is_paging(struct kvm_vcpu *vcpu) 156 { 157 return likely(kvm_read_cr0_bits(vcpu, X86_CR0_PG)); 158 } 159 160 static inline bool is_pae_paging(struct kvm_vcpu *vcpu) 161 { 162 return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu); 163 } 164 165 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu) 166 { 167 return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48; 168 } 169 170 static inline u64 get_canonical(u64 la, u8 vaddr_bits) 171 { 172 return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits); 173 } 174 175 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu) 176 { 177 return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la; 178 } 179 180 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, 181 gva_t gva, gfn_t gfn, unsigned access) 182 { 183 u64 gen = kvm_memslots(vcpu->kvm)->generation; 184 185 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) 186 return; 187 188 /* 189 * If this is a shadow nested page table, the "GVA" is 190 * actually a nGPA. 191 */ 192 vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK; 193 vcpu->arch.mmio_access = access; 194 vcpu->arch.mmio_gfn = gfn; 195 vcpu->arch.mmio_gen = gen; 196 } 197 198 static inline bool vcpu_match_mmio_gen(struct kvm_vcpu *vcpu) 199 { 200 return vcpu->arch.mmio_gen == kvm_memslots(vcpu->kvm)->generation; 201 } 202 203 /* 204 * Clear the mmio cache info for the given gva. If gva is MMIO_GVA_ANY, we 205 * clear all mmio cache info. 206 */ 207 #define MMIO_GVA_ANY (~(gva_t)0) 208 209 static inline void vcpu_clear_mmio_info(struct kvm_vcpu *vcpu, gva_t gva) 210 { 211 if (gva != MMIO_GVA_ANY && vcpu->arch.mmio_gva != (gva & PAGE_MASK)) 212 return; 213 214 vcpu->arch.mmio_gva = 0; 215 } 216 217 static inline bool vcpu_match_mmio_gva(struct kvm_vcpu *vcpu, unsigned long gva) 218 { 219 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gva && 220 vcpu->arch.mmio_gva == (gva & PAGE_MASK)) 221 return true; 222 223 return false; 224 } 225 226 static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu *vcpu, gpa_t gpa) 227 { 228 if (vcpu_match_mmio_gen(vcpu) && vcpu->arch.mmio_gfn && 229 vcpu->arch.mmio_gfn == gpa >> PAGE_SHIFT) 230 return true; 231 232 return false; 233 } 234 235 static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int reg) 236 { 237 unsigned long val = kvm_register_read_raw(vcpu, reg); 238 239 return is_64_bit_mode(vcpu) ? val : (u32)val; 240 } 241 242 static inline void kvm_register_write(struct kvm_vcpu *vcpu, 243 int reg, unsigned long val) 244 { 245 if (!is_64_bit_mode(vcpu)) 246 val = (u32)val; 247 return kvm_register_write_raw(vcpu, reg, val); 248 } 249 250 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk) 251 { 252 return !(kvm->arch.disabled_quirks & quirk); 253 } 254 255 static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu) 256 { 257 return is_smm(vcpu) || static_call(kvm_x86_apic_init_signal_blocked)(vcpu); 258 } 259 260 void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs); 261 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip); 262 263 u64 get_kvmclock_ns(struct kvm *kvm); 264 265 int kvm_read_guest_virt(struct kvm_vcpu *vcpu, 266 gva_t addr, void *val, unsigned int bytes, 267 struct x86_exception *exception); 268 269 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, 270 gva_t addr, void *val, unsigned int bytes, 271 struct x86_exception *exception); 272 273 int handle_ud(struct kvm_vcpu *vcpu); 274 275 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu); 276 277 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu); 278 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); 279 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data); 280 int kvm_mtrr_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); 281 int kvm_mtrr_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); 282 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, 283 int page_num); 284 bool kvm_vector_hashing_enabled(void); 285 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code); 286 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, 287 void *insn, int insn_len); 288 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, 289 int emulation_type, void *insn, int insn_len); 290 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu); 291 292 extern u64 host_xcr0; 293 extern u64 supported_xcr0; 294 extern u64 host_xss; 295 extern u64 supported_xss; 296 297 static inline bool kvm_mpx_supported(void) 298 { 299 return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR)) 300 == (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); 301 } 302 303 extern unsigned int min_timer_period_us; 304 305 extern bool enable_vmware_backdoor; 306 307 extern int pi_inject_timer; 308 309 extern struct static_key kvm_no_apic_vcpu; 310 311 extern bool report_ignored_msrs; 312 313 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) 314 { 315 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult, 316 vcpu->arch.virtual_tsc_shift); 317 } 318 319 /* Same "calling convention" as do_div: 320 * - divide (n << 32) by base 321 * - put result in n 322 * - return remainder 323 */ 324 #define do_shl32_div32(n, base) \ 325 ({ \ 326 u32 __quot, __rem; \ 327 asm("divl %2" : "=a" (__quot), "=d" (__rem) \ 328 : "rm" (base), "0" (0), "1" ((u32) n)); \ 329 n = __quot; \ 330 __rem; \ 331 }) 332 333 static inline bool kvm_mwait_in_guest(struct kvm *kvm) 334 { 335 return kvm->arch.mwait_in_guest; 336 } 337 338 static inline bool kvm_hlt_in_guest(struct kvm *kvm) 339 { 340 return kvm->arch.hlt_in_guest; 341 } 342 343 static inline bool kvm_pause_in_guest(struct kvm *kvm) 344 { 345 return kvm->arch.pause_in_guest; 346 } 347 348 static inline bool kvm_cstate_in_guest(struct kvm *kvm) 349 { 350 return kvm->arch.cstate_in_guest; 351 } 352 353 DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu); 354 355 static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu) 356 { 357 __this_cpu_write(current_vcpu, vcpu); 358 } 359 360 static inline void kvm_after_interrupt(struct kvm_vcpu *vcpu) 361 { 362 __this_cpu_write(current_vcpu, NULL); 363 } 364 365 366 static inline bool kvm_pat_valid(u64 data) 367 { 368 if (data & 0xF8F8F8F8F8F8F8F8ull) 369 return false; 370 /* 0, 1, 4, 5, 6, 7 are valid values. */ 371 return (data | ((data & 0x0202020202020202ull) << 1)) == data; 372 } 373 374 static inline bool kvm_dr7_valid(u64 data) 375 { 376 /* Bits [63:32] are reserved */ 377 return !(data >> 32); 378 } 379 static inline bool kvm_dr6_valid(u64 data) 380 { 381 /* Bits [63:32] are reserved */ 382 return !(data >> 32); 383 } 384 385 /* 386 * Trigger machine check on the host. We assume all the MSRs are already set up 387 * by the CPU and that we still run on the same CPU as the MCE occurred on. 388 * We pass a fake environment to the machine check handler because we want 389 * the guest to be always treated like user space, no matter what context 390 * it used internally. 391 */ 392 static inline void kvm_machine_check(void) 393 { 394 #if defined(CONFIG_X86_MCE) 395 struct pt_regs regs = { 396 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 397 .flags = X86_EFLAGS_IF, 398 }; 399 400 do_machine_check(®s); 401 #endif 402 } 403 404 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu); 405 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu); 406 int kvm_spec_ctrl_test_value(u64 value); 407 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 408 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, 409 struct x86_exception *e); 410 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva); 411 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type); 412 413 /* 414 * Internal error codes that are used to indicate that MSR emulation encountered 415 * an error that should result in #GP in the guest, unless userspace 416 * handles it. 417 */ 418 #define KVM_MSR_RET_INVALID 2 /* in-kernel MSR emulation #GP condition */ 419 #define KVM_MSR_RET_FILTERED 3 /* #GP due to userspace MSR filter */ 420 421 #define __cr4_reserved_bits(__cpu_has, __c) \ 422 ({ \ 423 u64 __reserved_bits = CR4_RESERVED_BITS; \ 424 \ 425 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \ 426 __reserved_bits |= X86_CR4_OSXSAVE; \ 427 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \ 428 __reserved_bits |= X86_CR4_SMEP; \ 429 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \ 430 __reserved_bits |= X86_CR4_SMAP; \ 431 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \ 432 __reserved_bits |= X86_CR4_FSGSBASE; \ 433 if (!__cpu_has(__c, X86_FEATURE_PKU)) \ 434 __reserved_bits |= X86_CR4_PKE; \ 435 if (!__cpu_has(__c, X86_FEATURE_LA57)) \ 436 __reserved_bits |= X86_CR4_LA57; \ 437 if (!__cpu_has(__c, X86_FEATURE_UMIP)) \ 438 __reserved_bits |= X86_CR4_UMIP; \ 439 if (!__cpu_has(__c, X86_FEATURE_VMX)) \ 440 __reserved_bits |= X86_CR4_VMXE; \ 441 if (!__cpu_has(__c, X86_FEATURE_PCID)) \ 442 __reserved_bits |= X86_CR4_PCIDE; \ 443 __reserved_bits; \ 444 }) 445 446 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes, 447 void *dst); 448 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t src, unsigned int bytes, 449 void *dst); 450 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, 451 unsigned int port, void *data, unsigned int count, 452 int in); 453 454 #endif 455